Commit Graph

28609 Commits

Author SHA1 Message Date
Kyösti Mälkki 2fbb6773e3 arch/x86: Enforce CPU stack alignment
When rmodule is loaded CPU stack alignment is only guaranteed
to 4kiB. Implementation of cpu_info() requires that each
CPU sees its stack aligned to CONFIG_STACK_SIZE.

Add one spare CPU for the stack reserve, such that alignment can
be enforced runtime.

Change-Id: Ie04956c64df0dc7bb156002d3d4f2629f92b340e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/26302
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14 11:59:51 +00:00
John Zhao b318be2218 mb/google/octopus/variants: Disable xHCI compliance mode
Some usb devices exhibits signal loss which causes xHCI entering
compliance mode. The resolution is to disable xHCI compliance mode.

BRANCH=octopus
BUG=b:115699781
TEST=Verified usb operation successfully.

Change-Id: I41fecaa43f4b1588a0e4bbfc465d595feb54dd24
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30817
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14 11:58:47 +00:00
John Zhao 91600a3182 soc/intel/apollolake: Add option to disable xHCI Link Compliance Mode
Provide options to disable xHCI Link Compliance Mode. Default is FALSE
to not disable Compliance Mode. Set TRUE to disable Compliance Mode.

BRANCH=octopus
BUG=b:115699781
TEST=Verified booting to kernel.

Change-Id: I2a486bc4c1a8578cfd7ac3d17103e889eaa25fe4
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30816
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14 11:58:38 +00:00
Aamir Bohra e49b2f088f mb/google/hatch: Use USB2 Port 10 for BT over CnVi
Integrated BT controller in CnVi uses USB port 10 for communication.

BUG=b:122552619
TEST=lsusb shows BT device

Change-Id: Iad1ca0e9419b534f50a3ce3fdcbd660caf8efb5c
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/30809
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14 11:58:05 +00:00
Peter Lemenkov 522a1b526b mb/lenovo/[xtz]60: Introduce and use RCBA64 macro
Change-Id: I85ca631dfb01acb92dd1ac38dff07215114cab8c
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-14 11:57:25 +00:00
Peter Lemenkov e23245517b mb/lenovo/*/romstage: Use macros instead of magic numbers
Apparently coreboot still uses magic numbers instead of macros in some
Lenovo mainboards. Let's use macros instead.

Note that IOTR[0123] is a 64-bit width variable.

Change-Id: Icf185c77ede5a258fe37be9e772be6804d014b57
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-14 11:57:06 +00:00
Peter Lemenkov 7b42811fa5 sb/intel: Use common RCBA MACROs
This commit follows up on commit 2e464cf3 with Change-Id
I61fb3b01ff15ba2da2ee938addfa630c282c9870.

Change-Id: Iaf06d347e2da5680816b17f49523ac1a687798ba
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: David Guckian
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-14 11:56:38 +00:00
Patrick Rudolph aa6d388597 soc/intel/fsp_broadwell_de: Move early_mainboard_romstage_entry()
Move early_mainboard_romstage_entry before console_init.
Allows to setup a SuperIO, if any, for serial console.

Change-Id: I370263a6197a4c0c805352f07fedddbee1b8e247
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-14 09:14:01 +00:00
Patrick Rudolph 95c021b63a intel/fsp1_0: Add option to select FSP debug level
Useful for debugging FSP.

Change-Id: I06e837cf1b051c55a531c3361e94fa1449bc8526
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
2019-01-14 09:13:01 +00:00
Patrick Rudolph 79131f8323 soc/intel/fsp_broadwell_de: Fix uart
* Disable FSP serial output if not CONSOLE_SERIAL

Tested on wedge100s.

Change-Id: Idd825d2d6eb423452d3e81265860205980f6aa5b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-14 09:12:41 +00:00
Kyösti Mälkki 7d9016931c AGESA binaryPI: Consolidate ACPI for IMC
Change-Id: Ieff6041f3c9ad02f9cebae0ec83d0898abb0d601
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/18538
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14 06:55:47 +00:00
Kyösti Mälkki 24aea52e29 AGESA binaryPI: Remove unused IMC ACPI methods IMSP and IMWK
Note that IMC must sleep while SPI writes are in progress.
Instead of using these ACPI methods, flashrom currently does
raw IO to achieve the same.

Change-Id: Ifca4e8328c54d1074b4799ddecfece24607214db
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/18537
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14 06:55:15 +00:00
Kyösti Mälkki f40f209c15 binaryPI: Remove ACPI for IMC we don't run
IMC is used on some of the AMD reference designs, so do not
touch them yet.

Change-Id: I6a58ab53d4a800d4c0c2026e50826122ece2c59f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/21190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-01-14 06:54:10 +00:00
Kyösti Mälkki 51769b2f92 AGESA: Remove ACPI for IMC we don't run
IMC is used on some of the AMD reference designs, so do not
touch them yet.

Change-Id: Iae21e0294f0155f07fb4f4348ebc5b3120d50fd1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/18536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-01-14 06:53:54 +00:00
Mike Banon 7515cd0d04 AGESA/PI: replace HUDSON_DISABLE_IMC with HUDSON_IMC_ENABLE
Only a few boards are using IMC for the onboard fan control,
so regarding the availability of IMC selection it should be opt-in,
not opt-out. Also, select HUDSON_IMC_ENABLE for Gizmo 2
because Gizmo 2 could use IMC for the onboard fan control.

Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I3590b13c3b155405d61e373daf1bd82ca8e3bd16
Reviewed-on: https://review.coreboot.org/c/30756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-14 06:50:11 +00:00
Mike Banon d06d5256e2 drivers/spi/amic.c: Add the rest of >=1MB AMIC A25 chips
Required for ACPI S3 suspend support at some motherboards.
Synchronizing with flashchips.c/h flashrom source code.

Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: Ic5bd3e43e0d3fd5f454fae71b307c0682f203d5c
Reviewed-on: https://review.coreboot.org/c/30884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-14 02:25:46 +00:00
Mike Banon 8a1cbf00aa drivers/spi/adesto.c: Add the rest of >=1MB Adesto AT25 chips
Required for ACPI S3 suspend support at some motherboards.
Synchronizing with flashchips.c/h flashrom source code.

Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I8c0e6d8f1487ca90f88d4a56af3fb0e21458ef1e
Reviewed-on: https://review.coreboot.org/c/30883
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14 02:25:13 +00:00
Mike Banon 2db6e6806b drivers/spi/gigadevice.c: Add the rest of >=1MB Gigadevice GD25 chips
Required for ACPI S3 suspend support at some motherboards.
Synchronizing with flashchips.c/h flashrom source code.

Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I333c8589ddc2bece488608ff66015ca8307eae0f
Reviewed-on: https://review.coreboot.org/c/30882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-14 02:24:51 +00:00
Mike Banon 4902a802c8 drivers/spi/macronix.c: Add the rest of >=1MB Macronix MX25 chips
Required for ACPI S3 suspend support at some motherboards.
Synchronizing with flashchips.c/h flashrom source code.

Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I4508a65a5bdcbf58aadf452de5e896fc3c5b1bc3
Reviewed-on: https://review.coreboot.org/c/30877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-14 02:24:32 +00:00
Mike Banon 3c3351306c drivers/spi/spansion.c: Add more Spansion S25FL_K chips
Add S25FL208K (ID 0x4014), S25FL132K (ID 0x4016) and S25FL164K (ID 0x4017)
chips in a way similar to S25FL116K (ID 0x4015) chip from the same family.

Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I9bf7197bbc0d12797c8ed100c673628de9c140f7
Reviewed-on: https://review.coreboot.org/c/30874
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-14 02:24:13 +00:00
Matt DeVillier 1d4f936f61 google/butterfly: correct northbridge selection
butterfly is a Sandybridge device, and selecting Ivybridge
breaks libgfxinit currently due to CPU mismatch

Test: build/boot butterfly w/libgfxinit

Change-Id: I1a7f5a3681d21a256834b11b545855c4365f5f78
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30820
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-13 19:51:24 +00:00
Matt DeVillier e2c4a3518e google/butterfly: add cpu/gpu pwm backlight register values
Required for functional internal display on butterfly using libgfxinit.

Test: boot/build butterfly, verify internal display functional
prior to OS driver loading.

Change-Id: Ib8060f2d1ad0694f0886d35c83763907f61b47b1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30819
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-13 19:51:10 +00:00
Elyes HAOUAS c2c1dc9c76 {mb,nb,soc/fsp_baytrail}: Get rid of dump_mem()
Use hexdump() instead of dump_mem().

Change-Id: I7f6431bb2903a0d06f8ed0ada93aa3231a58eb6f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Guckian
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-13 16:24:31 +00:00
Nico Huber 15b83da39a nb/intel/x4x: Remove spurious pcidev_on_root() usage
It's supposed to be the same device that is passed to the executing
function.

Change-Id: I6cf994390c16e0393c96a2b2e04a36305be88e68
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/30880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-13 14:01:19 +00:00
Nico Huber 4e008c699b nb/intel/i945: Reduce pcidev_on_root() calls
Also removes one call for 0:2.0 (integrated graphics) that might be
disabled.

Change-Id: I494aa366030b77baf431f29ba331f13f7c567025
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/30881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-13 14:00:54 +00:00
Nico Huber 744d6bd638 sb/intel: Check for NULL-return of pcidev_on_root()
In these cases we have to expect a NULL pointer because the IGD
device 0:2.0 may be disabled.

The behaviour still differs from using dev_find_slot(), which may
return a disabled device. Though, if you'd try to read its config
space you'd only read garbage (0xff) and in cases where we filled
ACPI data with devicetree information, the information shouldn't
be interpreted by the OS because of the disabled device.

Change-Id: I1bab8fa3a82daca71d03453315cdd69d8951fc24
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/30879
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-13 14:00:33 +00:00
Kyösti Mälkki 8c1258ab8b usbdebug: Remove option DEBUG_USBDEBUG
Superseeded with DEBUG_CONSOLE_INIT.

For dbgp_print_data() return early and skip reading
registers when dprintk() would not get printed anyways.

Change-Id: Idf470b8572ad992c8d4684a860412d9140f514ca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-13 13:02:23 +00:00
Kyösti Mälkki 6627795289 console: Add Kconfig debug option DEBUG_CONSOLE_INIT
Under normal circumstances no printk() goes through until
console_hw_init() has completed. This is wanted behaviour,
except when you need to debug the setup of one of consoles.

Change-Id: Ifc2bb22bf930009ee229d4461f512ada3018307b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-13 13:01:42 +00:00
YH Lin 67618dd250 mb/google/kukui: add flapjack on top of kukui
Add placeholder for future flapjack additions/modifications.

BUG=None
BRANCH=kukui
TEST=build with kukui/flapjack configurations
Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: Ib9cd39e284f19b9179da73ed9f2b13d97442960e
Reviewed-on: https://review.coreboot.org/c/30859
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-13 11:34:31 +00:00
Kyösti Mälkki 0377a369b9 aopen/dxplplusu: Switch to C_ENVIRONMENT_BOOTBLOCK
This board is the only user of these ancient chipsets,
so we'll do all in one go.

Also wipe out some extra headers.

Change-Id: I22c172d577e6072562d8fcfa58145ec62473823e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-13 08:38:13 +00:00
Kyösti Mälkki 34856579f8 arch/x86: Drop Kconfig AP_SIPI_VECTOR
This was used to check romcc-built bootblock and romstage
agree about the location of 16-bit entrypoint. There was
no need to customize it as bootblock size requirement did
not grow. Just check for a fixed location at 4 GiB - 4 KiB.

With C_ENVIRONMENT_BOOTBLOCK we can have a proper symbol
for the purpose, since it appears in the same compilation
unit. It will adjust if C_ENV_BOOTBLOCK_SIZE changes.

Change-Id: I93f3c37e78ba587455c804de8c57e7e06832a81f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-01-13 08:37:01 +00:00
Arthur Heymans 95b3ba5264 cpu/intel/car/p4: Update microcode in CAR setup
This updates the BSP microcode during CAR setup.

Change-Id: I87d34cf38dbd700ecb04d87c5b4767910e4a922c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30682
Reviewed-on: https://review.coreboot.org/c/30777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-13 08:36:08 +00:00
Lijian Zhao f9154c5cc6 soc/intel/cannonlake: Hook up Microcode
Hook Coffeelake U43e and Coffeelake H/S/E3 microcode into SOC and remove
the MICROCODE_BLOB_NOT_HOOKED_UP.

BUG=N/A
TEST=Boot up with coffeelake rvp board and check microcode revision in
coreboot log.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I6593081374dd4898a82db5b43c3b5bf154b3ef60
Reviewed-on: https://review.coreboot.org/c/30864
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-12 23:12:11 +00:00
Gaggery Tsai 3afb84a245 src/drivers/intel/wifi: Add a W/A for Intel ThP2 9260
This patch adds a workaround for ThP2. The PCIe root port LCTL2.TLS
is by default GEN1 and ThP has bad synchronization on polarity
inversion. When the root port request for speed change, ThP doesn’t
confirm the request, and both sides are moving to polling after
timeout, hot reset is issued, and then most of the CFG space is
initialized. From the observation, CCC/ECPM/LTR would be reset to
default but CCC/ECPM of root port and end devices have been
reconfigured in pci_scan. The LTR configuration for root port
is still missing.

BUG=B:117618636
BRANCH=None
TEST=Warm/cold reset for 10 times and didn't see unsupported request
     related AER error messages & $lspci -vvs 00:1c.0|grep LTR and
     ensure LTR+ is presenti & $iotools pci_read32 0 0x1c 0 0x68
     and ensure bit10 is set.

Change-Id: Id5d2814488fbc9db927edb2ead972b73ebc336ce
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/30486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-11 23:42:39 +00:00
Lijian Zhao 64925b5128 soc/mainboard: Update mainboard UART Kconfig
After f5ca922 (Untangle CBFS microcode updates) got merged, all
mainboard using intel apollolake, cannonlake, coffeelake, glk,
kabylake, skylake, icelake and whiskeylake get affected.
Using INTEL_LPSS_UART_FOR_CONSOLE instead of UART_DEBUG
and set default console for each platform.

BUG=N/A
TEST=Build and test on Sarien platform, by default we can still get
console from cbmem, and enable CONSOLE_SERIAL can get logs from UART
port 2.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I550a00144cff21420537bb161c64e7a132c5d2de
Reviewed-on: https://review.coreboot.org/c/30853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-11 18:59:21 +00:00
Mario Scheithauer dd217362d4 siemens/mc_apl1: Use INTEL_LPSS_UART_FOR_CONSOLE
With the commit a96e66a (soc/intel: Clean mess around UART_DEBUG), an
adjustment is necessary for this mainboard.

Change-Id: I0fb6288959f8bcb45c4cc93cc132f31a5ab2a5ad
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-11 18:54:56 +00:00
Patrick Georgi 5ce73e9836 util/crossgcc: derive date and version from latest commit
This way date and version are automatically updated when util/crossgcc
was changed, the version contains the commit ID and we have less churn
on these variables.

Change-Id: I475ba9578a8bb421d7c342d2569d7de7fcf4161d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-01-11 14:55:39 +00:00
Paul Menzel e0368b434e Revert "cpu/amd: Use `get_option()`"
This reverts commit 6fffd70435.

Doing more tests on the Asus KGPE-D16, it seems to cause a reboot loop
quite often. Therefore, revert the commit.

The problem might be caused by the spinlocks used by `get_option()`, and
which are not used by `read_option()`.

Change-Id: Ic25129aa71c8e8e40a65bb2658de78005766fea8
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/30830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-11 14:33:39 +00:00
Nico Huber da8c12b54f console/Kconfig: Fix dependency of FIXED_UART_FOR_CONSOLE
The Kconfig declaration for FIXED_UART_FOR_CONSOLE was accidentally
placed inside an `if CONSOLE_SERIAL` in a96e66a (soc/intel: Clean mess
around UART_DEBUG).

TEST=Start a clean config, select intel/leafhill and disable serial
console. Confirm that config can be saved without error.

Change-Id: Ie41687e91af11a13697cbe25938dada2c74b40fb
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/30829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-11 14:04:38 +00:00
Arthur Heymans 804adaa1f1 arch/x86/ebda: Don't trash the EBDA on the resume path
Clearing the EBDA was introduced with b4aaaa "Prepare the BIOS data
areas before device init." which states that the purpose of setting up
these area's is just to make sure they are sane. On the S3 path doing
this is not needed and can even thrash data set up by payloads (mostly
SeaBIOS) that used that memory.

Change-Id: I9c54156bd8247e8a34dec6edc27cfc2d33cde595
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-11 13:43:55 +00:00
Arthur Heymans c6bf74ec75 cpu/intel/microcode: Support update before CAR entry
Change-Id: Ie3c2d2e1bc79dcaffd9901e17f83ceeaabd1d659
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-11 10:19:16 +00:00
Kyösti Mälkki a706ad5444 arch/x86/lapic: Remove second stack poisoning
It was already done once in c_start.S.

Change-Id: I1cb0ea25251644dbd1127d177247a02ba52bb550
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-01-11 00:53:51 +00:00
Jett Rink 2dbe51a17c mainboard/google/octopus: configure EC_AP_INT_ODL
Enable the EC_AP_INT_ODL interrupt on GPIO_134 for all octopus boards
that support it. Also removing unnecessary IO standby support since we
don't use this pin to wake up the SoC.

BRANCH=octopus
BUG=b:122552125,b:120679547
TEST=CTS tests with changes

Change-Id: I018864ae5fa400372b5b443e49828e8202b9aa4d
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30788
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-10 19:01:54 +00:00
Nico Huber 835f5cf23a soc/intel/fsp_broadwell_de: Drop MICROCODE_BLOB_NOT_HOOKED_UP
It's been hooked up in the meantime.

Change-Id: I64176b09e375034189000ea4308c58771f0019a1
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/30812
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-10 16:11:36 +00:00
Kyösti Mälkki ef62994b94 northbridge/amdfam10: Deal with PCI_ADDR() better
PCI_ADDR() is tightly coupled with different setup_resource_map()
variants so move the declaration away from global namespace.

In the implementation of setup_resource_map() use the bottom
12 bits as the register mask like the other variants do already.

Change-Id: Iadedfe993621a4458ce8f12c5e98c8cee537d2db
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30784
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-10 13:40:57 +00:00
Kyösti Mälkki 20c294884f amdfam10 boards: Simplify early resourcemap
Purpose of the table is to load initial address maps
on PCI function 0:18.1. Provide a macro of its own so
it is clear no other PCI devfn is accessed here.

Change-Id: Ic146207580a5625c4f6799693157b02422bef00a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30783
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-10 13:40:40 +00:00
Kyösti Mälkki 934156694f sb/nvidia/mcp55: Avoid confusion with PCI_ADDR()
What you see in the table are not the PCI devices
that will be written to. Use a helper MCP55_DEV()
to make you look twice what is actually done.

Change-Id: I1349af9f734aaabb576d1370ae29a56c91569a7c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-10 13:40:27 +00:00
Kyösti Mälkki 43997b7aa3 sb/nvidia/ck804: Avoid confusion with PCI_ADDR()
What you see in the table are not the PCI devices
that will be written to. Use a helper CK804_DEV()
to make you look twice what is actually done.

Change-Id: I0ee244dacd6bbd0a88a5e6a5c634f381b0cf713d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-10 13:40:16 +00:00
Kyösti Mälkki 22521ab2e6 amdfam10 boards: Drop extern on apicid_sp5100
The value get_bus_conf() initialises this value to is
discarded.

Change-Id: I8382861574e6f8ab52839169502a5af7c3742daa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-01-10 13:40:04 +00:00
Patrick Georgi 4b2553eea5 soc/intel/cannonlake: complete rename of TCO2_STS_SECOND_TO
TCO2_STS_SECOND_TO was renamed to TCO_STS_SECOND_TO but one use
slipped through.

Change-Id: I9e3b1cc5cb2f319db35416edf6cea612d755d40a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30805
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-10 13:34:52 +00:00