2 commits

Author	SHA1	Message	Date
Lijian Zhao	9b50a57e43	soc/intel/cannonlake: Program DMI PCR settings ... According to CNL PCH BIOS spec (570374) 2.4.1, DMI cycle decoding needs to be programmed before it gets locked. Update lpc programming to add decode programming on DMI side as well. Also enabled io port 0x200 decoding by default. BUG=b.70765863 TEST=Apply changes and add chromeos EC decoding in mainboard devicetree.cb, then read back IO port in depthcharge cli and check that return is not zero. Change-Id: I6b8f393c92cbd0632fed86212ae384ff53c9f8c3 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>	2018-01-16 19:40:00 +00:00
Lijian Zhao	a515849259	soc/intel/cannonlake: Add lpc pci driver ... 1.Add common ITSS support as part of LPC driver init code. 2.Add LPC pci driver for CNL Change-Id: I6c810fd7158e1498664b77eecae22132e2f6878f Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>	2017-10-03 20:23:32 +00:00