Update the fields that need to be updated directly in the local static
usb_phy_config struct instead of dereferencing the pointer written to
the corresponding UPD field. This will allow updating the type of UPD
field in a follow-up commit to enable 64 bit coreboot builds.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I44a9fe719e6803fc957fee3db13b261489ed313d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69896
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This ports forward part of commit df09680626 ("soc/amd/picasso: Add
support for 64bit builds") to the newer AMD SoCs.
Use -Wl instead of -l to get the output format that the commands in the
Makefile expect to extract the value for PSP_BIOSBIN_SIZE. Without this
change, readelf will split the output into two lines in case of a 64 bit
coreboot build. This results in invalid amdcompress and amdfwtool
command lines which will cause the amdfwtool call to fail with
Error: BIOS binary destination and uncompressed size are required
With the old readelf -l command we get this output in a 64 bit build:
Program Headers:
Type Offset VirtAddr PhysAddr
FileSiz MemSiz Flags Align
LOAD 0x0000000000000080 0x0000000002030000 0x0000000002030000
0x0000000000010000 0x0000000000010000 RWE 0x10
while we get the correct output in a 32 bit build:
Program Headers:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
LOAD 0x000060 0x02030000 0x02030000 0x10000 0x10000 RWE 0x20
With readelf -Wl we also get the expected output in a 64 bit build:
Program Headers:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
LOAD 0x000080 0x0000000002030000 0x0000000002030000 0x010000 0x010000 RWE 0x10
TEST=This fixes the 64 bit build on Cezanne with some follow-up patches
applied.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I35f9feda4d0da3546592dfac233ca66732bd5464
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69895
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Use the newly added functions to iterate over the FSP HOBs to report the
resources used by FSP to the resource allocator instead of open coding
the iteration over the HOBs in the SoC code.
TEST=Patch doesn't change reported resources on Mandolin
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I67ca346345c1fa08b008caa885d0a00d2d5afb12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Use VBOOT_STARTS_BEFORE_BOOTBLOCK to determine whether the VERSTAGE
needs to be build as x86 stage.
Change-Id: I126801a1f6f523435935bb300f3e2807db347f63
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
When no HOB list is found, not only adding the resources reported by the
FSP were skipped, but also adding the GNB IOAPIC resource was skipped.
Fix this bug by moving the reporting of the GNB IOAPIC resource before
the resources reported in the FSP HOBs to not skip the IOAPIC resource
when there's no HOB list.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9174c8d7e5e94144187d27210e12f2dca3a6010f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69460
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It is no longer necessary to explicitly add "ERROR: "/"WARNING: " in
front of every BIOS_ERR/BIOS_WARN message.
Change-Id: I22ee6ae15c3d3a848853c5460b3b3c1795adf2f5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Use the common device ops instead of an soc-specific device ops.
TEST=builds for each soc
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I1804200c3c3f5ab492d237f4b03484c383862caf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Morgana/Glinda have a different register mapping for data fabric access,
although the registers themselves are mostly compatible. The register
layouts defined by each soc capture the differences and the common code
can use those.
Move the register offsets to soc headers and update the offsets for
morgana/glinda per morgana ppr #57396, rev 1.52 and glinda ppr #57254,
rev 1.51
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I9e5e7c85f99a9afa873764ade9734831fb5cfe69
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This change disables support for memory types not used by each of the
chips. This will in turn remove the files for those memory types from
the platform builds.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8c7f47b43d8d4a89630fbd645a725e61d74bc2a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add structs to define the data_fabric register bitfields, updated per
glinda ppr #57254, rev 1.51
Update IOMS0_FABRIC_ID and DF_MMIO_NP per referenced ppr.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I509eaf5910d8d65ce0956200d7c00451ff9ce864
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The data_fabric_set_mmio_np function is effectively identical, so move
it to common code.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I58e524a34a20e1c6f088feaf39d592b8d5efab58
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Don't set bit 2 in _STA in order for Windows not to show a warning about
an unknown device in the device manager for this device. Since the _STA
object just returns a constant, a name definition can be used instead of
a method definition.
TEST=The unknown device with device instance path ACPI\AAHB0000\0
disappeared from the device manager in Windows 10 build 19045 on a
Mandolin board with a Picasso APU.
Just shutting down and then booting it again won't clear some internal
state in Windows, so a reboot is needed instead for the change to become
visible.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8cb1712756c3623cc3ea16210af69cde0fa18f62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
CB:66943 - commit 8d66fb1a70 (soc/amd: Add amdfw.rom in coreboot.pre)
changed the build flow for the amd firmware binary after glinda was
branched from morgana. Update glinda to match the other SoCs.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I5b0ccaa8c33e59f7146edd6a86f107480c152008
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This adds the initial framework for the Glinda SoC, based on what's been
done for Morgana already.
I believe that there's more that can be made common, but that work will
continue as both platforms are developed.
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I43d0fdb711c441dc410a14f6bb04b808abefe920
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
