Commit Graph

7878 Commits

Author SHA1 Message Date
Gabe Black d8d4d113f0 libpayload: If there's no IO space, complain if the serial claims to use it
Change-Id: I36c750d520ff034c9ca9b9af46bd99bd49af7355
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/2659
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-13 23:04:54 +01:00
Gabe Black 1c1171208f libpayload: Consolidate io vs. mem mapped serial into accessor functions
This way we won't have two copies of the hardware init function, and three
copies of the putchar, havechar, and getchar functions.

Change-Id: Ifda7fec5d582244b0e163ee93ffeedeb28ce48da
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/2657
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-13 23:04:29 +01:00
Gabe Black d267987083 libpayload: Make whether or not there's an IO address space configurable
Default it to no to be consistent with the other architecture wide options
(endianness), and turn it on explicitly for x86 and PowerPC.

Change-Id: Idda26d580156bbbf08ea11b28abe75cfa6b594b2
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/2658
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-13 23:02:05 +01:00
Stefan Reinauer ffc13bdb2a Update 3rdparty mark to latest repository
For google/stout binaries

Change-Id: I4ef3f9cc35dfb6d27e1c9f074759f0e3ddee73c4
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2635
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-13 23:00:49 +01:00
Ronald G. Minnich ba949d32ba libpayload: Start using only internal and compiler headers.
When building other payloads with lpgcc the -nostdinc flag was injected into
CFLAGS, but when building libpayload itself some headers were being used from
the host system. This change puts -nostdinc into the Makefile and xcompile
script, fixes up one include path in include/inttypes.h, adds the compiler
provided include directory to the include search path, and deletes the two now
redundant stdint.h files.

BUG=None
TEST=With this and other changes, built libpayload and depthcharge for Daisy,
Link, and Fox.
BRANCH=None

Change-Id: Ia7817fceab5297cd82ccc0d392330de0df61980e
Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2710
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-13 22:04:44 +01:00
Gabe Black 2def2625e0 libpayload: Add more parenthesis to the endian conversion macros
There weren't enough parenthesis in the macros so operations might only apply
to the last part of an expression passed in as an argument.

Change-Id: I5afb406f9409986e45bbbc598bcbd0dd8507ed35
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/2665
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-13 19:12:31 +01:00
Gabe Black b53a73ef77 libpayload: Make the source for lzma decompression const
Change-Id: I9a16331dedc97f17af94bf2cf535a9c93d1729a0
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/2667
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-03-13 18:16:35 +01:00
Paul Menzel aeda4b8c0a src/mainboard: Drop redundant `CHIP_NAME` again for new ports
Since commit »Drop redundant CHIP_NAME in mainboard.c« (a93c3fe7) [1]
`CHIP_NAME` is unneeded for mainboards as the name is composed
automatically in `src/devices/root_device.c` from the strings in
Kconfig.

Unfortunately the ports for Google Butterfly, Link and Parrot as
as well as IEI PM-LX2-800-R10 introduced CHIP_NAME again. So drop
it again too.

[1] http://review.coreboot.org/1635

Change-Id: Ice7577a2a5c6070e196f2647c440b7a8e140e27e
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2708
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-13 17:39:58 +01:00
Hung-Te Lin e112b746e0 libpayloads: Provide BSD/glibc style endian functions.
The functions in endian.h (betoh{l,w,ll} and others) were named differently from
the well-known BSD/glibc style endian functions (ex, betoh{16,32,64}). We should
provide the BSD/glibc style functions to prevent confusion.

Change-Id: Ia3bee481ba7989ac25b79ddb89bc6819d52fd8c3
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2705
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-13 17:37:09 +01:00
David Hendricks a0996a9c7c exynos5250: Don't set PS_HOLD in bootblock_cpu_init
PS_HOLD gets set in exynos' power_init().

Change-Id: Ib08e0afcad23cbd07dc7e3727fd958a1bc868b5a
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2700
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-13 16:55:54 +01:00
David Hendricks d2bed05e6a exynos5250/snow: call PMIC's power_init() function
Call the power_init() function. We appear to have forgotten about it
when deprecating lowlevel_init_subsystems(), but it didn't seem to
cause problems until we got to doing more interesting stuff recently.

There are some clean-ups to do from the original code, such as not
attempting to configure I2C from PMIC code, which we'll get around
to in follow-up patches.

(Credit to Gabe for spotting this)

Change-Id: I6a59379e9323277d0b61469de9abe6d651ac5bfb
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2699
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-13 16:55:33 +01:00
Gabe Black e0c974185c libpayload: Remove unnecessary include of arch/msr.h
The functions defined in that header aren't used anywhere in the actual code,
and that include breaks things on ARM.

Built for ARM with COREBOOT_VIDEO_CONSOLE turned on and saw compiler
errors go away.

Change-Id: I56d6fe5e00c8fccda6e31ef8752326bd36398e74
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/2656
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-03-12 23:56:43 +01:00
Gabe Black 2c2c4fae22 libpayload: In the USBMSC read_capacity function, make buf an array of u32.
That way when it's treated as a u32 when its value is extracted for numblocks
and blocksize below, it doesn't make the compiler unhappy, and it ensures that
the buffer will be properly aligned on architectures where that sort of thing
matters.

Built and saw warnings about type punning go away.

Change-Id: I254e0b5e70847112d660675b7df0ac9cb52e4051
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/2653
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-03-12 23:56:16 +01:00
Paul Menzel ee5c111755 AMD CIMx SB800: Enable AHCI mode for SATA controller by default
The current default is IDE mode which is slower compared to AHCI
mode. Therefore use AHCI mode by default.

A similar change was made for AMD Persimmon in commit
»Enable SATA AHCI for faster boot with SeaBIOS.« (96be74c7) [1]
but was indirectly reverted by »sb800: Add sata ahci/raid mode
kconfig option« (d4a0e7d0) [2].

[1] http://review.coreboot.org/220
[2] http://review.coreboot.org/225

Change-Id: I4fa31b0a3280891e7a3f37675ae8415205818947
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2661
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-12 22:52:44 +01:00
Patrick Georgi 5021209f5a watchdog.h: Fix compile time error on disabling watchdog handling
There's a compile time error that we didn't catch since the
board defaults as used by the build bot won't expose it.

Just make watchdog_off() a no-op statement so there aren't any
stray semicolons in the preprocessor output.

Change-Id: Ib5595e7e8aa91ca54bc8ca30a39b72875c961464
Reported-by: 'lautriv' on irc.freenode.net/#coreboot
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2627
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-03-12 12:06:43 +01:00
Patrick Georgi db2e3aa257 libpayload: Fix reading x86 CBFS images from RAM
Three issues:
 1. the hardcoded dereferenced pointer at 0xfffffffc
 2. "RAM media" has no idea about ROM relative addresses
 3. off-by-one in RAM media: it's legal to request 4 bytes from 0xfffffffc

Change-Id: I671ac12d412c71dc8e8e6114f2ea13f58dd99c1d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2624
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2013-03-12 10:23:12 +01:00
Vadim Bendebury 6e7abcd4b5 Fix 'git describe' invocation
The 'git describe' command is used to obtain the source tree status
information when building coreboot. As used this command expects git
tags to be defined, so it can report the discrepancy between the
current state of the tree and the latest tag.

The problem is that the coreboot source tree does not have any git
tags defined, so when 'git describe' is invoked, it reports "fatal: No
names found, cannot describe anything.". This scary message can be
seen on the console during coreboot builds.

The solution is to add --always to the `git describe' invocation,
which causes it to report the discrepancy with the latest sha1, if
any, which is better than nothing.

  $ rm -rf /tmp/li && mkdir /tmp/li
  $ cp configs/config.link .config
  $ make obj=/tmp/li oldconfig
  $ make obj=/tmp/li
  $ grep COREBOOT_VERSION /tmp/li/build.h
  #define COREBOOT_VERSION "1623c06"
  $ echo '#' >> Makefile.inc
  $ grep COREBOOT_VERSION /tmp/li/build.h
  $ make obj=/tmp/li
  #define COREBOOT_VERSION "1623c06-dirty"
  $ git checkout Makefile.inc

Change-Id: Ia77428b7cd765cbbd59bdbf8251b7bef489d47a5
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/2637
Tested-by: build bot (Jenkins)
2013-03-12 10:22:44 +01:00
Patrick Georgi 68daf3a875 pci.h: Drop unused `mainboard_pci_subsystem*` prototypes
We used to allow mainboards to override subsystems using
mainboard_pci_subsystem_vendor_id and mainboard_pci_subsystem_device_id.

Mechanisms have changed and the only occurrence of these names is in
the header.

Change-Id: Ic2ab13201a2740c98868fdf580140b7758b62263
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2625
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2013-03-11 15:04:37 +01:00
Paul Menzel ce8410e1d3 ASUS M5A88-V: Kconfig: Fix mainboard model name
Despite everywhere the model name M5A88-V is used, in Kconfig the
string M5A88PM-V is used. Searching for that model string on the
WWW does not return anything which is unrelated to coreboot, so
change that string to M5A88-V.

Change-Id: I25cf9d4a5fc3f9b9356e8616452066ebf873f44c
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2613
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: QingPei Wang <wangqingpei@gmail.com>
2013-03-11 07:29:53 +01:00
Marc Jones e7ae96f488 Add Intel Panther Point USB3 initialization
Add PEI updates and ACPI updates for supporting EHCI to XHCI
USB port support.

Change-Id: I9ace68a1b3950771aefb96c1319b8899291edd9a
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/2519
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-03-09 00:09:37 +01:00
Mike Loptien 4733c647bc Persimmon DSDT: Add secondary bus range to PCI0
Adding the 'WordBusNumber' macro to the PCI0
CRES ResourceTemplate in the Persimmon DSDT.
This sets up the bus number for the PCI0 device
and the secondary bus number in the CRS method.
This change came in response to a 'dmesg' error
which states:
'[FIRMWARE BUG]: ACPI: no secondary bus range in _CRS'

By adding the 'WordBusNumber' macro, ACPI can set
up a valid range for the PCIe downstream busses,
thereby relieving the Linux kernel from "guessing"
the valid range based off _BBN or assuming [0-0xFF].
The Linux kernel code that checks this bus range is
in `drivers/acpi/pci_root.c`.  PCI busses can have
up to 256 secondary busses connected to them via
a PCI-PCI bridge.  However, these busses do not
have to be sequentially numbered, so leaving out a
section of the range (eg. allowing [0-0x7F]) will
unnecessarily restrict the downstream busses.

This change will apply to other AMD mainboards and
will be in a different commit.

Change-Id: I44f22bc03a0dcbcd2594d4291508826cc2146860
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2592
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-08 23:59:13 +01:00
David Hendricks ae0e8d3613 Eliminate do_div().
This eliminates the use of do_div() in favor of using libgcc
functions.

This was tested by building and booting on Google Snow (ARMv7)
and Qemu (x86). printk()s which use division in vtxprintf() look good.

Change-Id: Icad001d84a3c05bfbf77098f3d644816280b4a4d
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2606
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-08 23:14:26 +01:00
Kimarie Hoot 31c5e07a04 AMD Inagua: Use SPD read code from F14 wrapper
Changes:
 - Get rid of the inagua mainboard specific code and use the
   platform generic function wrapper that was added in change
   http://review.coreboot.org/#/c/2497/
   AMD f14: Add SPD read functions to wrapper code

 - Move DIMM addresses into devicetree.cb

 - Add the ASF init that used to be in the SPD read code into
   mainboard_enable()

Notes:
 - The DIMM reads only happen in romstage, so the function is not
   available in ramstage.  Point the read-SPD callback to a generic
   function in ramstage.

Change-Id: Id05227fcf18c6ab94ffe1beb50b533ab7b0535db
Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
Reviewed-on: http://review.coreboot.org/2607
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-03-08 22:33:57 +01:00
Paul Menzel a5ddac02f4 AMD CIMx SB800 boards: platform_cfg.h: Integrate Kconfig SATA Mode choice
Currently for Advansus A785E-I, ASRock E350M1 and ASUS M5A88-V
despite what is chosen in Kconfig »Chipset« menu item,

    $ more .config
    […]
    # CONFIG_ENABLE_IDE_COMBINED_MODE is not set
    CONFIG_IDE_COMBINED_MODE=0x1
    # CONFIG_SB800_SATA_IDE is not set
    CONFIG_SB800_SATA_AHCI=y
    # CONFIG_SB800_SATA_RAID is not set
    CONFIG_SB800_SATA_MODE=0x2
    […]

the SATA controller is put into IDE mode.

    $ lspci -nn | grep SATA
    00:11.0 SATA controller [0106]: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 SATA Controller [IDE mode] [1002:4390] (rev 40)

Commit »sb800: Add sata ahci/raid mode kconfig option«
(d4a0e7d0) [1] added the options above to configure the mode
using Kconfig and some SB800 boards were adapted already. For
example commit »persimmon: sb800 sata mode configure update«
(1386fa74) [2] did so for AMD Persimmon.

Doing the same by assigning the Kconfig variable to the value in
`platform_cfg.h` integrates this with the three remaining boards
listed above.

The patch is successfully tested with the ASRock E350M1.

    $ lspci -nn | grep SATA
    00:11.0 SATA controller [0106]: Advanced Micro Devices [AMD] nee ATI SB7x0/SB8x0/SB9x0 SATA Controller [AHCI mode] [1002:4391] (rev 40)

[1] http://review.coreboot.org/225
[2] http://review.coreboot.org/227

Change-Id: I227257e2c8f04f18c27ff00fe62d42e372de67e4
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2610
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-03-08 22:25:12 +01:00
Paul Menzel b55b74fc24 AMD Persimmon: mainboard.c: Make comment generic to reduce difference
Replace »persimmon« by »board« in comment to keep `diff` output
between boards small.

Change-Id: Ieae2a63782c488ae35f22eb30f5b1049200d12c8
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2611
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-03-08 22:23:10 +01:00
Kimarie Hoot 9ca4f51bd4 AMD Union Station: Use SPD read code from F14 wrapper
Changes:
 - Get rid of the union_station mainboard specific code and
   use the platform generic function wrapper that was added
   in change http://review.coreboot.org/#/c/2497/
   AMD f14: Add SPD read functions to wrapper code

 - Move DIMM addresses into devicetree.cb

 - Add the ASF init that used to be in the SPD read code into
   mainboard_enable()

Notes:
 - The DIMM reads only happen in romstage, so the function is not
   available in ramstage.  Point the read-SPD callback to a generic
   function in ramstage.

Change-Id: I19d6b0d674b67294519383f80928471b37da1e14
Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
Reviewed-on: http://review.coreboot.org/2609
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-03-08 22:18:50 +01:00
Kimarie Hoot a2f8eb98f5 AMD South Station: Use SPD read code from F14 wrapper
Changes:
 - Get rid of the south_station mainboard specific code and
   use the platform generic function wrapper that was added
   in change http://review.coreboot.org/#/c/2497/
   AMD f14: Add SPD read functions to wrapper code

 - Move DIMM addresses into devicetree.cb

 - Add the ASF init that used to be in the SPD read code into
   mainboard_enable()

Notes:
 - The DIMM reads only happen in romstage, so the function is not
   available in ramstage.  Point the read-SPD callback to a generic
   function in ramstage.

Change-Id: If4291d25ea81bf375f55b64c07c223a847a211d0
Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
Reviewed-on: http://review.coreboot.org/2608
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-03-08 22:16:30 +01:00
Ronald G. Minnich b21eaa74a6 ARMV7 and Google/Snow: Add exception support code to the ramstage
This is previously used exception code from libpayload.
On startup it installs and then tests an exception handler.
The test is an unaligned memory operation.

Yes, we've seen what might be exceptions in the ramstage, and
it makes sense to handle them. This code is identical in structure
and operation to the previously committed payload exception handler,
though we reserve the right to change it as circumstances require.

The remaining question is whether we need it in romstage.

Change-Id: I24484686c33c9757af8ba171ebae9773828fb69d
Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2614
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-03-08 22:03:37 +01:00
Konstantin Aladyshev c2f2bd0a6d AGESA: Fix CR0_PE bit define
AGESA code has wrong definition of CR0_PE bit (1 instead of 0).

PE [Protected Mode Enable] is 0 bit in CR0 register
(If PE=1, system is in protected mode, else system is in real mode)

Bit 1 is MP [Monitor co-processor]
(Controls interaction of WAIT/FWAIT instructions with TS flag in CR0)

System uses CR0_PE define, but I didn't expect any consequences because of this bug.

Change-Id: I54d9a8c0ee3af0a2e0267777036f227a9e05f3e1
Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/2591
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-08 07:30:06 +01:00
Konstantin Aladyshev 4c1e906e36 Supermicro H8QGI: set up right frequency limits for memory controller
According to BKDG:
"Memory controller (MCT) and DRAM controllers (DCTs) additions:
• Support for 933 MHz (1866 MT/s) MEMCLK frequency."

Change-Id: I6f307ce3fcb355d5445f1ea86def73a41b928a57
Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/2589
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-08 07:27:51 +01:00
Konstantin Aladyshev 7fcbbb09fd AGESA: Fix bug in AMD_DISABLE_STACK_FAMILY_HOOK_F15
_RDMSR instruction loads the contents of a 64-bit model specific register (MSR)
specified in the ECX register into registers EDX:EAX.
The EDX register is loaded with the high-order 32 bits of the MSR
and the EAX register is loaded with the low-order 32 bits.

EDX:EAX = MSR[ECX]

So bit 49 will be contained in EDX register.

Buggy code instead of bit 49 (CombineCr0Cd) sets bit [49-32=17] (PfcStrideDis).
PfcStrideDis bit disables stride prefetch generation. This leads to memory
bandwidth loss.

_________

Supermicro H8QGI board

After applying this change i observed huge memory bandwidth increase in tests
that runs on small amount of cores. But unfortunately it doesn't affect
overall bandwidth results on 4P system with 48 cores.
So i think that in this system leading limiting factor is
AMD HT-ASSIST feature (Probe filter).

But right now it is not working. System stucks in Linux boot. I have done
some experiments and figured out that stuck happens when system have cores in
compute unit (CU) other than CU with BSC (boot strap core).
CU is two cores (primary and seconary) that shares some things (L2 cache, FPU ...)
So with probe filter i can boot Linux with one (BSC)
or two (BSC + secondary core in its CU) cores.
And with this configuration i can see memory bandwidth on 1 core (or two cores)
close to original bios.

Change-Id: I5a95f5b753d600c70d3c93d36fecc687610c61cd
Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/2588
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-08 07:25:15 +01:00
Jens Rottmann 00d673d165 FrontRunner/Toucan-AF: lower SPI speed to 22 MHz
The Hudson-E1's default SPI speed for normal i.e. non-fast reads is 66 MHz,
but the SST 25VF032B datasheet allows max. 25.  Lower the speed to 22 MHz,
otherwise BIOS flashing fails.

Change-Id: I22e87d833a3ebd316b6e873595a2480831533ab1
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-on: http://review.coreboot.org/2605
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-03-08 00:56:19 +01:00
Martin Roth 45f72ce60f AMD Persimmon: Use SPD read code from F14 wrapper
Changes:
 - Get rid of the persimmon mainboard specific code which has been
   moved into the wrapper as a platform generic function in change
   http://review.coreboot.org/#/c/2497/
   AMD f14: Add SPD read functions to wrapper code

 - Move DIMM addresses into devicetree.cb

 - Add the ASF init that used to be in the SPD read code into
   mainboard_enable()

Notes:
 - The DIMM reads only happen in romstage, so the function is not
   available in ramstage.  Point the read-SPD callback to a generic
   function in ramstage.

Change-Id: I5f017dbb8dee5a09ec19734a6069ff9b71a6ab50
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2500
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-07 18:29:38 +01:00
Martin Roth 3b2653b1fc AMD Fam14: Add SPD read functions to wrapper code
Change:
This is the initial step for moving the AMD F14 & HUDSON1,2,3
SPD-read callout out of the mainboard directories and into
the wrapper.  The next step is to update the platforms to use
this routine in BiosCallouts.c and to delete the code from the
mainboard directories.  The DIMM addresses should be moved into
devicetree.cb.
If there are significant differences or reasons that the mainboard
needs to override this code, it's perfectly reasonable to keep using
the version in the mainboard, but this allows us to remove duplicated
code and simplify the mainboard directories.

Notes:
This started by duplicating what was in Persimmon, and was changed to
use the devicetree.cb structures.  The ASF setup was also removed from
the persimmon copy (PMIO writes to 0x28 & 0x29) as that's not needed
for the SPD access and doesn't make sense to initialize here.
Significant cleanup and magic number reduction was done as well.

It is intended that this file will not be included in ramstage as
the DIMM init is all done in romstage.

This is similar to what was done for Parmer/Thatcher in commit
7fb692bd - http://review.coreboot.org/#/c/2190/
Fam15tn: Move SPD read from mainboards into wrapper

Yes, it would make sense to split this into two separate files
and move the SMBUS initialization and access into the southbridge
wrapper.  Maybe that can come next.

Change-Id: I1e106d3912c160b0015bf02158d9faba4f578ee3
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2497
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-07 18:29:23 +01:00
Ronald G. Minnich be738eb133 Remove UTF-8 characters from comments
I've used an operating system for over 10 years now that makes
UTF-8 easy. It's not called Linux or OSX.

When UTF-8 is needed, of course, then we can look again.
I can't think of a single redeeming feature of placing
it in the comment in this manner. It's certainy not
needed.

The inclusion of UTF-8 characters is inconvenient,
especially from a text terminal.
I don't really want to start using compose in
CROSH shell terminals on chromeos.

We might want to incorporate "no UTF-8" as a
commit filter. For now, get rid of these
characters.

Change-Id: If94cc657bae1dbd282bec8de6c5309b1f8da5659
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2604
Reviewed-by: Bernhard Urban <lewurm@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-03-07 18:28:16 +01:00
David Hendricks 147cdc3b17 Revert "ARMv7: Simplify div64"
This reverts commit 1cd6160821

Division bites us again. I don't know how or why, but printk() seems to break (again) with this patch. I'm surprised we didn't encounter problems earlier on...

Change-Id: I81cb9f20879f5eb73a76e1af47b96a68d1e81dc8
TODO: Find a better solution for div64. This one is too painful, but seems necessary for now (and sort-of works with our vtxprintf hack).
Reviewed-on: http://review.coreboot.org/2600
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-07 06:45:43 +01:00
David Hendricks d9b16f3b04 snow: add real values for GPIOs in fill_lb_gpios()
This adds some real GPIO mappings where virtual GPIOs were used before.

Change-Id: I25d4be45f986c8d622b97151f8bdae2651baf3e6
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2603
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-07 06:42:17 +01:00
David Hendricks 1d290eeb1c exynos5: add GPIO port enums
This adds an enum for GPIO ports on the Exynos5. To make them
useful, they are assigned the absolute MMIO address where a
s5p_gpio_bank struct can point to.

Change-Id: Ia539ba52d7393501d434ba8fecde01da37b0d8aa
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2602
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-07 06:41:37 +01:00
Stefan Reinauer 2323f3551f google/snow: fix coding style
cosmetics

Change-Id: Iea33768d901641861aa7b2c76af8753a848f584d
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2601
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-03-07 01:43:24 +01:00
Paul Menzel 0f4c0e2669 src/arch/x86/boot/acpigen.c: Small coding style and comment fixes
While reading through the file fix some spotted errors like
indentation, locution(?), capitalization and missing full stops.

Change-Id: Id435b4750e329b06a9b36c1df2c39d2038a09b18
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2484
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-07 01:07:43 +01:00
Kyösti Mälkki d59fc5340e Fix build by adding `cbmem.c` to `COLLECT_TIMESTAMPS`
A board without HAVE_ACPI_RESUME did not build with
COLLECT_TIMESTAMPS enabled as `cbmem.c` was not built.

Change-Id: I9c8b575d445ac566a2ec533d73080bcccc3dfbca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/2549
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-07 00:49:03 +01:00
Kyösti Mälkki 41dd3dbd5e Intel e7505: provide get_top_of_ram
This is required to enable EARLY_CBMEM_INIT.

Change-Id: I6d8caf382aa48eded81c1e94bbbcd3975ea88a1a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/2550
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-03-07 00:48:02 +01:00
Kyösti Mälkki 5a22b14d47 Fix socket LGA775
Models 6ex and 6fx select UDELAY_LAPIC so cannot select
contradicting UDELAY_TSC here.

Model 1067x requires speedstep.

Change-Id: I69d3ec8085912dfbe5fe31c81fa0a437228fa48f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/2525
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-07 00:46:32 +01:00
Paul Menzel e988b515f1 ASRock E350M1: Let `BiosGnbPcieSlotReset()` return `AGESA_UNSUPPORTED`
Quoting Jens Rottmann [1]:

Nevertheless I still think this whole function is bogus for the E350M1.  The
function assumes GPIO21 is wired to reset APU PCIe lane 0+1 (PCIe x8, port 4+5
as Coreboot/AGESA calls it), GPIO25 resets lane 2 (PCIe x4) and GPIO02 lane 3.
But the E350M1 has PCIe x16 i.e. probably APU lanes 0-3 bundled, completely
different layout.  They could have chosen GPIO21 to force resets, or 25 - or
maybe 50 like on the Persimmon or any other they fancied or - and this is the
most probable - none at all.  Having BiosGnbPcieSlotReset() toggle some GPIOs
without knowing what they do on the E350M1 (if anything at all) is nonsense.
In my opinion this whole function should just "return AGESA_UNSUPPORTED" and
good riddance.

[1] http://review.coreboot.org/#/c/2445/

Change-Id: Iac66da41182e838c7e6925250cc3982adbb3e4ec
Reported-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2489
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
2013-03-07 00:45:41 +01:00
Ronald G. Minnich 6bde149d9c samsung/exynos5: add display port and framebuffer defines and initialization
These are essential functions for setting up the display port and
framebuffer, and also enable such things as aux channel
communications.  We do some very simple initialization in romstage,
mainly set a GPIO so that the graphics is powering up, but the complex
parts are done in the ramstage. This mirrors the way in which graphics
is done in the x86 size.

I've added a first pass at a real device, and put it in the mainboard
Kconfig, hoping for corrections. Because startup is so complex,
depending on device type, I've created a 'displayport' device that
removes some of the complexity and makes the flow *much* clearer.  You
can actually follow the flow by looking at the code, which is not true
on other implementations. Since display port is perhaps the main port
used on these chips, that's a reasonable compromise. All parameters of
importance are now in the device tree.

Change-Id: I56400ec9016ecb8716ec5a5dae41fdfbfff4817a
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2570
Tested-by: build bot (Jenkins)
2013-03-06 23:41:42 +01:00
Paul Menzel a4b802ce86 ASRock E350M1: mainboard.c: Add declarations for `set_pcie_{,de}reset`
Since the merg of the ASRock E350M1 port (a649a96e) the compiler
warns about the following [1].

    mainboard.c:35, GNU Compiler 4 (gcc), Priorität: Normal
    no previous prototype for 'set_pcie_reset' [-Wmissing-prototypes]
    mainboard.c:43, GNU Compiler 4 (gcc), Priorität: Normal
    no previous prototype for 'set_pcie_dereset' [-Wmissing-prototypes]

Adding the function prototypes to the beginning of the file as
done in commit »Persimmon updates for AMD F14 rev C0« (d7a696d0)
addresses the warning.

[1] http://qa.coreboot.org/job/coreboot-gerrit/4975/warnings13Result/package.-139448264/file.-1544928473/
[2] http://review.coreboot.org/137

Change-Id: Iad2e62ec37c3a2f749a264974b61ac7c226e9b83
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2590
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-06 22:54:52 +01:00
Ronald G. Minnich 31dc0acd9b Google/Snow: enable sound hardware clocks
Set up the clocks used for sound and turn on the sound clock.

Change-Id: Ic59bfa9ae87116299503e6d25aeefba98c842fb8
Signed-off-by: Gabe Black <gabeblack@google.com>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2587
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-03-06 22:53:19 +01:00
Ronald G. Minnich f4861df1e7 google/snow: Change MMC0 to work in 8 bit mode.
The MMC0 on google/snow can run in 8 bit mode. To simplify driver development,
we thought disabling it (using zero, which runs in 1-bit / 4-bit mode) may help.

However, after some experiments in payload drivers, setting pinmux to 8 bit mode
can still allow MMC to run in 1-bit / 4-bit mode, so it's pretty safe to enable
8 bit mode by default for better performance.

Verified to boot on google/snow, and got MMC0 working.

Change-Id: Ic0acc723fe6a8aecf373429d3801beadd70815d9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2585
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2013-03-06 22:04:51 +01:00
Jens Rottmann 3914a316c3 AMD SB800: don't switch clock from 14 to 48 MHz for smscsuperio
The power up default for the 14M_25M_48M_OSC switchable clock output ball of
the SB800 chipset is 14 MHz.  sb800/bootblock.c changes this to 48 MHz,
which is the correct value for almost all SIOs.  However, not for
'smscsuperio' (SMSC SCH311x), which needs the original 14 MHz and is not
configurable for other clock speeds.  A wrong SIO clock supply results in
funny RS232 output (wrong bit speed) and non-working PS/2.

We could switch back to 14 MHz in the mainboard's romstage.c, but then the
clock frequency would change twice.  The resulting short 48 MHz burst causes
a handful of rubbish characters on RS232 on every boot until the SIO clock
has stabilized again.

This patch skips the SB800 clock switch if the SIO Kconfig requests 14 MHz.
This does not affect any boards currently in the repository (yet).

Change-Id: Icff41fd88dc41c08f3700ab4f786852f04eff2a4
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-on: http://review.coreboot.org/2454
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-03-06 19:07:28 +01:00
Jens Rottmann 069795a947 FrontRunner/Toucan-AF: drop unnecessary compile time CPU model selection
The first reason for selecting the CPU model at compile time was a
multi-second pause if booting a single core Fusion T40R with MAX_CPUS=2.
Recent tests show the pause has disappeared, someone must have fixed it.

The second reason was me not knowing how to make a single vgabios image
work with two different PCI IDs.  Many thanks to Martin Roth for educating
me!  Quote:

"The way to make coreboot use the same vbios for different video device IDs
 is through the map_oprom_vendev function. In family 14 it's in
 northbridge/amd/agesa/family14/amdfam14_conf.c You would name your video
 bios 1002,9802 in the config and all the other device/vendor IDs for the
 family 14h processors will fall through the initial check for the video
 bios and will get remapped to use that vbios. This only works if you're
 initializing the vbios inside coreboot. I don't know if you're using
 SeaBios as a payload, but if you are you can add the vbios to cbfs as
 vgaroms/vbios.rom and the rom will always be initialized."

I'd like to add the vgabios is added as type 'optionrom' when Coreboot make
adds it, however to work with SeaBios it has to be added manually with
cbfstool and with type 'raw', or it will hang.

Change-Id: I8190d0c3202a60dfccb77dde232f9ba7ce5ce318
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-on: http://review.coreboot.org/2584
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-03-04 23:05:31 +01:00