Commit Graph

4947 Commits

Author SHA1 Message Date
Arthur Heymans 91f5da4776 util/amdfwtool: Add some PSP entries to both levels
Some SoC like Genoa require this.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I01ff792e8016b16f34bc69722469b63cae5a42ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76468
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-07-31 13:55:49 +00:00
Arthur Heymans 93aa0903a0 amdfwtool: Add early vga BIOS ID to enum
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ife8c166350030cb89d794ac42834d79ec933f278
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-07-24 15:13:12 +00:00
Martin Roth baf82808ae util/docker: Update libncurses5-dev to libncurses-dev package
The libncurses5-dev package no longer seems to be available in debian
sid. It's been marked as a transitional package, pointing to
libncurses-dev (ncurses 6) for since 2018, so this patch updates the
package to the new name.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I81e1a174ab25f573a7d7711eeeb26ef22fd3854b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-07-23 20:59:19 +00:00
Nick Vaccaro ea025af4dc spd_tools: bring README up to date
bug=b:260128250
TEST=none

Change-Id: I412044a13f636e87db1d2266b33c9134e746e1a2
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76543
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18 18:40:40 +00:00
Nico Huber f9aec6e298 Makefile,genbuild: Provide length for abbreviated commit hashes
The original default, minimum abbreviated hash length was 7. It dif-
fers on newer systems, however. This breaks reproducibility, so set
an explicit length. 12 hex digits should be good enough.

Note: This sets only a minimum. With a high enough number of commit
objects in the repository, Git could still decide to use a longer
hash, again breaking reproducibility. 12 digits will hopefully pro-
vide enough margin.

Change-Id: Ia86e9cc41e27a0a57d498dcb13aec954c4ea0f04
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-07-18 14:57:11 +00:00
Nico Huber 99eee16a13 Center bootsplash on bigger framebuffers
In the JPEG decoder, use `bytes_per_line` instead of `width` for
address calculations, to allow for bigger framebuffers. When
calling jpeg_decode(), add an offset to the framebuffer address
so the picture gets centered.

Change-Id: I0174bdccfaad425e708a5fa50bcb28a1b98a23f7
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-17 14:49:04 +00:00
Arthur Heymans 9b186e0ffe util/xcompile: Add NASM to xcompile
Reason: opensil uses nasm code.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ib8d89354bfd21113f77927186e418e2ec3eab44c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76465
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-17 14:18:29 +00:00
Patrick Georgi e4d660b2dc crossgcc: Enable rv32iafc-ilp32 configuration
rv32iafc-ilp32 is compatible with rv32iac-ilp32 for library
implementation, so add a reuse rule allowing the default configuration
to support rv32iafc.

-IAFC is an unusual configuration (much less common than -IMAFC),
but multilib reuse has essentially no cost: this change is useful to
users of platforms that support hardware floating-point but cannot
use hardware multiply/divide for any reason. To avoid generating a
new set of libraries this is limited to the soft-float ABI.

Tested by verifying that `gcc -march=rv32iafc -mabi=ilp32
--print-search-dirs` refers to the rv32iac/ilp32 library directory
as expected, rather than just the root library directory as occurs
when an unsupported target is selected (for instance, rv32id).

Change-Id: Ie056ba6488a138fe0876eebf7cbc59477b3c3518
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-07-17 13:57:12 +00:00
Elyes Haouas ba7fee9159 util/intelmetool: Remove useless break after a break
Change-Id: Ifb76d8fa09585ad6da9bfb1488a15bf853c4da99
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-07-15 06:06:48 +00:00
Felix Singer ebafd4b905 util/crossgcc: Update GCC version from 11.3 to 11.4
Change-Id: Ia9063af4495735a0e47f4cab1179441185d888b3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-07-14 18:04:14 +00:00
Yu-Ping Wu d5e336720d util/lint/checkpatch_json.py: Make output message verbatim
Some of the error messages of checkpatch.pl contain "*". Since now
Gerrit supports markdown, messages with "*" will be rendered
incorrectly. For example,

 foo* bar should be foo *bar

will be shown as

 foo bar should be foo bar

with "bar should be foo" being in italics. Fix the problem by
surrounding the output message with "`" to make it verbatim.

Change-Id: I02d0e894adf7f94a9e154f99321f51d4097963a5
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76392
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
2023-07-14 14:29:48 +00:00
Felix Singer 90753398b6 util/crossgcc: Fix broken link by Intel to acpica tarball
All requests to acpica.org are redirected to an intel.com site now,
which breaks our buildgcc script as it's unable to download the source
tarball. Use GitHub again as it's a more reliable source.

*rant*

Change-Id: Ie4570539d6c8abe59295e5a29b323b091e939f90
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76399
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-11 17:10:44 +00:00
Rob Barnes d6b58d5c76 util/apcb: Add apcb edit tool for phoenix
Add a new apcb edit tool, apcb_v3a_edit.py, that injects SPDs into
an APCB for phoenix platform.

The tool makes several assumptions:
 * Each SPD only uses blocks 0, 1, 3 and 5. All other blocks are zero.
 * Each block is 64 bytes.
 * Dimm and socket are always 0
 * Unused SPD entries are zero'd

BUG=b:281983434
BRANCH=None
TEST=build, flash, boot myst

Change-Id: Ifb50287de77138170714a702ab87d56427aacfef
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76188
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-06 17:46:08 +00:00
Sergii Dmytruk 6da62684de util/cbmem: add parsing of TPM logs per specs
CBMEM can contain log in different forms (at most one is present):
 - coreboot-specific format (CBMEM_ID_TPM_CB_LOG exported as
   LB_TAG_TPM_CB_LOG)
 - TPM1.2 format (CBMEM_ID_TCPA_TCG_LOG)
 - TPM2 format (CBMEM_ID_TPM2_TCG_LOG)

The last two follow specifications by Trusted Computing Group, but until
now cbmem couldn't print them.  These formats were added not so long ago
in:
 - commit 4191dbf0c9 ("security/tpm: add TPM log format as per 1.2
   spec")
 - commit 53db677586 ("security/tpm: add TPM log format as per 2.0
   spec")

These changes make cbmem utility check for existence of TPM1.2/TPM2 logs
in CBMEM and add code necessary for parsing and printing of their
entries.

TEST=`cbmem -L` for CONFIG_TPM1=y case
TCPA log:
	Specification: 1.21
	Platform class: PC Client
TCPA log entry 1:
	PCR: 2
	Event type: Action
	Digest: 5622416ea417186aa1ac32b32c527ac09009fb5e
	Event data: FMAP: FMAP

TEST=`cbmem -L` for CONFIG_TPM2=y case
TPM2 log:
	Specification: 2.00
	Platform class: PC Client
TPM2 log entry 1:
	PCR: 2
	Event type: Action
	Digests:
		 SHA256: 68d27f08cb261463a6d004524333ac5db1a3c2166721785a6061327b6538657c
	Event data: FMAP: FMAP

Change-Id: Ib76dc7dec56dd1789a219539a1ac05a958f47a5c
Ticket: https://ticket.coreboot.org/issues/425
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68749
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-04 13:07:13 +00:00
Jakub Czapiga 00d71ffca8 util/sconfig: Improve usage and long options
Move usage function closer to main(), remove excessive printf() calls,
use descriptive argument flags.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: If5252de63692c5e43bfbde4d7d93e1d7a84e8dff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-07-03 13:00:19 +00:00
Felix Singer 318f629fca util/docker/coreboot-sdk: Drop legacy libftdi package
flashrom does not support libftdi 0.20 anymore and it's not used by
anything else. Its build systems (Makefile and Meson) only reference
libftdi1 and it still compiles fine without the legacy package. Thus,
drop it from the package list.

Change-Id: If1b575bc9abfd192e93811a83d8615bed61eba0c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-07-02 21:09:13 +00:00
Felix Singer 2d9ae536fe util/docker/coreboot-sdk: Drop legacy libusb package
flashrom does not support libusb 0.1 anymore and it's not used by
anything else. Its build systems (Makefile and Meson) only reference
libusb1 and it still compiles fine without the legacy package. Thus,
drop it from the package list.

Change-Id: Ib9b7530e5b707e12fbf3f8058999456dc1f8dff4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-07-02 21:08:55 +00:00
Elyes Haouas afa5383fdc crossgcc: Upgrade IASL from 20230331 to 20230628
Changes: https://acpica.org/node/204

Change-Id: I4a1be7ffa6cb363d3fe0cddc59f0f4283fcc5257
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-07-02 11:46:53 +00:00
Felix Singer 62c62885ea util/docker/coreboot-sdk: Install GNAT meta package instead gnat-12
The versions of both GCC and GNAT need to be in sync and the meta
package for GCC is already used. So use the meta package for GNAT as
well.

Change-Id: Ifcd6960731bc02c70a510e520b385ca300caf88f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-06-27 17:40:27 +00:00
Felix Singer 796b61c2a1 util/docker/coreboot-sdk: Drop subversion package
Subversion is not used anywhere (anymore?). Thus, drop it from the
package list.

Change-Id: Ibf8073c7878c130ff688102e850bbdcd66e3becc
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-06-26 17:50:14 +00:00
Felix Singer 2b4d2edfd6 util/crossgcc: Update LLVM from version 16.0.5 to 16.0.6
Change-Id: I68f776c676b1c3c5562e9209c68c7a840198e36f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-06-24 21:54:22 +00:00
lilacious 40cb3fe94d commonlib/console/post_code.h: Change post code prefix to POSTCODE
The prefix POSTCODE makes it clear that the macro is a post code.
Hence, replace related macros starting with POST to POSTCODE and
also replace every instance the macros are invoked with the new
name.

The files was changed by running the following bash script from the
top level directory.

  sed -i'' '30,${s/#define POST/#define POSTCODE/g;}' \
  src/commonlib/include/commonlib/console/post_codes.h;
  myArray=`grep -e "^#define POSTCODE_" \
  src/commonlib/include/commonlib/console/post_codes.h | \
  grep -v "POST_CODES_H" | tr '\t' ' ' | cut -d ' ' -f 2`;

  for str in ${myArray[@]}; do
    splitstr=`echo $str | cut -d '_' -f2-`
    grep -r POST_$splitstr src | \
    cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g";
    grep -r "POST_$splitstr" util/cbfstool | \
    cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g";
  done

Change-Id: I25db79fa15f032c08678f66d86c10c928b7de9b8
Signed-off-by: lilacious <yuchenhe126@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-23 15:06:04 +00:00
Michał Żygowski 95be012c11 soc/intel/alderlake/hsphy: Add possibility to cache HSPHY in flash
The patch adds a possibility to cache the PCIe 5.0 HSPHY firmware in
the SPI flash. New flashmap region is created for that purpose. The
goal of caching is to reduce the dependency on CSME and the HECI IP
LOAD command which may fail when the CSME is disabled, e.g. soft
disabled by HECI command or HAP disabled. This change allows to
keep PCIe 5.0 root ports functioning even if CSME/HECI is not
functional.

TEST=Boot Ubuntu 22.04 on MSI PRO Z690-A and notice PCIe 5.0 port
is functional after loading the HSPHY from cache.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I5a37f5b06706ff30d92f60f1bf5dc900edbde96f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68987
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-23 08:59:50 +00:00
Nico Huber 558d8b79e6 util/qemu: Add config for AArch64
Most arguments taken from the Kconfig help. RAM needs to be >= 531M,
as coreboot is linked to reside between 512M..531M.

Tested `make qemu` with QEMU 7.2.0.

Change-Id: Id7f23918a786bc126188d5caf285e9f532dbb0ed
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-23 08:48:29 +00:00
Kyösti Mälkki 6656f3151f util/abuild: Improve elapsed time measurement
Time elapsed for a single board build with ccache typically measures
well below 10 seconds. Improve the measurements to milliseconds
resolution using bash EPOCHREALTIME (pseudo) environment variable.

Change-Id: Iaedc470bb45cf9bb6f14ff8b37cd6f7ae3818a08
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-06-14 19:25:56 +00:00
Felix Singer 592700b5a6 util/docker: Add Alpine Dockerfile
Add a Dockerfile for Alpine to build-test with musl-libc.

Change-Id: If90412146acc94f01a89cd681539aad48e92dd2e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
2023-06-14 12:43:32 +00:00
Stefan Reinauer c598fd8d4a Update goswid submodule to upstream master
Updating from commit id bdd55e4:
2022-08-11 13:59:07 +0200 - (Add json minify to remove comments in JSON files)

to commit id 567a1c9:
2023-01-18 20:38:13 +0100 - (Fix README.md uSWID table)

This brings in 5 new commits:
567a1c9 Fix README.md uSWID table
f5fd52f Add PlantUML Documentation
cd56b5b Add uSWID Documentation
1a294af Add more comprehensive example in README
b0e66ae Add plantuml output

Change-Id: Ib399578a20c5c64978edf4b6198439bf6983ea44
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-12 00:51:50 +00:00
Stefan Reinauer b082e9ca36 Update cbootimage submodule to upstream master
Updating from commit id 65a6d94:
2019-07-17 17:47:14 -0600 - (Free image buffer on read error)

to commit id 80c499e:
2019-09-19 12:41:46 -0600 - (Correct spelling mistakes)

This brings in 1 new commits:
80c499e Correct spelling mistakes

Change-Id: I0557e7116052e98266ee1d078a078d698232bb2c
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75798
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-12 00:51:21 +00:00
David Hendricks 09b573ff75 board_status: Point to documentation in header
This adds a pointer to the README and to the wiki in the header of
board_status.sh.

Change-Id: I5877a3bf3544f175ac74a5e5a8e1ef1cab366ab8
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/21569
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-10 01:44:06 +00:00
Evgeny Zinoviev 88a54db592 util/inteltool: Fix building with musl libc
1. Make sure __always_inline is defined.
2. To test if we're on Linux, check presence of __linux__
   instead of __GLIBC__.

Change-Id: I2ccfc4d2ef4c60877e24508f9926b533cffec0ed
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2023-06-10 00:52:54 +00:00
Peter Lemenkov ac0e7448e4 util/inteltool: suggest booting with iomem=relaxed
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Change-Id: Ib80efd7d1ba516cb0ae4bdb86f95877855195ce0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63999
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-10 00:25:04 +00:00
Nico Huber b992df9891 util/qemu: Revise q35 configs
Add an NVMe drive and be more conservative with hotplug-capable PCIe
ports. QEMU treats everything as hotpluggable by default, so devices
can be added at runtime. However, this leads to unrealistic resource
allocations with PCIEXP_HOTPLUG enabled.

Tested recent allocator changes with QEMU/Q35 config and:

  $ make qemu QEMU_EXTRA_CFGS=util/qemu/q35-alpine.cfg

Change-Id: I23746b642329356c6767b04ec177cd9411e3adb9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67026
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-06-04 19:21:13 +00:00
Elyes Haouas 44f676afc9 crossgcc: Upgrade LLVM from version 16.0.4 to 16.0.5
Change-Id: I1f227bf55bac51e6226ca5d13156e54220e33629
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75635
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-04 18:29:42 +00:00
Elyes Haouas dea0f21c4b crossgcc: Upgrade CMake from version 3.26.3 to 3.26.4
Change-Id: Id6dca6be8f7a82eadcbc18b4736219faf51b843c
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-04 18:29:20 +00:00
Karthikeyan Ramasubramanian d7a5d9e9da util/amdfwtool: Add ability to split hash table
Hash table containing hashes of all signed PSP binaries is compiled at
build time and installed into the concerned CBFS. During boot, PSP
verstage reads the hash table binary and passes it to PSP bootloader.
PSP bootloader in turn uses the hash table to verify the signed PSP
binaries. Currently the hashes for all the signed PSP binaries are
compiled into one hash table. On upcoming platforms with more number of
signed PSP binaries, PSP bootloader does not have resources to handle
one monolithic hash table. Instead PSP bootloader recommends splitting
them into smaller hash tables (currently limited to 3 hash tables).

Update amdfwtool tool to support splitting hash tables. This is done by
adding an optional hash table id to the entries in the amdfw.cfg file.
By default, one hash table binary is always compiled and it's name is of
the format ${signed_rom}.hash. If an entry has a hash table id defined,
then this utility will compile a separate hash table binary whose name
is of the format ${signed_rom}.${N}.hash where N is the hash table id.

BUG=b:277292697
TEST=Build Skyrim BIOS image and boot to OS. Ensure that the hash table
is identical with and without this change. Perform suspend/resume
cycles, warm/cold reset cycles for 50 iterations each.
TEST=Artificially inject hash table id against some entries in
amdfw.cfg and ensure that the concerned hash table binaries are getting
compiled.

Change-Id: I7ef338d67695a34c33b5c166924832939f381191
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-06-02 22:19:44 +00:00
Martin Roth 5a4cedb9c1 util/docker: Split coreboot-sdk test into its own docker image
This allows the coreboot-sdk docker image to build properly even if the
testing fails, and keeps the added overhead out of the coreboot-sdk
image.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I6488799256f57ad64e14c93e7317b7ad2a71781c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-02 22:12:27 +00:00
Fred Reitberger 9d6008ea5b amdfwtool: Only use AMD_FW_RECOVERYAB_A on phoenix
BUG=285390041

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I4321c6a8553b470096aec263fb4b15b831efae7f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74971
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-02 20:14:26 +00:00
Grzegorz Bernacki dfdf81c32e amdfwtool: Add --output-manifest option
Passing this option tells amdfwtool to create a text file, containing
the versions of the blobs below:
- PSP bootloader (type 0x01),
- SMU firmware (type 0x08),
- AGESA bootloader 0 (type 0x30),
- PSP bootloader AB (type 0x73).

Created file can be embedded into CBFS which allows to read the version
of blobs at runtime. This way version of blobs used to build the
coreboot image can be verified at runtime and also from the binary file.

Format of manifest file is following:

    $ cat build/amdfw_manifest
    type: 0x01 ver:00.35.00.13
    type: 0x08 ver:00.5a.23.a6
    type: 0x30 ver:2a.14.b0.10
    type: 0x73 ver:00.35.00.13

BUG=b:224780134
TEST=Tested on Skyrim device

Change-Id: Idaa3a02ace524f44cfa656e34308bd896016dff6
Signed-off-by: Grzegorz Bernacki <bernacki@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-06-02 17:35:56 +00:00
Elyes Haouas a84823d078 util/crossgcc: Update nasm from 2.15.05 to 2.16.01
Timeless build for QEMU (i440fx/piix4) does not modify the binary.
New patch is add to fix the build in a separate directory from the source.

Change-Id: Ib69437be8ee69ad62fb1dfbbafabc2c4c885b7b2
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-29 21:06:41 +00:00
Subrata Banik 9cd85d0859 util/ifdtool: Add support for Intel 800 series chipset
This commit adds support for Intel 800 series chipset. The new chipset
can be uniquely identified by its SPI speed, eSPI speed, and
chipset name.

This commit message is clear and concise, and it accurately describes
the changes that were made to the code. It also includes the following
information:

- Specify the correct chipset name.
  "PCH Revision: 800 series Meteor Lake"
- Show the valid eSPI/EC frequency.
  "Read eSPI/EC Bus Frequency: 20MHz"

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I70619d9e3ed2bcad86f84a0527e3a0ad13acd706
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-27 04:01:45 +00:00
Felix Held 91795a6da1 libpayload;arch,cpu/x86: drop USE_MARCH_586 Kconfig option
Only the Intel Quark SoC selected this option and that SoC was dropped
in commit 531023285e ("soc/intel/quark: Drop support"), so drop this
Kconfig option too.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic4f1c7530cd8ac7a1945b1493a2d53a7904daa06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75473
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-27 00:29:02 +00:00
Zheng Bao e8183599ae commit-msg: Match the Signed-off-by line with name and mail address
The previous regular expression only matches the line starting with
"Signed-off-by:". If the name and mail address are missing, it can not
find out. The following words should be "name <mail@xxx.com>".

Change-Id: I42cc399e79b65928a6aef87c51e5476c7158d166
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-26 21:16:32 +00:00
Elyes Haouas a28e2358c2 util/crossgcc: Update binutils-2.40 import set_entry_point patch
Import set_entry_point patch from https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=3539414584be0094b0a4fe56dfd64ea79d802edc
to fix issue in binutils 2.40 with LTO when applied to
PE/PE+ binaries (i.e. UEFI).

Change-Id: I3844b53c8761239932ce91c2ff19ed0402321d1a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-26 15:17:45 +00:00
Elyes Haouas 9c599c8b30 crossgcc: Upgrade IASL from 20221020 to 20230331
Changes: https://acpica.org/node/202

Change-Id: I43fc180bd51ff7cb06a67619c8350d28b086bc90
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-25 20:18:36 +00:00
Felix Singer 38453784d7 util/crossgcc: Add empty directory for tarballs
A directory for tarballs is needed in any case but it's created at build
time. However, in reproducible build environments the sources are
downloaded before the buildgcc scripts runs and the directory needs to
be created.

Thus, to simplify that, add an empty tarballs directory.

Change-Id: Id3b4bf918c93f10c145f580684e916a4f8bae3b1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-05-24 21:11:21 +00:00
Zheng Bao 948c0b7947 amdfwtool: Set the minimum size of entry PSPL2 A/B
This is a PSP FW requirement.
This is only for recovery A/B without ISH header. That means only
Cezanne.

Change-Id: I62616d5a866f66fc71e6c0b31a23c62dc11cf3c6
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-05-24 12:24:28 +00:00
Elyes Haouas cf993bd343 crossgcc: Upgrade LLVM version 15.0.7 to 16.0.4
Change-Id: I753bbcf3f03907b0cf966454c3dd6c9b61869599
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-23 13:34:51 +00:00
Konrad Adamczyk d6b4db159b util: Use common ARRAY_SIZE define
Remove duplicated definitions of ARRAY_SIZE macro across util/ dir.
Instead of duplicates, use the one from commonlib/bsd/helpers.h file.

BUG=b:231765496
TEST=make -C util/cbfstool; make -C util/cbmem;
     make -C util/intelmetool; make -C util/superiotool

Change-Id: I29b776586b4f0548d4026b2ac77095791fc9f3a3
Signed-off-by: Konrad Adamczyk <konrada@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74474
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Grzegorz Bernacki
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-22 19:24:27 +00:00
Krystian Hebel 9ab3a1fe4a util/kconfig: Fix default value getter for integer options
CB:37152 was supposed to be uprev to Linux's kconfig, but it got this
one case wrong, Linux never returned "0" [1]. As a result, when an
option has default value different than 0, and it was changed to 0,
savedefconfig skips saving it. However, during the build from such
defconfig the option is assigned default value.

TEST=Set SEABIOS_DEBUG_LEVEL to 0 and see that savedefconfig writes
it to defconfig file.

[1] 7cf3d73b43

Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Change-Id: I821e45dcec99904fab85f136298cbd0315237ff6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72650
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2023-05-22 12:34:50 +00:00
Felix Singer fb03140757 util/docker: Add Dockerfile for Arch Linux
Add a minimal Dockerfile that pre-installs necessary software which is
needed to work with coreboot.

Change-Id: I85f3dc7b28b77989f0f1400d1282ed4b17082f65
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-05-17 19:55:18 +00:00