Commit Graph

18718 Commits

Author SHA1 Message Date
Chris Wang 0e1d022e26 mb/google/poppy/variants/nautilus: remove ALS for nautilus
nautilus doesn't support ALS. remove the definition from ec.h.

BRANCH=master
BUG=b:66462881
TEST=compiled/boot to ChromeOS.

Change-Id: Ib357328799015f78b18cd260db221e524e98cef7
Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/22584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: shkim <sh_.kim@samsung.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-28 01:01:24 +00:00
Martin Roth 17e7a1e0e0 mainboard/google/kahlee: Update Grunt for 16MB ROM chip
- Update Grunt to 16MB chip in Kconfig.
- Move chromeos.fmd into variant directory & update Kconfig with the new
location.
- Add Grunt specific chromeos.fmd file.

BUG=b:69691210
TEST=Build grunt; Build & Boot Kahlee

Change-Id: I8d2f5e3255984d0d9a18df560f84f6db03b73a78
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-11-28 01:00:08 +00:00
Martin Roth 320b41b148 mainboard/google/kahlee: Update chromeos.fmd
- Remove SI_ALL section.  This is no longer needed as the PSP dirctory
is placed into the RO coreboot section.
- Add 1MB Legacy section.
- Add Memory cache section. These sections are called "MRC", which is
an Intel term, but AMD platforms will use the same regions for saving
the same sort of data.

BUG=b:65497959, b:67035984
TEST=Build & boot kahlee

Change-Id: I5e41a0aa6bd4b29b8014c6559126a29cd7ed45d8
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-28 00:59:53 +00:00
Kane Chen 73031bcce0 google/fizz: correct memory rcomp settings
Follow the schematic and Doc 573387 to correct the rcomp and
rcomp target settings for fizz

TEST= boot ok and the system can enter and resume from S3.

Change-Id: Iffa90461509cfadaca20e335a6655e549e79e749
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/22479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-27 03:55:42 +00:00
Gaggery Tsai 6919a9376e drivers/net: add SSDT ACPI declaration and WOL feature
This patch adds SSDT ACPI generator and declares _UID, _HID, _DDN and
also _PRW for WOL feature. Besides, adds a wake variable in chip
information.

BUG=b:69290148
BRANCH=None
TEST=Add register "wake" = "GPE0_PCI_EXP" in devicetree under r8168
     chip driver && dump SSDT to make sure _UID, _HID, _DDN and _PRW
     are filled correctly && put system into S3 && sudo etherwake -i
     eth0 $MAC to make sure the system could be woken up by WOL package.

Change-Id: Ibc9115e8a08ba2bfcb3ee1e34c73cf1976a6ba2d
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/22480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-27 02:44:02 +00:00
Shelley Chen eca98ba460 google/fizz: Remove tpm i2c configs from Kconfig
We are disabling tpm over i2c, so the configs are not needed
anymore.

BUG=b:65056998
BRANCH=None
TEST=emerge fizz and make sure can still boot up.

Change-Id: Id88f32fa952801749544534442fc15d85fc1a892
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/22577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-25 08:31:55 +00:00
Shelley Chen 5537f02bd5 google/fizz: Disable unused i2c lines
As cr50 has now switched to using SPI, no need to enable the i2c1
anymore.  Additionally, disabled unused I2C devices -- I2C0, I2C2 and
I2C3.

BUG=b:69374421
BRANCH=None
TEST=test on fizz celeron.  Make sure /dev/tpm0 created on (many)
     reboots.  cat /proc/interrupts.  Make sure # interrupts for 16
     after booting is reasonable (not > 10k)  and idma64.0,
     i2c_designware.0 are not listed with that interrupt line anymore.
     Should look something like this:

     16: 1174 0 IO-APIC 16-fasteoi i801_smbus, snd_soc_skl, AudioDSP

Change-Id: Iac3e31264a937a1d7ed6bd41632e7e065317781b
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/22576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-25 08:31:40 +00:00
Vaibhav Shankar 6fd5a79d47 soc/intel/cannonlake: Add PM methods to power gate SD card controller
When system enters S0ix, system fails to power gate SD card
controller.

This patch implements PM methods to put the SD card controller
in D3 during S0ix entry.

TEST=Suspend and resume using 'echo freeze > /sys/power/state'.
The System should not be blocked by sd card controller.

Change-Id: I9a9fe14fb6cd3b76ee95c565b3359cdae1a3c445
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/22487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-11-23 05:03:14 +00:00
Matt DeVillier d18db73d49 google mainboards: select SYSTEM_TYPE_LAPTOP where appropriate
Some Google boards are missing this selection, leading them to being
incorrectly identified as type 'Desktop' in SMBIOS type 3 table.
Correct this by adding 'select SYSTEM_TYPE_LAPTOP' to the boards'
Kconfigs.

TEST: boot Linux and check correct chassis type listed via dmidecode

Change-Id: Ib1145e314812a3f300cfd1a435a687aa0862158a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-23 05:02:35 +00:00
Jonathan Neuschäfer 482d16fb0a src/mainboard: Fix various typos
These typos were found through manual review and grep.

Change-Id: Ia5a9acae4fbe2627017743106d9326a14c99a225
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/22525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-23 05:01:47 +00:00
John Zhao bfd62fabc9 soc/intel/cannonlake: Invoke pmc and hard reset only if CSE fails to reset
If CSE fails to do a global reset with the calling sequence of heci
reset/send/receive, then invoke pmc and hard reset.

TEST= Force global reset from early or late romstage. The function
send_heci_reset_message has the calling sequence of heci reset/send/receive.
It is observed timed out error (associated with heci_receive) occurs
only if global reset is forced during early romstage. If global reset is
trigged at late stage (i.e, after fsp_memory_init), then no timed out error
and CSE handles reset properly.

Change-Id: I5bb12554e5745d7704a1b684a3a51034bb35f787
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22549
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-23 05:00:55 +00:00
Jonathan Neuschäfer 8f06ce3512 Constify struct cpu_device_id instances
There is currently no case where a struct cpu_device_id instance needs
to be modified. Thus, declare all instances as const.

Change-Id: I5ec7460b56d75d255b3451d76a46df76a51d6365
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/22526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-23 05:00:17 +00:00
Arthur Heymans 46234ea36b sb/intel/i82801jx: Store initial timestamp in bootblock
The function to fetch this timestamp is already present.

Change-Id: I760aea8a867339764be9ca627b2ccdff4fd18e30
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-23 04:59:50 +00:00
Arthur Heymans f1c8ede1a5 sb/intel/i82801ix: fetch initial timestamp in bootblock
TESTED on Thinkpad x200

Change-Id: I3cd286709f8734793dc6ae303215433eff29d25b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-23 04:59:26 +00:00
Shelley Chen a35ad0e6ee google/fizz: Define smbios_mainboard_sku to return OEM IDs
Currently, mosys just returns "fizz" as model/chassis values.
Returning proper OEM IDs so that mosys can return the proper
variant.

BUG=b:67732053
BRANCH=None
TEST=mosys platform model; mosys platform chassis;
     Make sure returns the right variant string and not fizz.

Change-Id: I42e293e833b0f7c9870dc275561ad13256836e60
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/22557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-23 01:14:09 +00:00
Marc Jones cae58f1306 soc/amd/common: Include appropriate headers in dimm_spd.h
Change-Id: I69e8eaffefbda4fdfb89264a55762558950aa5e2
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22547
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-23 00:34:11 +00:00
Marc Jones 17431abab0 soc/amd/stoneyridge: Get entire DDR4 SPD
Set the SPD size to 512 to get the entire DDR4 SPD.

Change-Id: I0bdf8101de22533b2f4337d3c9e4423d62e6c66d
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-23 00:34:01 +00:00
Furquan Shaikh 8788fd6395 chromeec: Change the API for hostevent/wake masks to handle 64-bit
ChromeEC is getting ready to bump up the hostevents and wake masks to
64-bits. The current commands to program hostevents/wake masks will
still operate on 32-bits only. A new EC host command will be added to
handle 64-bit hostevents/wake masks. In order to prevent individual
callers in coreboot from worrying about 32-bit/64-bit, the same API
provided by google/chromeec will be updated to accept 64-bit
parameters and return 64-bit values. Internally, host command handlers
will take care of masking these parameters/return values to
appropriate 32-bit/64-bit values.

BUG=b:69329196

Change-Id: If59f3f2b1a2aa5ce95883df3e72efc4a32de1190
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-22 19:10:26 +00:00
Ege Mihmanli beb0468fce google/gru: Add support for rainier
Rainier is a scarlet-derived board but uses eDP as opposed to MIPI. Using
GRU_BASEBOARD_SCARLET is enough, except for display related logic. In
those cases, use board specific logic instead of baseboard. 


Change-Id: I596f7ca6bc26312ecaeb261c96cebd46974c2cdf
Signed-off-by: Ege Mihmanli <egemih@google.com>
Reviewed-on: https://review.coreboot.org/22542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-22 19:09:39 +00:00
Martin Roth ae01634e47 vendorcode/amd/pi/00670F00: Halt build if headers aren't wrapped
Make sure that AGESA headers don't get pulled directly into coreboot
files again.

BUG=b:66818758
TEST=Build gardenia; Build & boot kahlee; Include AGESA.h into files
verify that the build fails.

Change-Id: I8d6d94872ebf76a9df2850ed0452cf6b1a446ffd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-22 18:28:56 +00:00
Martin Roth 4d13307030 vendorcode/amd/pi/00670F00: Remove direct AGESA header includes
Update amdlib to pull in the AGESA headers through agesa_headers.h

BUG=b:66818758
TEST=Build gardenia; Build & boot kahlee

Change-Id: I3a2a2fde9738a9fe7a0b55cb91c29416cdc227a2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-22 18:28:49 +00:00
Richard Spiegel 2983c70815 Create SOC description file soc.asl
Request from commit 519680948b (move carrizo_fch.asl code to soc), merge
several includes into a single file in soc directory.

Rename soc_fch.asl to sb_fch.asl. Rename fch.asl to sb_pci0_fch.asl.
Then copy the required section from dsdt.asl into a new soc.asl.

Affected boards: amd/gardenia and google/kahlee.

BUG=b:69368752

Change-Id: I83d850cf9457f7c2c787336823d993ae2e9d28ce
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22541
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-22 18:28:29 +00:00
Duncan Laurie 2bc6ad3ff1 drivers/i2c/tpm/cr50: Simplify and increase init delay to 30 seconds
The Cr50 i2c driver provides separate entry points for probing and
initialization, but probing function does not really do much.

It also claims and releases locality on every coreboot stage, but
there is no need for this - locality should be definitely claimed
after reset and then it could be retained through the boot process.

On top of that the driver does not properly account for long time it
could take the Cr50 chip to come around to reset processing if TPM
reset request was posted during a lengthy TPM operation.

This patch addresses the issues as follows:

  - tpm_vendor_probe() and tpm_vendor_cleanup() become noops, kept
    around to conform to the expected driver API.
  - tpm_vendor_init() invokes a function to process TPM reset only in
    the first stage using TPM (typically verstage), the function
    checks if locality is claimed and if so - waits for it to be
    released, which indicates that TPM reset processing is over.
  - before claiming locality check if it is already taken, and if so -
    just proceed.

BRANCH=none
BUG=b:65867313, b:68729265
TEST=Verified that reef no longer hangs during EC reboot and
     firmware_Cr50ClearTPMOwner (not yet merged) tests.

Change-Id: Iba8445caf1342e3a5fefcb2664b0759a1a8e84e3
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/22554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-22 15:18:03 +00:00
Vadim Bendebury 8727e644ea spi/tpm: claim locality just once during boot
All coreboot stages using TPM start with the same sequence: check if
locality is claimed, if so, release it by writing 'active locality'
bit, then try claiming it.

This is actually not a proper procedure: section "5.5.2.3.1 Command
Aborts" of "TCG PC Client Platform TPM Profile (PTP) Specification
Level 00 Revision 00.430 Family 2" lists overwriting active locality
status bit as a means of triggering TPM command abort.

On top of that, none of the coreboot stages releases locality, it is
enough to claim it once when device starts booting.

In fact, locality being active when the device is in verstage is most
likely due to delayed TPM reset processing by the Cr50 TPM: reset is
an asynchronous event, and is processed once current command
processing completes.

The proper procedure is to wait if locality is active until it is
released (which will happen when Cr50 processes reset) and then
proceed to claim it. This needs to happen only during verstage, other
stages using TPM are guaranteed has been claimed earlier.

BRANCH=gru
BUG=b:65867313

TEST=the new autotest triggering EC reset during key generation
     process does not cause boot failures on Fizz device any more.
     Below are times verstage had to wait:

  TPM ready after 3132 ms
  TPM ready after 22120 ms
  TPM ready after 4936 ms
  TPM ready after 6445 ms
  TPM ready after 11798 ms
  TPM ready after 27421 ms
  TPM ready after 4582 ms
  TPM ready after 7532 ms
  TPM ready after 27920 ms
  TPM ready after 3539 ms
  TPM ready after 12557 ms
  TPM ready after 6773 ms
  TPM ready after 1631 ms
  TPM ready after 197 ms
  TPM ready after 24330 ms
  TPM ready after 3241 ms

Change-Id: Iaee04f009bcde03712483e5e03de4a3441ea32b1
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/22489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-21 23:16:27 +00:00
Vadim Bendebury 0d0408ad4f src/soc/intel/apollolake: move TCO1 disable into bootblock
Cr50 reset processing could take long time, up to 30 s in the worst
case. The TCO watchdog needs to be disabled before Cr50 driver starts,
let's disable it in bootblock.

BRANCH=none
BUG=b:65867313, b:68729265
TEST=verified that resetting the device while keys are being generated
     by the TPM does not cause falling into recovery.

Change-Id: Iaf1f97924590163e45bcac667b6c607503cc8b87
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/22553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-21 17:53:02 +00:00
Mario Scheithauer f1eb0ea537 arch/x86: Write ACPI DBG2 table only if the device has been enabled
The commit 93bbd41e (soc/intel: Enable ACPI DBG2 table generation)
causes a crash on the mainboard mc_apl1. On this mainboard all internal
SOC UARTs in the devicetree are switched off. As a result, no resources
are allocated to the UARTs. The function find_resource() expects an
existing resource. Otherwise, the CPU will stop. It should therefore not
only be queried whether a device is present, but also whether it is
enabled.

Change-Id: I56ce44ae0cf77916fcb640f79fb8944fe33177cd
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/22552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-11-21 17:01:01 +00:00
Martin Roth ece69f2123 vendorcode/amd/pi/00670F00: Clean up makefile
- Remove unnecessary cflags, exports, and variables
- Don't include AGESA cflags in the entire build
- Reformat build target

BUG=b:69220826
TEST=Build

Change-Id: I60cb20a3849439cb808f5d3919588853e9c8c734
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-21 01:38:42 +00:00
John E. Kabat Jr 7057a27a44 soc/amd/stoneyridge: Add ELOG to SMM
1. Add ELOG entries to smihandler.c
2. Add save_state utilities that are needed by southbridge_smi_gsmi

BUG=b:65485690

Change-Id: I458babe1694f042215dd0e1c3277856e340de86f
Signed-off-by: John E. Kabat Jr <john.kabat@scarletltd.com>
Reviewed-on: https://review.coreboot.org/21728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-21 01:37:03 +00:00
Marshall Dawson 0e022038fc amd/stoneyridge/spi: Fix reads greater than 5 bytes
This corrects a bug in 918c8717 "amd/stoneyridge: Add SPI controller
driver".  Pass a pointer to din to the do_command() function so the
caller's copy is correctly updated.  The bug allowed reads <= 5 bytes
to work correctly (3 bytes consumed in the FIFO by the address) but
overwrote data in the din buffer on larger transfers.

Change-Id: I32b7752f047112849871cafc9ae33c5ea1466ee1
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-21 01:36:27 +00:00
Richard Spiegel a85f8b94ab soc/amd/common: Remove duplicated #include amd_pci_int_defs.h
Remove <#include amd_pci_int_defs.h> from amd_pci_util.h, as the user
of the functions declared in amd_pci_util.h don't need the contents of
amd_pci_int_defs.h.

BUG=b:62200907

Change-Id: I258d549d3eea3fb8919c0cddbb41dc2bc4738c4e
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-21 01:20:16 +00:00
Matt DeVillier 1ad41525ca mb/google: Update/add ChromeOS device marketing names
Commit c09c2a4 [mb/google: Add Chromebook marketing names] added
marketing names for many ChromeOS devices; add some that were left out,
correct some errors, and try to format model names/numbers consistently 
(or as consistently as the manufacturers allow).

Change-Id: Ia13858e2e6ba7d7e025f25fad33e6338250498e5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-21 01:19:15 +00:00
Shelley Chen 9af3f2d63a mainboard/google/fizz: Enable separate MRC cache for recovery mode
Enable separate MRC cache for recovery mode. This requires change in
flash layout to accomodate another region for RECOVERY_MRC_CACHE.

BUG=b:69473883
TEST=Verified following scenarios:
1. Boot into recovery does not destroy normal mode MRC cache.
2. Once recovery MRC cache is populated, all future boots in recovery
mode re-use data from the cache.
3. Forcing recovery mode to retrain memory causes normal mode to retrain
memory as well.

Change-Id: Icdfac3698507d89d98a51cfc3d756a56d2a2d648
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/22518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-20 23:33:00 +00:00
Ege Mihmanli 75b154334d google/gru: Add config for scarlet-derived boards
There is merit in having new boards use the pinouts and controls
in scarlet. This adds a config so new scarlet-derived boards can
easily use scarlet structure without going through every file
and adding new logic.

TEST=Run "emerge-scarlet coreboot"
Signed-off-by: egemih@chromium.org
Change-Id: I5808f93f4563033ce93050e1eedb6eac2b52c3b3
Reviewed-on: https://review.coreboot.org/22517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-20 18:56:45 +00:00
Lijian Zhao 21573e9f4e soc/intel/cannonlake: Add ACPI workaround for EMMC
Two W/A had been added here for EMMC to make it working properly.
1. Enable power gating after D3 entry, disable power gating before D0
entry.
2. Add 50 ms delay to ensure Rcomp calibration done before EMMC out of
D3.

BUG=b:69323943
TEST=Run multiple ACPI S3 cycles on cannonlake u LPDDR4 platform.

Change-Id: Ic6e98264521fb02b911a8c157a7982afa35fe20c
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-20 17:13:57 +00:00
Marc Jones afd03d8a28 amd/stoneyridge: Fix SPD files and functions camel case
Remove ugly camel case in the soc/amd/common and Stoney Ridge
SPD files and functions. Update the related mainboards.

Also, remove a unreferenced function prototype, smbus_readSpd().

Change-Id: I51045b6621f0708d61a570acbdcb4e6522baa1ea
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-20 16:26:12 +00:00
Lin Huang da6b1bc9e2 include/timer.h: add NSECS_PER_SEC macro
Change-Id: I4367f84be5a4bd635b422b6e7cbdc9aa3ccfbf5c
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/22466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-19 01:50:13 +00:00
Martin Roth 241391841e vendorcode/amd/pi/00670F00: Remove dependency on amd/include dir
Copy the two headers used by the Stoney BinaryPI implementation into
the 00670F00 directory so that any changes that are made to them don't
affect other platforms.

BUG=b:67299330
TEST=Build

Change-Id: I5d37fac72871f2617c4be45c151741436cbfce96
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-19 01:44:07 +00:00
Martin Roth 6c623ca565 mb/google/kahlee: Move ec.h into variant include directories
The mainboard directory is included through the PI makefile - most
mainboard directories aren't in the include path at all.  Move the
ec.h file into the baseboard/variant directory that is already in
the include path.

BUG=b:69220826
TEST=Build

Change-Id: I89d361b700c66ba576de724927574fdab9461fc6
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-19 01:44:00 +00:00
Martin Roth c94021b0ef vendorcode/amd/pi/00670F00: Remove cpuFamilyTranslation.c
The file Proc/CPU/cpuFamilyTranslation.c isn't being included into
the build, so it's obviously not needed.

BUG=b:69220826
TEST=Build

Change-Id: Id244d110b4f15e1d6af6c701f62e2f05d7eb289a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-19 01:43:40 +00:00
Martin Roth 73a52d212b mainboard/google/kahlee: Remove direct AGESA header includes
All AGESA headers should be included only through agesawrapper.h

I missed this file in the Kahlee cleanup.

BUG=b:66818758
TEST=Build gardenia; Build & boot kahlee

Change-Id: Id9b303cb3cee8088fb5cca5257566c033d28c692
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-19 01:43:32 +00:00
Martin Roth 1cdb6f2a1d mainboard/google/kahlee: Update memory.c
This fixes some issues with the initial implementation that was copied
from reef.
- The board ID value shouldn't be size_t - it's not a size.
- Kahlee doesn't even need the memory.c file - it uses an SoDIMM.

BUG=b:68293392
TEST=build stoney platforms, boot kahleebo

Change-Id: Ife5660d36912e887edfd0365a9f16c5a172c9c86
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22515
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-19 01:43:04 +00:00
Jonathan Neuschäfer c09c2a4883 mb/google: Add Chromebook marketing names
It's sometimes hard to find the code name of a Chromebook. Add the
marketing names to Kconfig, since they are easily available.

Information (mostly) taken from:
https://www.chromium.org/chromium-os/developer-information-for-chrome-os-devices

Unknown boards (unreleased, etc.):
* Fizz
* Foster
* Nasher, Coral
* Purin
* Rotor
* Rowan
* Scarlet, Nefario
* Soraka
* Urara
* Veyron_Rialto

Baseboards:
* Glados
* Gru
* Jecht
* Kahlee
* Nyan
* Oak
* Poppy
* Rambi
* Zoombini

White label boards:
* Enguarde
* Heli
* Relm, Wizpig

TODO: How does this interact with the board_status code?

Change-Id: I20a36e23bd3eea8c526a0b3b53cd676cebf9cd86
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/22404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-17 21:33:25 +00:00
Richard Spiegel a800bdb298 Move amd/stoneyridge/include/amd_pci_int_defs.h to include/soc/
Move src/soc/amd/stoneyridge/include/amd_pci_int_defs.h to
src/soc/amd/stoneyridge/include/soc/.

After much discussion, src/soc/amd/stoneyridge/include/soc is probably
the best location. It was found that there are other common code that
include headers from this folder.

BUG=b:62200907

Change-Id: I69e0a54e5d64ae28919871c687a0177786b789c8
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-11-17 20:31:14 +00:00
Marshall Dawson 209ea1459b amd/gardenia: Add defines in OemCustomize.c
Add a #define for MB_DIMM_SLOTS and verify it doesn't exceed the max
supported for the device.  AGESA's DRAM procedures follow the BKDG and
may vary depending on the number of slots on the motherboard.  DIMM
numbering and ordering is also affected by this value.

Replace hardcoded integers with defined values for DIMM slots and
number of channels.

Change-Id: I81aa0165660e7627f1d977ac40479700cff8b80b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21854
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-17 20:28:43 +00:00
Bora Guvendik a778237948 soc/intel/cannonlake: fix gpio pin numbers
Update pin numbers to match kernel cannonlake pinctrl driver.

TEST=boot to OS

Change-Id: Id65736db03200fd434dd9292ce081727abd6832b
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/22477
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-17 19:39:52 +00:00
Shaunak Saha c6518b2712 soc/intel/cannonlake: Add cpu.asl file
This patch adds the cpu.asl file in cnl. We are only defining
the PNOT method here in this patch as this is needed by the
ec/google/chromeec/acpi/ec.asl file for the AC methods.

TEST= code compiles and boots when we include the ec.asl file.

Change-Id: Id93012833fac116d4d7514aa2d0b8493d2f666a9
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/22365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-11-17 18:46:24 +00:00
Marshall Dawson 91b80416b7 amd/stoneyridge: Enable SMI trap on SlpTyp
Program PMx08 to support SMIs when software writes the SlpTyp bit in
the Pm1Control register.  The southbridge needs to send the SMI message
prior to the completion response of the I/O cycle.  Also, disable
sending the STPCLK message before the completion response.

Disable the SlpTyp functionality, then enable the SMI source.

BUG=b:65595850

Change-Id: I8db0df36b285ad26c8c9e62c3857fb6580c35229
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-17 17:40:51 +00:00
Marshall Dawson 081851a9e4 amd/stoneyridge: Add SlpTyp SMI handler
When an SMI occurs due to SlpType, interpret the type of request being
made.  If it's S3 or higher, flush the cache and disable further SMIs.
Reenable SlpTyp functionality in the ACPI logic and reissue the cycle.

BUG=b:65595850

Change-Id: I88d413cdbfc2daf44e8d1142c6532f7034795ead
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-17 17:40:16 +00:00
Marshall Dawson 918c8717b2 amd/stoneyridge: Add SPI controller driver
Add more definitions for the controller registers and fields.  Add
source that is adapted from hudson and updated for Stoney Ridge.

This was tested with follow-on patches that write S3 data to flash.

BUG=b:68992021

Change-Id: I61d64cfdb4fce11c068113680da7ba6a199d6893
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-11-17 17:39:25 +00:00
Kevin Keijzer 6d941bad78 mb/lenovo/t400/blc.c: Add LTN154P2-L05 to whitelist
TESTED on Lenovo T500

Change-Id: I5546641cb34264e29ccb3398dd68f6144dafe524
Signed-off-by: Kevin Keijzer <kevin@quietlife.nl>
Reviewed-on: https://review.coreboot.org/22367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-17 15:06:15 +00:00
Kevin Keijzer 15af281744 mb/lenovo/t400: Add LTN154X3-L02 to list of known displays
TESTED on Lenovo T500

Change-Id: I9c9fef82ca4af99c7d4813e0ab0e315fde93b972
Signed-off-by: Kevin Keijzer <kevin@quietlife.nl>
Reviewed-on: https://review.coreboot.org/22475
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-11-17 11:32:16 +00:00
Martin Roth 690afa1f8c vendorcode/amd/pi/00670F00: Get rid of filecodes, replace filecode.h
coreboot doesn't need AGESA's version of Filecode.h.  Some of the files
that have been copied from AGESA include the header, so we can't get rid
of it completely yet.
- Remove includes from files that weren't copied from the AGESA source.
- Remove FILECODE definitions from coreboot source.

BUG=B:69220826
TEST=Build Gardenia; Build & boot Kahlee.

Change-Id: If16feafc12dedeb90363826b62ea7513e54277f4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-16 15:27:43 +00:00
Martin Roth 744104e24d vendorcode/amd/pi: Create stoney version of amdlib
Copy the vendorcode/amd/pi/Lib directory into 00670F00 directory and
update the 00670F00 Makefile to use it instead of using the common
version.

This allows changes to stoney without affecting the rest of the AMD
binary PI platforms.

BUG=b:67299330
TEST=Build Gardenia; Build & boot kahlee

Change-Id: I2fe4303f882938e9d917a3001476213f49426455
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-16 15:27:36 +00:00
Martin Roth 059988dbe4 vendorcode/amd/pi: Split stoney PI into its own Makefile
- Copy vendorcode/amd/pi makefile to 00670F00 directory
- Remove all stoney references from the vendorcode/amd/pi makefile
- Remove all non-stoney references from 00670F00 Makefile
- Remove directories that don't exist from 00670F00 Makefile
-- Proc/CPU/Feature
-- Proc/Fch/Kern
-- Proc/Fch/Kern/KernImc

BUG=b:67299330
TEST=Build Gardenia; Build & boot kahlee

Change-Id: I34690cfc3b1c4508d25d7cf062fcb9aea5945634
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-16 15:25:56 +00:00
Shelley Chen 85eb0311d2 drivers/spi/tpm: Poll TPM_VALID bit until valid
In case the TPM is doing a long crypto operation the initial probe
could be very delayed.  Rather than end up in recovery make the delay
long enough to accommodate the (current) long crypto times. This would
add a maximum of 30 seconds to boot time.

Mirroring changes done on i2c side in CL:756918

BUG=b:65867313, b:68729265
BRANCH=None
TEST=Make sure fizz boots up

Change-Id: Ie944bfb6fe33d6e9ee794439165716ab624be491
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/22370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-16 06:06:45 +00:00
Marc Jones 067031e0e1 variants/kahlee: Add thermal ASL
Connect the EC thermal to Kahlee and Grunt thermal ASL. Intialize GNVS
thermal values in the mainboard finalize.

BUG=b:67999819

Change-Id: I89159a5fd3c639e511139b8c5948b6a4ee19aaa3
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-11-15 18:19:31 +00:00
Marc Jones c8999a7c43 google/kahlee: Get power plug notification from the EC
Set the EC SCI reporting mask to include the power plug reporting.

BUG=b:65637324
TEST=Check power_supply_info on AC/DC.

Change-Id: I58814fc495081ffe8e47162da0fa4fbeba49d67b
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-15 18:19:23 +00:00
Richard Spiegel 519680948b mb/{amd/gardenia,google/kahlee}: move carrizo_fch.asl code to soc
Code within carrizo_fch should be SOC specific instead of board specific.

BUG=b:64034810

Change-Id: I5de2020411794bfcd3730789f62af9c9834a018b
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22455
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-15 16:47:06 +00:00
Subrata Banik bffff54e09 soc/intel/skylake: Make use of common CSE code for skylake
TEST=Ensures global reset could able to reset system.

Change-Id: I11ce1812a5a0aa2da6b414555374460d606e220e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-15 16:44:36 +00:00
Subrata Banik 4a722f5e2f soc/intel/common: Use HOST_CSR to get circular Buffer Depth
As per CSME BWG section 3.4.4.
The Circular Buffer Depth can find by checking B0:D22:F0
MMIO_HOST_CSR register.

TEST=Build and boot eve/soraka/reef/cnl-rvp

Change-Id: I1d3c09077e040b5c32b3c8be867a07f392ea4e1c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-15 16:44:29 +00:00
Subrata Banik 5c08c73dd1 soc/intel/common: Add HECI message retry count
Send/Receive HECI message with 5 retry count in order
to avoid HECI message failure.

TEST=Build and boot eve/soraka/reef/cnl-rvp

Change-Id: I76662f8080fe312caa77c83d1660faeee0bdbe7e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22443
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-15 16:44:05 +00:00
Duncan Laurie 93bbd41ea8 soc/intel: Enable ACPI DBG2 table generation
Enable the ACPI DBG2 table generation for Intel boards.  This is
a Microsoft defined ACPI extension that allows an OS to know what
the debug port is on a system when it is not enabled by the
firmware, so it does not show up in the coreboot tables and
cannot be easily found by a payload.

broadwell: Use byte access device, set up only when enabled since
it relies on the port being put in byte access mode and using
this serial port for debug was not standard in this generation.

skylake: Enable for the configured debug port.  Skylake uses
intelblocks for UART but not ACPI.

common: Enable for the configured debug port.  This affects
apollolake and cannonlake.

Tested by compiling for apollolake/broadwell, tested by reading
the DBG2 ACPI table on kabylake board and using IASL to dump:

    [000h 0000   4]                    Signature : "DBG2"
    [004h 0004   4]                 Table Length : 00000061
    [008h 0008   1]                     Revision : 00
    [009h 0009   1]                     Checksum : 3B
    [00Ah 0010   6]                       Oem ID : "CORE  "
    [010h 0016   8]                 Oem Table ID : "COREBOOT"
    [018h 0024   4]                 Oem Revision : 00000000
    [01Ch 0028   4]              Asl Compiler ID : "CORE"
    [020h 0032   4]        Asl Compiler Revision : 00000000

    [024h 0036   4]                  Info Offset : 0000002C
    [028h 0040   4]                   Info Count : 00000001

    [02Ch 0044   1]                     Revision : 00
    [02Dh 0045   2]                       Length : 0035
    [02Fh 0047   1]               Register Count : 01
    [030h 0048   2]              Namepath Length : 000F
    [032h 0050   2]              Namepath Offset : 0026
    [034h 0052   2]              OEM Data Length : 0000
    [036h 0054   2]              OEM Data Offset : 0000
    [038h 0056   2]                    Port Type : 8000
    [03Ah 0058   2]                 Port Subtype : 0000
    [03Ch 0060   2]                     Reserved : 0000
    [03Eh 0062   2]          Base Address Offset : 0016
    [040h 0064   2]          Address Size Offset : 0022

    [042h 0066  12]        Base Address Register : [Generic Address Structure]
    [042h 0066   1]                     Space ID : 00 [SystemMemory]
    [043h 0067   1]                    Bit Width : 00
    [044h 0068   1]                   Bit Offset : 00
    [045h 0069   1]         Encoded Access Width : 03 [DWord Access:32]
    [046h 0070   8]                      Address : 00000000FE034000

    [04Eh 0078   4]                 Address Size : 00001000

    [052h 0082  15]                     Namepath : "\_SB.PCI0.UAR2"

Change-Id: If34a3d2252896e0b0f762136760ab981afc12a2f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/22453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-15 16:07:21 +00:00
Duncan Laurie e4a36c7b52 arch/x86/acpi: Add support for writing ACPI DBG2 table
Add a function to create an ACPI DBG2 table, which is a Microsoft
ACPI extension for providing a description of the available debug
interface on a board.

A convenience function is provided for creating a DBG2 table with
a 16550 UART based on a PCI device.

This is tested by generating a device and verifying it with iasl:

[000h 0000   4]                    Signature : "DBG2"
[004h 0004   4]                 Table Length : 00000061
[008h 0008   1]                     Revision : 00
[009h 0009   1]                     Checksum : 3B
[00Ah 0010   6]                       Oem ID : "CORE  "
[010h 0016   8]                 Oem Table ID : "COREBOOT"
[018h 0024   4]                 Oem Revision : 00000000
[01Ch 0028   4]              Asl Compiler ID : "CORE"
[020h 0032   4]        Asl Compiler Revision : 00000000

[024h 0036   4]                  Info Offset : 0000002C
[028h 0040   4]                   Info Count : 00000001

[02Ch 0044   1]                     Revision : 00
[02Dh 0045   2]                       Length : 0035
[02Fh 0047   1]               Register Count : 01
[030h 0048   2]              Namepath Length : 000F
[032h 0050   2]              Namepath Offset : 0026
[034h 0052   2]              OEM Data Length : 0000
[036h 0054   2]              OEM Data Offset : 0000
[038h 0056   2]                    Port Type : 8000
[03Ah 0058   2]                 Port Subtype : 0000
[03Ch 0060   2]                     Reserved : 0000
[03Eh 0062   2]          Base Address Offset : 0016
[040h 0064   2]          Address Size Offset : 0022

[042h 0066  12]        Base Address Register : [Generic Address Structure]
[042h 0066   1]                     Space ID : 00 [SystemMemory]
[043h 0067   1]                    Bit Width : 00
[044h 0068   1]                   Bit Offset : 00
[045h 0069   1]         Encoded Access Width : 03 [DWord Access:32]
[046h 0070   8]                      Address : 00000000FE034000

[04Eh 0078   4]                 Address Size : 00001000

[052h 0082  15]                     Namepath : "\_SB.PCI0.UAR2"

Raw Table Data: Length 97 (0x61)

  0000: 44 42 47 32 61 00 00 00 00 3B 43 4F 52 45 20 20  // DBG2a....;CORE
  0010: 43 4F 52 45 42 4F 4F 54 00 00 00 00 43 4F 52 45  // COREBOOT....CORE
  0020: 00 00 00 00 2C 00 00 00 01 00 00 00 00 35 00 01  // ....,........5..
  0030: 0F 00 26 00 00 00 00 00 00 80 00 00 00 00 16 00  // ..&.............
  0040: 22 00 00 00 00 03 00 40 03 FE 00 00 00 00 00 10  // "......@........
  0050: 00 00 5C 5F 53 42 2E 50 43 49 30 2E 55 41 52 32  // ..\_SB.PCI0.UAR2
  0060: 00                                               // .

Change-Id: I55aa3f24776b2f8aa38d7da117f422d8b8ec5479
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/22452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-15 16:07:14 +00:00
Vaibhav Shankar 8f20044c77 soc/intel/cannonlake: Fix and clean up xhci ACPI code
During S3 cycling, system entered S3 only once and falied to
enter S3 the second time. The system gets stuck at this point
and we have to do a cold reboot to restore the system.

Since XHCI IP is able to power gate during kernel freeze/suspend,
this patch removes unnecessary device gating from ASL. This helps
in continuous cycling of S3.

BUG=b:69115421
TEST=run powerd_dbus_suspend multiple times and check if
the system enters and resumes from S3.

Change-Id: Id459631ea2d32feea4b8f658fd34fa25945f909e
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/22389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-15 05:56:33 +00:00
Aaron Durbin f0349023a2 device: further untangle device_t from struct device
This further allows compilation units to be re-used without
having to add macro guards because of declarations not being
around in the __SIMPLE_DEVICE__ case. These declarations are for
functions that operate on struct device. struct device is a known
type so just expose the functions using the correct type. Also,
DEVTREE_CONST is empty while in ramstage so there's no reason
to separate the declarations. Lastly, fix up device_util.c to
use the proper types. It's only compiled in ramstage and it only
operates on struct device.

Change-Id: I306e0ad220cdab738cb727dda4a93bdec77c5521
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-15 05:19:42 +00:00
Cheng-Yi Chiang 09ab15798a mb/google/eve: Add DSP calibration clock name/rate for RT5514
Add a property for DSP calibration clock name and rate such that
RT5514 codec driver can control ssp1_mclk for DSP clock calibration.

BUG=b:67763576
TEST=boot on eve check RT5514 codec driver can get this device
     property.

Change-Id: Icf9695ef67efb2bb073e39b2ece02d57f0460a0c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org>
Original-Change-Id: Ie204dda81a099f23beb20be71380a8494a9bee31
Original-Reviewed-on: https://chromium-review.googlesource.com/756261
Original-Reviewed-by: Dylan Reid <dgreid@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/22451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14 21:21:48 +00:00
Duncan Laurie 37da8846fa mb/google/eve: Set DSP SPI clock to 12MHz
To enable faster download of hotword data set the SPI clock to the
Realtek 5514 DSP chip to 12MHz instead of the default 1MHz.

BUG=b:67763576, b:66161281
TEST=cras_test_client --listen /tmp/rec.raw, trigger hotword, and check
the samples using hexdump or cras_test_client --playback_f /tmp/rec.raw

Change-Id: I92710eae25613a8202c63888b86a269803c40fe6
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org>
Original-Change-Id: I7e50d755a90d739b6dec155228351c3974b2f3b9
Original-Reviewed-on: https://chromium-review.googlesource.com/686675
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Chinyue Chen <chinyue@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Original-Tested-by: Chinyue Chen <chinyue@chromium.org>
Original-Commit-Queue: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/22450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14 21:21:44 +00:00
Duncan Laurie d60b4930bb mb/google/eve: Enable VMX
This feature was enabled at the kernel level, but that is triggering an
issue where FSP expects it to be disabled so it forces a cold reboot on
every warm reboot.  Since we want this enabled anyway just set it this
way in the BIOS so it matches what the kernel expects.

BUG=b:68666100
TEST=pass firmware_FWtries on Eve with R63 OS image

Change-Id: I294e34d25406365d591da06ce4c931b710cfbbaa
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Change-Id: I964d3d30392d130e808f37a661f2c89ec926cf58
Original-Signed-off-by: Duncan Laurie <dlaurie@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/749733
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14 21:21:40 +00:00
Duncan Laurie bfd17e3421 mb/google/eve: Tune I2C4 hold times
Tune PCH I2C4 hold times to ensure the frequency is always <400KHz.

BUG=b:67029862
TEST=boot on eve and measure I2C4 at Tp262 to be 385KHz

Change-Id: Ie93c5c40bc74069b285f6c3ee311f1bd7cefcaf1
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Change-Id: Iceabc806a17b9e6a144a4f6288c6cca790d03950
Original-Signed-off-by: Duncan Laurie <dlaurie@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/739841
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14 21:21:37 +00:00
Furquan Shaikh ebd67c23ed mb/google/eve: Enable AER and LTR
AER and LTR must be enabled individually on ports that need it,
in this case it should be enabled for WiFi and NVMe.

BUG=b:65457528
TEST=Wifi team verified that the performance is better with these changes.

Change-Id: I0d688fe07a1f3117c1ca617c2ce78e0d024a3510
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Change-Id: Ib059517fa782ccc18ba5ef1f76058a1898b7bf7a
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/671211
Original-Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Original-Commit-Queue: Duncan Laurie <dlaurie@google.com>
Original-Tested-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/22447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14 21:21:33 +00:00
Duncan Laurie f8e4eb84e5 mb/google/eve: Use rt5663 driver and set properties
Use the rt5663 driver and provide values for the offsets which are
needed for providing manual values to compensate the DC offset for
L and R channels between headphone and headset.

BUG=b:62712227
TEST=build and boot on eve and ensure rt5663 is functional.

Change-Id: I88113616e4b7c79cff840168b7c54ae754dfa75f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Change-Id: Ica4090636c1ff29f0298114e62c9cc6fe167a425
Original-Signed-off-by: Duncan Laurie <dlaurie@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/611606
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Hsinyu Chao <hychao@chromium.org>
Reviewed-on: https://review.coreboot.org/22446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14 21:21:29 +00:00
Duncan Laurie 477942e253 mb/google/eve: Remove ACPI control of touchscreen power
Change the touchscreen power control back to coreboot instead of
under the ACPI _ON/_OFF methods, and switch the TOUCHSCREEN_STOP_L
pin back to an output.

This reverts previous changes to touchscreen GPIOs that were made
to get back to a known good/working state.  Having ACPI control these
pins was resulting in a small percentage of touchscreen not being
discovered at boot.  This platform is not intending to use S0ix so
the ACPI control is not needed.

BUG=b:63718744
TEST=manual testing on Eve devices.

Change-Id: I3fd64a435a053da1558ef736fe7baceee3c8f3a0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Change-Id: Ia1e2ae7ca2a8b668c60fbda2aa50373e580646b2
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/572692
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Original-Commit-Queue: Duncan Laurie <dlaurie@google.com>
Original-Tested-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/22445
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-14 21:21:27 +00:00
Martin Roth 4cd93b3b7f mb/amd/gardenia: Remove direct AGESA header includes
All AGESA headers should be included only through agesawrapper.h

BUG=b:66818758
TEST=Build gardenia

Change-Id: I3c9ae7a435fadabf577f1f65ad4a6aa6234e9a29
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-14 21:00:38 +00:00
Martin Roth 78b05dfbb2 soc/amd/stoneyridge: Remove direct AGESA header includes
All AGESA headers should be included only through agesawrapper.h

BUG=b:66818758
TEST=Build gardenia; Build & boot kahlee

Change-Id: Iadc516e11148048ed9bf43c7a46827793245027a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-14 21:00:18 +00:00
Martin Roth b2c0d08a4e soc/amd/common: Remove direct AGESA header includes
All AGESA headers should be included only through agesawrapper.h

BUG=b:66818758
TEST=Build gardenia; Build & boot kahlee

Change-Id: I94140235f46a627dda99540af8619aeca3f4f157
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-14 21:00:02 +00:00
Martin Roth b564eae5e1 mb/google/kahlee: Remove direct AGESA header includes
All Stoney AGESA headers should be included only through agesawrapper.h

BUG=b:66818758
TEST=Build and boot tested

Change-Id: I642f5caf8a37ae4042c32fec3a92e0995193cb7a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-14 20:59:36 +00:00
Martin Roth d6ccf4eaa9 AMD Stoney Ridge: Add agesa_headers.h
- Create header files for the stoneyridge PI that pulls in AGESA pi
headers and encloses them in #pragma pack push/pop to keep the
'#pragma pack(1)' in Porting.h from leaking.
- Add that header to agesawrapper.h, replacing AGESA.h and Porting.h

Following patches will update the coreboot code to use only
agesawrapper.h to pull in the AGESA headers.

BUG=b:66818758
TEST=Build tested

Change-Id: Ib7d76811c1270ec7ef71266d84f3960919b792d4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-14 20:59:14 +00:00
Patrick Rudolph 112ae4860f ec/lenovo/h8/acpi/ec: Add registers
Add register HPPI and GSTS.
Add method WLSW that is used by thinkpad_acpi kernel module.
Seperate method by an empty newline.

Change-Id: I5a125047fad0e08cd9256bc53c3f5a7db7e56e7d
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-11-14 17:44:03 +00:00
Marshall Dawson 28f30a138a amd/common/spi: Update flash driver usage
Fix how the SPI driver is accessed in spi_SaveS3info.  This code has
been unused to date.

Change-Id: Ie2b97c13079fd049f6e02f3ff8fa630ed880343f
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-14 17:27:36 +00:00
Marshall Dawson f5e057c885 soc/amd/stoneyridge: Load SMU fimware using PSP
Add the ability to locate the SMRAM-based SMU firmware early and
call the PSP library to load it prior to DRAM initialization.  This
is currently placed in bootblock to ensure the blob is loaded
before any reset occurs.

Add similar functionality in ramstage for SMU FW2 to the hook already
in place for running AmdInitEnv.  Rename the hook to make more sense.

This patch was tested using a pre-released PSP bootloader on a
google/kahlee system.

Leave the option unused until the bootloader is ready.

BUG=b:66339938

Change-Id: Iedf768e54a7c3b3e7cf07e266a6906923c0fad42
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-14 17:27:23 +00:00
Marshall Dawson 6350b8789f amd/stoneyridge: Add generic IMC sleep and wakeup
Hudson code, the basis for soc//stoneyridge southbridge, has typically
contained direct calls to vendorcode/amd//ImcLib.c.  In an effort to
keep #include files clean in other stoneyridge files, put the new calls
into imc.c.

Change-Id: I830d5431635ac4acaf3c3c974cb452847dc147cd
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-11-14 17:18:05 +00:00
Marshall Dawson 5e2e74f981 amd/stoneyridge: Replace BIT(n) in southbridge
Use more descriptive #define values for the ACPI features and
register decoding.

Change-Id: Iaaf9f9bd5761001bc4bfe6b64a6c72b1f04844bd
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22427
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-14 17:17:06 +00:00
Marshall Dawson 7465b9dc8d amd/stoneyridge: Define bits for AcpiConfig
Add defintions for PMx74.

Change-Id: Id9483be9032abe6fbd5a6ec2af6bb8869a4ab766
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22426
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-14 17:16:31 +00:00
Martin Roth dffd280b55 mb/google/kahlee: Add getter function for GPIO array
Instead of getting the address of the GPIO function with an extern,
add a getter function and make the GPIO arrays static.

TEST=Build Grunt; Build & boot Kahlee
BUG=b:69164070

Change-Id: I3defcb66696459b915d7d4f43234d5c08ab7d417
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-13 20:21:22 +00:00
Martin Roth b77bc6f5e7 mb/google/kahlee: Remove mainboard.h
mainboard.h only had a single function definition.  Move it into
baseboard/variants.h and get rid of the file.

TEST=Build grunt/kahlee
BUG=b:69164070

Change-Id: I6b7d50d5c949733d77c42b4daf56ed1f97ed6954
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-13 20:19:53 +00:00
Martin Roth fa3aff0906 mainboard/google/kahlee: Add Grunt variant framework
Update common files and add files for grunt to the variant directory.

BUG=b:68293392
TEST=Build only

Change-Id: I7b80e470058872d6613e66e64c8dd1494942e9b9
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-13 20:19:43 +00:00
Martin Roth ac35e622c2 mainboard/google/kahlee: Add baseboard framework
BUG=b:68293392
TEST=Build only

Change-Id: Ie4d039b4da10a992fc9dd2b0221fd4a1644aae6a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-13 20:19:38 +00:00
Lijian Zhao e1f4d790e4 soc/intel/common: Add error print in common i2c
Print error message when using common i2c without default clock defined.

TEST=Do not define default clock in Kconfig, compile will stop for
assertion.

Change-Id: I803f97698b3928e6b64df0010e71a6ded1400f87
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-11-13 17:39:53 +00:00
Lijian Zhao f3885618d9 soc/intel/cannonlake: Define default LPSS clock
Default LPSS clock need to be defined for SOC.

TEST=Turn on COMMON_I2C_DEBUG, add I2C clock entry and check I2C
programing properly during coreboot.

Change-Id: I2c6b9bb23950b09f6f05e3ef762ccb1a260efc5f
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-13 17:39:41 +00:00
Marc Jones 290a59284e soc/amd/stoneyridge: Add CPU PPKG ASL
Add PPKG Method for processor passive thermal control list.

BUG=b:67999819

Change-Id: I5d84832af06f64c923485926e4e0c73c65a2b0b2
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22399
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-13 17:36:51 +00:00
Marc Jones 31c8cdda73 soc/amd/stoneyridge: Add GNVS variables for thermal control
BUG=b:67999819

Change-Id: I78db830c14092f5e918657e62bf38ab7124b1646
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-13 17:36:37 +00:00
Marc Jones cc7aba7cb1 amd/gardenia: Add globalnvs.asl
Stoney Ridge ASL uses global NVS for sharing data between ACPI and SMM.

Change-Id: I8f497870844da1f56ff5c3b126d5613be36a9bfb
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-13 17:36:27 +00:00
Marshall Dawson 3e4e4c5f88 soc/amd/stoneyridge: Fix DRAM clear check
Explicitly add #include files to romstage.c to ensure sizes of the
devicetree structures are correct. The AMD support headers have an
open #pragma pack(1) which causes structure sizes to change based on
include ordering in different compilation units. More concretely, this
fixes a bug where dev->chip_info is incorrectly detected as 0.

Also shorten a printk string to bring the source line within 80 columns.

Change-Id: I1ed51cdbb8df387a453de6cb944b90538dac4431
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-13 17:21:56 +00:00
Matt DeVillier c4f9f4bdae google/chell: add missing SPD hex files
Several SPD hex files for chell were missing from upstream coreboot
(as compared to the Chromium tree/branch), which resulted in the
incorrect type and amount of RAM being reported on chell boards
with > 4GB RAM.  Add these missing files and their Makefile entries.

TEST: boot google/chell m7/16GB config and observe correct RAM
type and amount reported via dmidecode and cbmem console log.

Change-Id: I37d708c96e754b438e40fc413420aa64bf234c29
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22402
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-13 16:52:43 +00:00
Lijian Zhao 8e3b5e849c intel/fsp: Update cannonlake FSP header
Update cannonlake FSP header to revision 7.x.11.43. Following changes
had been made:
1.Remove Minimum control ration from FSPM UPD.
2.Add Intersil VR command option in FSPS UPD.
3.Add minimum and maxiam ring ratio override.

TEST=None

Change-Id: I63c990e5766370a82dc1c044bcf744612229a605
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-11 21:08:56 +00:00
Martin Roth 16995fb7ea vendorcode/amd/pi/00670f00: Set ModuleIdentifier to be 8 bytes
ModuleIdentifier must be 8 bytes.   Every other location else that uses
this value explicityly defines it as 8 bytes.  If it's initialized here
to less than 8 bytes, it gets passed to those other locations with
garbage at the end and fails to load the AGESA binary.

TEST=Build & boot Kahlee
BUG=B:69165234

Change-Id: I11fc90748f49782e2b16ee5326aee17cfe92d0bc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-11 21:08:18 +00:00
Subrata Banik 15129b4db4 soc/intel/apollolake: Make use of Intel SPI common block
TEST=Build and boot reef

Change-Id: I1bb22ef1737b9e35892294ec0d66df39c546d72e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-11 18:20:12 +00:00
Subrata Banik c0ec28642f soc/intel/apollolake: Add support for SPI device
Provide a translation table to convert SPI device structure
into SPI bus number and vice versa.

Change-Id: I4c8b23c7d6f289927cd7545f3875ee4352603afa
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-11 18:20:06 +00:00
Subrata Banik 5a283ef65c soc/intel/cannonlake: Make use of Intel SPI common block
TEST=Build and boot RVP

Change-Id: I5ff9867f08e43016a797b1b3719053df0c382174
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-11 18:19:58 +00:00
Subrata Banik cca50852fe soc/intel/skylake: Make use of Intel SPI common block
TEST=Build and boot soraka/eve

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I10de3ff75a3b063c4c46471e380bbbe2630c35f3
Reviewed-on: https://review.coreboot.org/22361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-11 18:19:39 +00:00
Subrata Banik 09564fce55 soc/intel/{cannonlake,skylake}: Add _soc_ prefix in spi soc routine
This ensures that function callback into the SoC code.

Change-Id: Idc16d315ba25d17a2ab537fcdf0c2b51c8802a67
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-11 18:19:31 +00:00
Subrata Banik 6c4b5916fc soc/intel/common/block: Add Intel common SPI support
SOC need to select specific macros need to compile
common SPI code.

Change-Id: I82f7d1852d12ca37f386b64a613a676753da959c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-11 18:19:15 +00:00
Marshall Dawson f79b636088 google/kahlee: Use devicetree register values for UMA
Set the UMA memory size to 128 MiB. This value was empirically tested
by AMD as the lowest value one could use.

BUG=b:64927639

TEST=default, and 64, 128, 256, 384MB non-legacy configurations.

Change-Id: I2bc808d8b402c3eb16a1a5962f3fa9d6b224cf52
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21335
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-10 22:01:28 +00:00
Aaron Durbin 36dbf1d74a soc/amd/stoneyridge: Add UMA settings to devicetree
Add three settings for the UMA configuration to correspond with
definitions in AGESA.h.
 * UMA off, Auto, or size specified
 * Size (if specified above)
 * Legacy vs. non-legacy (if Auto)

BUG=b:64927639

Change-Id: I38b6603f365fdc1f1f615794365476f749e58be7
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-10 22:01:22 +00:00
Marshall Dawson bf131b2616 amd/stoneyridge: Implement vboot_platform_is_resuming
Change-Id: I23882ad8cd93fbc25acd8a07eca6a78b6bafc191
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-10 19:18:10 +00:00
Marshall Dawson 0756880b80 amd/stoneyridge: Add function to find Pm1EvtBlk base
The AcpiPm1EvtBlk base I/O address is configured in PMx60.  Add a
helper function to read this.  The register is not lockable so it
shouldn't be assumed to be at its original address.

Change-Id: I91ebfb454c2d2ae561e658d903f33bfb34e1ad6f
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-10 19:17:42 +00:00
Marshall Dawson c5ada65620 amd/stoneyridge: Remove dead southbridge definitions
The revision level is not checked.  This was probably left over from
trying to determine hudson variants.

Remove the unused SMI command port values.  This was missed in:
  e9b862e amd/stoneyridge: Use generic SMM command port values

Change-Id: I91d8051372f4e238d390dd445d0bf06d06683a66
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-10 19:17:10 +00:00
Marshall Dawson 870fe79e64 amd/stoneyridge: Add more ACPI register definitions
Change-Id: I62a840499deed895cf474f1bfce1f399c970e589
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-10 19:17:06 +00:00
Marshall Dawson f9592ccef0 amd/stoneyridge: Use the new generic acpi_sleep_from_pm1
Unhardcode the acpi_get_sleep_type() function and rely on the new
function in arch/acpi.h.

Change-Id: Icd49c44fae43effb9f082db354abd327cad9f1ad
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-11-10 19:16:32 +00:00
Marshall Dawson 68592c34e3 amd/stoneyridge: Select AMD common sleep states
Change-Id: I2097293a1e843839bdc814345b1ec6437a6a0656
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-10 19:16:28 +00:00
Marshall Dawson 6139a5c6ad arch/x86: Add common AMD ACPI hardware definitions
Match the corresonding Intel definitions for the ACPI register
definitions.

Change-Id: Ib804f4544d04fe08fefa493d75e0375de7cf9348
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-11-10 19:15:38 +00:00
Richard Spiegel 77fee09509 soc/amd/stoneyridge: Use uint8_t as type for SPD address
SPD address is currenty int. It should be uint8_t.

BUG=b:62200225

Change-Id: Ia11c5994c41849ba01ecae3cee6fa97c527134d0
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-10 19:11:38 +00:00
Richard Spiegel cd04e31c8b soc/amd/stoneyridge: Simplify and fix SMBUS code
Solve issues left from Change-Id Ib88a868e654ad127be70ecc506f6b90b784f8d1b
Unify code: smbus.c to have the actual execution code, sm.c and smbus_spd.c
call functions within smbus.c.

Fix some functions that wrongly use SMBHSTCTRL as the register for the
data being transfered. The correct register is SMBHSTDAT0.

Include file smbus.h should only be used by sm.c, smbus.c and smbus_spd.c.

BUG=b:62200225

Change-Id: Ibd55560c95b6752652a4f255b04198e7a4e77d05
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-11-10 19:11:12 +00:00
Marshall Dawson 3f6c400310 google/kahlee: Add defines in OemCustomize.c
Add a #define for MB_DIMM_SLOTS and verify it doesn't exceed the max
supported for the device.  AGESA's DRAM procedures follow the BKDG and
may vary depending on the number of slots on the motherboard.  DIMM
numbering and ordering is also affected by this value.

Replace hardcoded integers with defined values for DIMM slots and
number of channels.

Change-Id: I4f7336da80b4e3d7f351502a63de0652e9ff5395
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21853
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-10 18:23:11 +00:00
Marshall Dawson 4af2342673 google/kahlee: Move DRAM clear override to devicetree
Kahlee needs to keep its DRAM contents after a reset. Move this
override out of the OemCustomize.c file to a devicetree register
setting.

Change-Id: I3196cb8b94bec64e8ce59e4285cf8d97f442bd3d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21858
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-10 18:23:01 +00:00
Richard Spiegel 67c2a7b487 soc/amd/common: Add DRAM clear option to northbridge.c
AmdInitPost() can be instructed to clear DRAM after a reset or to
preserve it. Use SetMemParams() to tell AGESA which action to take.

Note that any overrides from OemPostParams (OemCustomize.c) are not
affected by this change.

Change-Id: Ie18e7a265b6e0a00c0cc8912db6361087f772d2d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21856
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-10 18:22:53 +00:00
Subrata Banik 185988234d soc/intel/cannonlake: Remove structure variable initialization with 0
Variable without an initializer will default to 0 hence no
need of an explicit initialization.

Change-Id: I208d5e475600b102cd3d972919b170c10c790b32
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-10 16:38:05 +00:00
Subrata Banik 05e06cd0be soc/intel/common: Fix CSE common code to accomodate Skylake/Kabylake
This patch ensures Skylake/Kabylake soc can make use of common
CSE code in order to perform global reset using HECI interface.

TEST=Build and boot on soraka/eve/reef/cnl-rvp

Change-Id: I49b89be8106a19cde1eb9b488ac660637537ad71
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-10 16:37:38 +00:00
Subrata Banik 330dc10cfd soc/intel/apollolake: Include HECI BAR0 address inside iomap.h
This ensures HECI1_BASE_ADDRESS macro is coming from respective
SoC dirctory and not hardcoded inside common cse code. As per
firmware specification HECI1_BASE_ADDRESS might be different
between different socs.

Change-Id: I502b5b41b449bb07f14f07435bf311bbd4f943b6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-10 16:37:32 +00:00
Richard Spiegel cb01efcda1 src/soc/amd/stoneyridge/southbridge.h: Fix prototypes
Some prototypes types don't match the actual function type, though there's
no error message due to the types being alias. For clarity, types should
match between prototypes and actual functions.

BUG=b:68007655

Change-Id: I9573a68f7153dbbad2fc6551d5dab000760c871e
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-10 16:30:53 +00:00
Ben Chan eeb475c5c8 mainboard/google/coral: power off EN_PP3300_DX_LTE_SOC when entering S5
On Astronaunt, after the system enters the S5 power state, there is a
10-second timeout before the system transitions the power state from S5
to G3. The EN_PP3300_DX_LTE_SOC signal, which is controlled by GPIO_78
on the APL platform, remains on during that period. If the system is
powered back on before going to G3, the built-in modem won't go through
a power cycle as EN_PP3300_DX_LTE_SOC is never de-asserted.

Keeping the modem, and indirectly the SIM, powered during a quick system
power cycle may sometimes be undesirable. For instance, we would like a
SIM with PIN lock enabled to require unlocking each time the system is
powered on. After the SIM receives a PIN, it may remain unlocked until
its next power cycle.

Also, it is often desirable to power cycle the modem when the system
goes through a power cycle. For instance, a user may power cycle the
system to recover a wedged modem.

BUG=b:68365029
TEST=Tested the following on an Astronaunt device:
1. Verify that the modem is powered on after the system boots from cold.
2. Suspend the system to S0ix. Verify that the modem remains powered on
   when the system is in S0ix. After the system goes back to S0, verify
   that the SIM with PIN lock enabled doesn't request unlocking, and the
   modem can quickly reconnect to a network.
3. Configure the system to suspend to S3 instead of S0ix, and then
   repeat (2).
4. Perform a quick system power cycle, verify that the modem is powered
   cycle and the SIM with PIN lock enabled requests unlocking.

Change-Id: Ie60776d5d9ebc6a69aa9e360bd882f455265dfa2
Signed-off-by: Ben Chan <benchan@chromium.org>
Reviewed-on: https://review.coreboot.org/22415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-11-10 09:49:18 +00:00
Aaron Durbin 6f1e8d24af device: untangle device_t from struct device some more
This further allows compilation units to be re-used without
having to add macro guards because of declarations not being
around in the __SIMPLE_DEVICE__ case. These declarations are for
functions that operate on struct device. struct device is a known
type so just expose the functions using the correct type. Also,
DEVTREE_CONST is empty while in ramstage so there's no reason
to separate the declarations. They compile regardless of stage.

Change-Id: Idd4180437d30e7dfaa9f735416c108841e43129f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-11-10 06:33:28 +00:00
Richard Spiegel 7a39e02cfd soc/amd/stoneyridge: Fix and clean lpc.c
Rename set_lpc_resource to set_child_resource. Fix EC child resource not
recognized as already set. Remove code that's not needed.

BUG=b:62200877

Change-Id: I6e2bf9f8214b5f660084ccd622e3fe2c0cba7656
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-11-09 21:49:26 +00:00
Nick Vaccaro 8fc694ff25 mainboard/google/zoombini: add dptf.asl and gpio.h
Add dptf.asl (copied from reef) to baseboard variant includes,
instruct zoombini variant to use the baseboard's dptf.asl,
instruct zoombini variant to use the baseboard's gpio.h.

BUG=b:64395641
BRANCH=None
TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x
-a" compiles successfully.

Change-Id: I9aa37f5afc35dab372917a4c84ff3121ec569546
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/22381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-09 19:12:19 +00:00
Richard Spiegel 3e4aeec5f4 src/soc/amd/stoneyridge/southbridge.h: Remove unused prototypes
Remove unused s3_resume_init_data prototype from southbridge,h

BUG=b:68007655

Change-Id: If022f873813070aac6cc9090c2212178a4e66354
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-09 19:11:26 +00:00
Duncan Laurie 469af7b1d7 drivers/i2c/tpm/cr50: Increase init delay to 30 seconds
In case the TPM is doing a long crypto operation the initial probe
could be very delayed.  Rather than end up in recovery make the delay
long enough to accommodate the (current) long crypto times.

BUG=b:65867313, b:68729265
TEST=Verified that Soraka no longer hangs during EC reboot test.

Change-Id: I3bccff70e001dfc065c24be8ad34ef239a144db1
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-09 19:05:32 +00:00
Nick Vaccaro 605c2dc251 mainboard/google/zoombini: fix EC_SCI_GPI gpio define
Change EC_SCI_GPI to GPE0_ESPI.

BUG=b:69011806
BRANCH=master
TEST=none

Change-Id: I5d07bc0ef295d776635ff3a585c8de9028bd3f6a
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/22380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-09 19:04:23 +00:00
Furquan Shaikh d37107e130 mb/google/{poppy,nautilus,soraka}: Disable deep S3
Poppy and variants won't be using deep S3. This change disables deep
S3 option in devicetree.

BUG=b:69053636

Change-Id: I5fb4a6a0e4216a3648b5ed888f6dc6618f1a9fc4
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22378
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-09 19:02:03 +00:00
Gaggery Tsai 2ecf3f8cb9 mb/google/fizz: Enable NIC leds
This patch enables customized NIC leds as follows:

	Green	Orange (Amber)
100M	off	blinking
1000M	on	blinking

BUG=b:65437780, b:68284778
TEST=Make sure the registers are programmed as expected and observe the
     LEDs are behaving as expected. Perform suspend/resume test and the
     LEDs are still working as expected.

Change-Id: I9bb1367a4c742c2755d620e14ee6dfe70ee7f34b
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/22293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-09 18:39:12 +00:00
Martin Roth e0a6ee8880 mainboard/google/kahlee: Move usb_oc.asl into variant/acpi
This compares to the acpi directory in other variants.

BUG=b:68293392
TEST=Build and boot kahlee

Change-Id: I05d402995b280d6f020bc2575063dbffefa30670
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-09 18:19:11 +00:00
Martin Roth 95afc46382 mainboard/google/kahlee: Define MEM_CONFIG3 for Kahlee variant
Even though this GPIO isn't used for Kahlee, it needs to be defined
so that the weak version of the variant_board_id() function can
compile.

BUG=b:68293392
TEST=Build and boot kahlee

Change-Id: Ia8daf70fbafe02ec37c6b5eb8421cdb11de3be8b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-09 17:23:24 +00:00
Marshall Dawson 07132a4c32 amd/stoneyridge: Add PSP definitions southbridge and iomap
Define the PSP's BAR3 and BAR3 enable bit.  Define a default base
address for BAR3.

Change-Id: I59a0ec59b7c6bbc6468b3096ec8d025832349f44
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-08 21:59:14 +00:00
Marshall Dawson 5f0520a909 amd/stoneyridge: Add SMU firmware blobs to cbfs
Stoney Ridge supports two different sets of SMU firmware, one for
either fanless OPNs and one for fanned.

Add a Kconfig mechanism to select the proper set and add the blobs
into cbfs.

BUG=b:66339938

Change-Id: I8510823e2232b74ec6fe001cc28953f53b2aa520
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-08 21:59:08 +00:00
Marshall Dawson 596ecec009 soc/amd/common/psp: Add command to load fw blobs
An upcoming PSP firmware change will allow coreboot to load the two
SMU firmware blobs (one runs in SRAM and the other in DRAM).  The
traditional method is for the PSP to control most of the process,
e.g. loading the SRAM version prior to releasing the x86 reset.

Add a new command that can instruct the PSP to load a firmware blob
from a location in the flash.

The definition for commands 19 and 1a differ from others in that they
do not use a command/response buffer.  Instead, the PSP will look in
the command/response pointer registers directly for the blob's
address.

BUG=b:66339938

Change-Id: I8431af341930f45ac74f471628b4dc4ede7735f4
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-08 21:58:59 +00:00
Marshall Dawson 154239aff1 amd/stoneyridge: Remove fixme.c
Move the two functions in fixme.c to places where they make more sense.
Coincidentally fix the todo in amd_initcpuio() and use bsp_topmem()
instead of explicitely reading the MSR.

BUG=b:62241048

Change-Id: Ica80b92f48788314ad290ccf72e6847fb6d039c3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-08 19:24:49 +00:00
Marshall Dawson 22bb2bee60 amd/stoneyridge: Remove amdlib functions from fixme.c
Convert functionality to use coreboot-centric functions and defined
values.  This change should have no functional effect.

BUG=b:62241048

Change-Id: I87b258f3187db4247b291c848b5f0366d3303c75
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-08 19:24:28 +00:00
Marshall Dawson 2d69d75749 amd/stoneyridge: Add northbridge register macros
Add helpers for determining the D18F1 offset for MMIO base and limit,
and I/O base/limit registers.

Change-Id: I3f61bff00b8f3ada3e1bbfb163e1f223708bd47d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-08 19:23:49 +00:00
Shelley Chen b838256a51 google/fizz: add VBOOT_PHYSICAL_REC_SWITCH config
Now that recovery button has been enabled through cr50,
we can add VBOOT_PHYSICAL_REC_SWITCH config and treat
the recovery button like on any other chromebox.

BUG=b:37751915, b:63893483
BRANCH=None
TEST=With DUT in normal mode, boot into recovery, press ctrl+d
     followed by pressing the recovery button.  Should successfully
     boot into dev mode.
CQ-DEPEND=CL:737477

Change-Id: I72fb42508083295e317dd06900796dc0cda753f6
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/22368
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-08 16:26:26 +00:00
Naveen Manohar 5bcb23ebbb mb/google/poppy/variants/nautilus: Enable Dialog DA7219 support
Enable Dialog DA7219 codec i2c device and add required SSDT parameters

BUG=b:68686020
TEST=With req'd driver support in kernel v4.4 verify audio on headset

Change-Id: Ic815c929f29bec0d26a2981e9933b752c2d84c70
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Signed-off-by: Shruthi Sudhakar <shruthi.sudhakar@intel.com>
Reviewed-on: https://review.coreboot.org/22264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-07 23:37:38 +00:00
Naveen Manohar 351059a0b4 mb/google/poppy/variants/nautilus: add nhlt support
Nautilus board uses Dialog da7219 headset codec,
Select the appropriate NHLT blob to be packaged in CBFS.
Also generate the required ACPI NHLT table for codec
and the supported topology in nautilus.
Removes unwanted DMIC blob pick for nautilus

BUG=b:68686020
TEST=With the required driver support in kernel verify that
the Audio plays on headset and recording on headset mic

Change-Id: I104889f54da1de38854bcb72aabbc88b739d6c09
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Reviewed-on: https://review.coreboot.org/22325
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-07 23:37:19 +00:00
Naveen Manohar 83670c5176 soc/intel/kabylake: Add Dialog da7219 NHLT blob support
Add APIs and required parameters for creating Dialog da7219 SSP
endpoints in NHLT table.

The use of a NHLT table is required to make audio work
on the kabylake SoCs employing the internal DSP. The table
describes the audio endpoints (render vs capture) along with
their supported formats.

BUG=b:68686020
TEST=check that NHLT table for da7219 is created properly

Change-Id: I57b88873f1c59c8aadf8eec3c80a9d95165a2cc3
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/22324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-07 23:37:01 +00:00
Lijian Zhao a5b88e442b intel/cannonlake_rvp: Clean up GPIO programming
Since we move from cannonlake U DDR 4 platform to cannonlake U LPDDR4
platform, it is also critical to revisit the GPIO settings as they are
different. Remove unused GPIO setting for old platform, and clean up the
native function definition. PAD_CFG_NF can only select NF1,NF2 ..., set
to GPIO mode is illegal.

TEST=Boot up in chromeos successfully.

Change-Id: I0022b791bd8459ea2afdcd0241b603ce81408785
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2017-11-07 21:05:27 +00:00
Shaunak Saha d038d53a33 src/mainboard/intel/glkrvp: Fix Lid switch support
SCI trigger logic had to be inverted.
This patch enables the system to wake up from S3 when lid is opened
when the system is in suspend state.We are trying to match what a
external EC card running ChromeEC FW is sending on the signal.

TEST = Verified that system wakes up from S3 on toggling lid switch
back to open state.

Change-Id: Ib42a38088ee028eddc6769921b0552c569da25a9
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/22117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Schander <coreboot@mimoja.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-07 20:28:21 +00:00
Lann Martin b879ad9dfb mainboard/google/kahlee: Add MAINBOARD_FAMILY
BUG=b:68865273

Change-Id: Ia2e9b10035e9dd502a563cdf8324ea8ea1922db3
Signed-off-by: Lann Martin <lannm@chromium.org>
Reviewed-on: https://review.coreboot.org/22359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-11-07 12:35:10 +00:00
Mario Scheithauer 7ab5dcd5c8 siemens/mc_apl1: Select CONFIG_NC_FPGA_NOTIFY_CB_READY
For internal measurements this mainboard needs a marking inside the NC
FPGA when coreboot is ready and payload has been loaded.

Change-Id: I37908b21e2a077dec7fa99b0db6d1fd9b6878341
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/22356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-11-07 12:34:13 +00:00
Mario Scheithauer a39aedec9d src: Fix all Siemens copyrights
Some Siemens copyright entries incorrectly contain a dot at the end of
the line. This is fixed with this patch.

Change-Id: I8d98f9a7caad65f7d14c3c2a0de67cb636340116
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/22355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-11-07 12:33:51 +00:00
Julien Viard de Galbert 66c210ae37 mainboard/intel/harcuvar: update to set the HSIO lines configuration
Change-Id: Ifc3423ff983fb631edcab087d04742937b25ef86
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/22310
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-07 12:33:18 +00:00
Julien Viard de Galbert f528195bdf soc/intel/denverton_ns: re-factor HSIO configuration
The main goal is to allow configuring the HSIO lines from the mainboard code.
Also share the code for both romstage and ramstage.
Remove explicit dependency on the harcuvar mainboard.

Change-Id: Iec65472207309eae878d14eef5bc644b80fdbb1d
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/22309
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-07 12:32:53 +00:00
Patrick Rudolph 6a81184058 device/device_util: Add string for DEVICE_PATH_NONE
Add string for DEVICE_PATH_NONE in dev_path. The enum DEVICE_PATH_NONE
can be translated to string and shouldn't be translated by
"Unknown device path type: 0".

Makes console output a lot prettier and readable.

Note: DEVICE_PATH_NONE is used on dummy devices for hotpluggable slots.

Change-Id: I08d471d8217f966e80daefe2d9971e357defde62
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-07 12:32:13 +00:00
Jonathan Neuschäfer 67b3268fac RISC-V boards: Stop using the config string
RISC-V is moving towards OpenFirmware-derived device trees, and the old
functions to read the config string don't work anymore. Use dummy values
for the memory base and size until we can query the device tree.

Change-Id: Ice13feae4da2085ee56bac4ac2864268da18d8fe
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-07 12:31:00 +00:00
Jonathan Neuschäfer 5a6e389747 arch/riscv: Use a separate trap stack
This is the lazy solution, as explained in the comment, but it works for
now.

Change-Id: I46e18b6d633280d6409e42462500fbe7c6823b4d
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-07 12:30:38 +00:00
Jonathan Neuschäfer c90f1d7be0 arch/riscv: gettimer: Don't use the config string
Accessing the config string doesn't work anymore on current versions of
spike. Thus return dummy pointers until we have a better solution.

Change-Id: I684fc51dc0916f2235e57e36b913d363e1cb02b1
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-07 12:30:07 +00:00
Jonathan Neuschäfer 140a827daa arch/riscv: Drop mret workaround
Our toolchain can compile mret now, and once the encoding changes, we'll
have to adjust the code anyway.

Change-Id: Ic37a849f65195006fa15d74f651a8aa9a9da5b5c
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-07 12:29:27 +00:00
Jonathan Neuschäfer 92f0513a0c arch/riscv: mprv_read_*: Mark result as earlyclobber
This fixes a case of mstatus corruption, where GCC generated code that
used the same register for the mprv bit and the result.

GCC inline assembly register modifiers are documented here:
https://gcc.gnu.org/onlinedocs/gcc/Modifiers.html

Change-Id: I2c563d171892c2e22ac96b34663aa3965553ceb3
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-07 12:29:08 +00:00
Jonathan Neuschäfer 0c42cd3240 arch/riscv: Fix return type of mprv_read_u64
Change-Id: I3dc12feefe5f0762e27d2ad0234371e91313c847
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-11-07 12:28:37 +00:00
Patrick Rudolph 3dbd28470b lib/ramtest: Add comment
Add a comment about the tested RAM region size.

Change-Id: I29e99a06777bd21a65aa67049ceede4fd8adb603
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Maximilian Schander <coreboot@mimoja.de>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2017-11-07 12:28:20 +00:00
Bill XIE 54f45c684c ec/lenovo/h8: Clear EC output queue before enablement
Sometimes (observed on Thinkpad T400s during cold boot) a few (only one
observed) garbage bytes may detained in the output queue of EC after power
up, and they should be cleared otherwise later communications will be
disrupted.

Change-Id: Id1733f7350232d0b10ac0d1bc912b62e7fa4da75
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/22181
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Schander <coreboot@mimoja.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-11-07 12:26:51 +00:00
Bill XIE eb4ded6925 ec/acpi: add mechanisms to clear EC output queue
EC's output could be considered as a queue, and sometimes (observed on
Thinkpad T400s during cold boot) a few (only one observed) garbage bytes
may detained in such queue after power up. Those garbage bytes should be
checked and discarded first before real interactions, otherwise they may
disrupt the interaction during EC's enablement, causing a locked rfkill.

Change-Id: Iee031306c02f5211a4512c6b4ec90f7f0db196ae
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/22180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-11-07 12:26:42 +00:00
Julien Viard de Galbert c467334620 Microcode: add dependency to header files
When using microcode header and updating the header (due to a new
release of microcode during early development) the build system
doesn't detect the header change. This commit fixes this by adding
the appropriate dependency.

Change-Id: I4211a3e39f67da727ef7cddbbee6d8c4718dee4a
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/22307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-11-07 12:16:58 +00:00
Hal Martin 399d35fee0 cpu/intel: Add Intel FCBGA1023 socket support
This socket is used by 2nd and 3rd generation mobile SKUs from 2011-2013.

select SSE2 per review suggestion

Change-Id: I9306a3364ae15530c99ca3379cfa2057c5879681
Signed-off-by: Hal Martin <hal.martin@gmail.com>
Reviewed-on: https://review.coreboot.org/22209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-11-07 04:39:14 +00:00
Marshall Dawson 3727708aef soc/amd/common/psp: Require PSP PCI definition in SOC
Remove the definition for the PSP PCI device from the common PSP
code.  Any APU using this source should have its own definitions,
and this allows for the device to move within the config space.

Change-Id: Ie41dfa348b04f655640b4259b1aa518376655251
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-06 22:21:50 +00:00
Julius Werner 1ab8c01050 gru: Fix and export SPK_PA_EN GPIO for Scarlet
On older Grus, GPIO0_A2 was an audio voltage rail enable line. On
Scarlet, we instead moved the audio codec enable (previously on
GPIO1_A2) there. Unfortunately the code still had some hardcoded
leftovers that were overlooked in the initial port and make our speakers
smell weird.

This patch fixes the incorrect GPIO settings and adds the speaker enable
pin to the GPIOs passed through the coreboot table, so that depthcharge
doesn't have to keep its own definition of the pin which may go out of
sync.

Change-Id: I1ac70ee47ebf04b8b92ff17a46cbf5d839421a61
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
Reviewed-by: Alexandru Stan <amstan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-06 20:47:50 +00:00
Bora Guvendik b202a01acd intel/cannonlake_rvp: enable CNVi bluetooth
Enable USB2 port 10 for CNVi bluetooth.

TEST=Boot to OS, verify bluetooth functionality.

Change-Id: I5f2390c149bf0de911efac09f54ccd641f51bbcd
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/22290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-11-06 18:21:20 +00:00
Aaron Durbin 4239a1671c soc/amd/stoneyridge: consolidate addresses in iomap.h
Take the existing scattered around address space defines
and put them in iomap.h.

Change-Id: I78aa1370b05d3e2f90d43f754076b81734cccf7f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-06 16:11:23 +00:00
Aaron Durbin 733ad92c65 soc/amd/stoneyridge: start header file for iomap
Create a new header file, iomap.h, which serves as a single
place for providing the address space definitions. Remove
the amd_defs.h file that had a single define in it.

Change-Id: I1b1aaa8c5d60d670c272ac7131faeb6b3edc1968
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-06 16:10:45 +00:00
ren kuo 6d53c6bc6a mainboard/google/coral: Override VBT selection for astronaut
Current VBT setting for T8 is only 1ms which is under Innolux
N116BCA-EA1 panel's spec.

Modify T8 to 100ms.
(Innolux's panel's spec requires T8 needs to be greater than 80ms)

CQ-DEPEND=CL:*496012
BUG=b:67756548
BRANCH=master
TEST=emerge-coral depthcharge coreboot chromeos-bootimage
     Run on DUT and check panel sequence meets spec.

Change-Id: I580567decfccd78366c37181255015ac2cd76493
Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com>
Reviewed-on: https://review.coreboot.org/22306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quantatw.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-11-06 13:55:46 +00:00
Patrick Rudolph 0709dc0468 ec/lenovo/h8/acpi/thermal: Add ACPI fan control
Disengage the fan 10 degree below passive threshold as the automatic EC fan
control does not disengage the FAN even when CPU starts melting ...

* Add EC registers FAND and FANA.
* Add ACPI methods _AC0 and _AL0.
* Add fan device and PowerResource for fan control.

Tested on Lenovo T430:
* The fan disengages at 80°C and keeps running at full speed until temperature
  drops below 80°C.
* Fan can be disengaged using sysfs:
  /sys/devics/virtual/thermal/cooling_device0/cur_state
Tested on Lenovo T500:
* The fan disengages at 80°C and keeps running at full speed until temperature
  drops below 80°C.
* Fan cannot be disengaged using sysfs, but the current state can be read:
  /sys/devics/virtual/thermal/cooling_device0/cur_state

Change-Id: I075ff5c69676927db1c5e731294e18796884f97e
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21227
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-04 19:10:29 +00:00
Patrick Rudolph 3ab13a8691 ec/lenovo/h8/acpi/thermal: Add support for passive cooling
The ACPI spec requires _TSP, _TC1, _TC2 and _PSL for passive cooling.
_TSP already has been added in a previous commit.
Copy the coefficients used on google devices to activate the feature.

Tested on Lenovo T430:
 The CPU is throttled once the passive threshold has been reached.
Tested on Lenovo T500:
 The CPU is throttled once the passive threshold has been reached.

Change-Id: I922923a9029de77158988ac254bab4aad9536935
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vasya Boytsov <vasiliy.boytsov@phystech.edu>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-11-04 17:23:19 +00:00
Nico Huber 8b59b31514 cpu/intel/speedstep: Emit PPKG object for first package
Tested on Lenovo Thinkpad T500.

Change-Id: I89f1ab4be338841463fb95ac75d794103380d16f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-04 17:23:11 +00:00
Nico Huber 4d211ac08d arch/x86/acpigen: Add function to write a CPU package
Emits a list of CPU cores, e.g.

  Name (PPKG, Package (2) { \_PR.CP00, \_PR.CP01 })

Tested on Lenovo Thinkpad T500.

Change-Id: I10e9ebad84343d1fb282b3fbb28f5f014f664f14
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-04 17:23:06 +00:00
Aaron Durbin b2b2015be0 mainboard/google/kahlee: remove unused FILECODE macro
From what I can tell FILECODE isn't used at all in this file.
Remove it.

Change-Id: Ie88140e63a4917f470f42119c1fe4e8c7d2584ca
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-04 02:59:32 +00:00
Aaron Durbin 3173d4444f soc/amd/stoneyridge: don't open code known literals
We have macros for register addresses. Use it for MMIO_CONF_BASE
instead of duplicating a literal again.

Change-Id: I2250ea990bafa234fd5fea48d2690edcfc4982b9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-04 02:58:57 +00:00
Aaron Durbin 174abc5180 soc/amd/stoneyridge: fix incorrect constants in macros
Hex constants need '0x' prefix. Clearly these weren't being used,
but they should be fixed properly.

Change-Id: I43ab90500b6d5bc31db7ebd1c675d651c8971b87
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-04 02:58:48 +00:00
Aaron Durbin 426dc8e827 soc/amd/stoneyridge: remove superfluous NULL field initialization
By definition in C, fields that are not explicitly initialized will
be zero'd out. Therefore, remove the redundant struture field
initialization.

Change-Id: I1b3b2ddf6d2a763e65861a7bcebc6b7cd96691c2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-04 02:58:41 +00:00
Aaron Durbin 8dd4006161 soc/amd/common: remove superfluous NULL initializers on globals
Global variables that are unitialized in C programs reside
in the .bss section. By definition, this section is cleared
to 0. Therefore, remove the explicit NULL initialization because
it's completely unnecessary.

Change-Id: I9e7a5a1e2110aa48a5497ab7e2b06676dd557763
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-04 02:58:35 +00:00
Aaron Durbin e3f7d44d3b soc/amd/common: remove use of LibAmdMemFill()
memset() exists for a reason. There's 0 reason to duplicate the
functionality but add extraneous parameters that do nothing. This
is just poor coding practices. Remove LibAmdMemFill() usage.

BUG=b:62240746

Change-Id: I18028b38421efa9c4c7c0412a04479638cc9218b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-04 02:58:28 +00:00
Lijian Zhao 7b2d1ae299 soc/intel/cannonlake: Add DSP support
Add dsp driver support for cannonalake, especially the scan_bus function
of Audio controller required.

TEST=N/A

Change-Id: I573fecedbd4d6619112765c3f2f8baccabeb5ac5
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
2017-11-04 00:44:03 +00:00
Lijian Zhao 9bb684a0ec soc/intel/cannonlake: Install common i2c
Add common i2c support for cannonlake.

TEST=N/A

Change-Id: I5c60b0579f9e6050308896dcb13dda0bbb724d2b
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22238
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-04 00:42:00 +00:00
Shaunak Saha f08ed7d790 src/mainboard/glkrvp: Fix ec_in_rw and wp
Change-Id: I513b26d39973d9714b531d1ab0755c66d19eb332
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/22195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-04 00:40:38 +00:00
Hannah Williams 96939ae694 soc/intel/apollolake: Fix nhlt blobs path for GLK
Change-Id: Iabea32654918575c952857145ee6edb165899baf
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/22277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-04 00:38:25 +00:00
Aaron Durbin b1aa6114b1 cpu: assume SSE if SSE2 is selected
If the SSE2 Kconfig option is selected also select SSE.

Change-Id: I6ccba57d5ae13b8066f2f744cd739282ffd4fe73
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-11-04 00:34:20 +00:00
Jonathan Neuschäfer 0781cbe1d3 sb and soc: Enforce correct offset of member "chromeos" in global_nvs_t
The padding has recently been broken in commit 90ebf96df5
("soc/intel/skylake: Add GNVS variables and include SGX ASL") and fixed
again in commit af88398887 ("soc/intel/skylake: Fix broken GNVS offset
for chromeos").  Avoid this bug in the future.

Change-Id: I1bf3027bba239c8747ad26a3130a7e047d3b8c94
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/22229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-04 00:33:26 +00:00
Jonathan Neuschäfer 7bd4715a70 commonlib/helpers.h: Include stddef.h
The definition of offsetof() uses size_t, which is declared in stddef.h,
according to POSIX. Include stddef.h directly to avoid relying on
implicit inclusion.

Change-Id: I221be02c332de55c9fcf7d86673709ed43dd5c3c
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/22230
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Schander <coreboot@mimoja.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-04 00:32:13 +00:00
Lijian Zhao ebd7c44d7b soc/intel/skylake: Update coding style for i2c
From comment from https://review.coreboot.org/#/c/22238/, the coding
style need to be update.

TEST=N/A

Change-Id: Id022648951c0f11216aa32f422b5095476f82f8c
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-04 00:30:38 +00:00
Philipp Deppenwiese 86fd88407b include: Deactivate timestamp_get if kconfig option not set
If CONFIG_COLLECT_TIMESTAMPS not set all timestamp
functions should be deactivated by using a pre-processor
statement.

Change-Id: I8ac63ba7e4485e26dc35fb5a68b1811f6df2f91d
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-04 00:28:57 +00:00
Keith Hui 6b06abb461 asus/p2b: Move to EARLY_CBMEM_INIT
Change-Id: I0bf4d6318ade6e931db4f8b1af08db1f9f93c313
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/22228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-11-04 00:28:28 +00:00
Lijian Zhao 44e2abf38f soc/intel/apollolake: Move to common dsp driver
Move dsp driver implementation to common dsp driver.

TEST=Boot up and check dsp driver loaded or not in OS.

Change-Id: Ia2be1c9f18e0e110600bd56a0b6cb8d40ca5e01f
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-04 00:27:24 +00:00
Lijian Zhao 7b6a8cec9b soc/intel/common: Add common dsp driver
Audio DSP pci driver can be common across different platforms.

TEST=N/A.

Change-Id: Ia9206657864b8795799dc71af54996017c1eec57
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22232
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
2017-11-04 00:26:54 +00:00
Bora Guvendik af36f1d525 mainboard/intel/cannonlake_rvp: enable SD card
Set SCS SD enable FSP parameter and set card detect
gpio information.

Change-Id: Ic99466c0d2d59070418d765442ff6d217023803b
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/21603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-03 23:59:52 +00:00
Paul Menzel 1812311645 southbridge: Remove trailing space in `dump_south()` output
Change-Id: I4df9f8ce1058a2bb219508d0c8d04e153d37131c
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/5179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-11-03 23:54:41 +00:00
Divya Chellap 8fcd559ef9 soraka: update pad reset config of WLAN_PE_RST to RSMRST
In skylake based platforms, setting GPIO pad reset config
to DEEP will reset the gpio configuration across warm reset,
set it to RSMRST to preserve the configuration across warm resets.
Also, moving the configuration from early to late as appropriate.

BUG=b:64386481
BRANCH=none
TEST= WiFi functionality across S3, DeepS3, S0ix and warm/cold reboot.

Change-Id: I38940b7c7d71e60bf0e51d6978a00be148ad61bc
Signed-off-by: Divya Chellap <divya.chellappa@intel.com>
Reviewed-on: https://review.coreboot.org/22174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-03 22:00:20 +00:00
Matt DeVillier e3d8471a78 google/reks: override USB2 Phy settings on BSW D-Stepping SOC
Adapted from Chromium commit 12ad5b5: Reks : override USB2 Phy settings...

Base on Intel recommendation, override following
settings for USB2 port 1/2/3 on BSW D-stepping SOC.

1. Set USB[1] register for right side to 7321
2. Set USB[2] register for left side to 7021
3. Set USB[3] register for CCD to 7021

Original-Change-Id: I04240a010e875f29c47f4fea83ff918f180b0273
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>

Change-Id: Iabd6312576e9897315c4e4dbf19341380d9d1414
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-03 21:57:52 +00:00
Matt DeVillier 158170b0a8 google/reks: override RX ODT limit, RAM geometry if needed
Adapted from Chromium commit 6ee6f3d: Reks: To set the RX ODT limit...

Override RX ODT and DRAM geometry for Micron part MT52L256M32D1PF-107.
Use get_ramid() to determine if override is necessary.

Original-Change-Id: I41f3aba030a00152e1217533ef953338ac396605
Original-Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Original-Reviewed-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>

Change-Id: Iea8c3c67e5afb21285dc15ad665474ad5f192423
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-03 21:57:04 +00:00
Martin Roth 42ac307330 vendorcode/amd/pi/00670F00: remove unused headers
These header files are not used, so remove them.

BUG=b:68812513
TEST=Build

Change-Id: Ib43fc544186f7b46ecf9b318b9edcf008f2d08dc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-03 21:54:39 +00:00
Marshall Dawson 5bb0d75566 amd/stoneyridge: Clarify SPD structure in chip.h
Add #define values and clarify the spdAddrLookup array.

Change-Id: I39b9913a2fd52f9105e4a771f651a8d9649202e6
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21852
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-03 18:40:26 +00:00
Werner Zeh f1f67c3b75 siemens/nc_fpga: Set FW_DONE bit before jumping to payload
Once coreboot is ready and payload has been loaded a bit inside the NC
FPGA needs to be set to notify this event. As there are NC FPGAs with
different PCI device IDs save the BAR0 address in a global variable once
the driver evaluates this address. It can then be used to access the
register from the boot state machine callback without the need of searching
for all possible PCI devices again.

As this driver is only used at ramstage there is no need of using
CAR_GLOBAL for the global variable. Use a Kconfig switch to make this
feature selectable from mainboard as not every mainboard may have a FPGA
with that capability.

Change-Id: I9cd09e7051edde30d144a7e020b84bb549e9e8b9
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/22138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-03 16:20:15 +00:00
Nico Huber b31119a348 nb/intel/gm45: Enable LAPIC monotonic timer
Change-Id: I9f96561120d0feb44c5edd9e7241bc3456b31e5f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-11-03 16:19:27 +00:00
Paul Menzel 8890dccb23 soc/mediatek/mt8173: Remove cast of `NULL*` to `void *`
`NULL` already has that type in coreboot.

```
src/include/stddef.h:#define NULL ((void *)0)
```

Change-Id: I73aeaef178be8779020c436732952aa732e90c46
Reported-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/22296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-03 16:03:30 +00:00
Keith Hui b9c1a4e8d9 sb/intel/i82371eb: Consolidate bootblock.c logic
The southbridge bootblock entry point bootblock_southbridge_init()
just calls i82371eb_enable_rom() which does all the work. Move all
that code into bootblock_southbridge_init() and drop the second
function.

Plus combine the 3 lines that set 3 bits in XBCS into one.

Change-Id: I07a5a28c91da9586e3bdaaf4521cba3f53a5cc01
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-11-03 15:24:24 +00:00
Paul Menzel 427feecbf0 google/kahlee/acpi: Serialize method _CRS
ASL+ Optimizing Compiler/Disassembler version 20170831 shows the remark
below.

```
dsdt.aml     87:  Method (_CRS, 0x0, NotSerialized)
Remark   2120 -             ^ Control Method should be made Serialized \
        (due to creation of named objects within)
```

So, serialize the method.

Fixes: commit 4a51ea8470 (google/kahlee: Add ASL for Elan touchpad)
Change-Id: I664f493318cbfd80d91565c0d29ec918278c4906
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/21901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-03 15:23:52 +00:00
Paul Menzel 8eed67b3ab drivers/intel/fsp2_0/hob_verify: Correct conversion specifier
Use the correct conversion specifier for `size_t` to fix the error
below.

```
src/drivers/intel/fsp2_0/hob_verify.c:31:4: error: format '%lx' expects \
        argument of type 'long unsigned int', but argument 4 has type \
        'size_t {aka unsigned int}' [-Werror=format=]
    "FSP_BOOTLOADER_TOLUM_SIZE: 0x%08llx < 0x%08lx\n",
    ^
    range_entry_size(&tolum), cbmem_overhead_size());
                              ~~~~~~~~~~~~~~~~~~~~~
```

Found-by: gcc (Debian 7.2.0-8) 7.2.0

Change-Id: I4631672211095f9934925e9bd230ccbf63c736af
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/22131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-03 15:23:06 +00:00
Paul Menzel 11015342b4 soc/intel/quark/spi: Correct conversion specifier
Use the correct conversion specifier for `size_t` to fix the error
below.

```
from src/soc/intel/quark/spi.c:18:
src/soc/intel/quark/spi.c: In function 'xfer':
src/soc/intel/quark/spi.c:107:20: error: format '%ld' expects argument \
   of type 'long int', but argument 3 has type 'unsigned int' \
   [-Werror=format=]
   printk(BIOS_ERR, "bytesin > %ld\n", sizeof(ctrlr->data));
                    ^
```

Found-by: gcc (Debian 7.2.0-8) 7.2.0
Change-Id: I3974d116e85715086a2bd5533a80a20c4cc43303
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/22130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-03 15:22:06 +00:00
Paul Menzel 0187380875 arch/x86/gdt: Move variable assignment down
The Clang Static Analyzer warns about an unused assignment, when
building the image for the Lenovo X60.

```
src/arch/x86/gdt.c:39:6: warning: Value stored to 'num_gdt_bytes' \
        during its initialization is never read
        u16 num_gdt_bytes = (uintptr_t)&gdt_end - (uintptr_t)&gdt;
            ^~~~~~~~~~~~~   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
```

If `CONFIG_RELOCATABLE_RAMSTAGE` is selected, the function returns
before the assignment is used. So, move the assignment below the if
statement.

Change-Id: Ibcb8bce743d8cb3625647804816fb97f937dc429
Found-by: clang version 4.0.1-6 (tags/RELEASE_401/final), Debian Sid/unstable
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/21957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-03 15:20:15 +00:00
Martin Roth d540d740b6 mainboard/google/kahlee: Prepare for variants
Move files that are particularly specific to the mainboard into the
variant directory.  Files that only have small areas of mainboard
specific pieces use #if to separate between the boards.

Add memory.c to split out the variant board id into a weak function.
Add baseboard/gpio.h to satisfy the build - this will be updated in the
next commit.

BUG=b:68293392

Change-Id: I7c1beb45f571f2547f3b5b0d7ec78923d0cec761
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-03 15:19:05 +00:00
Paul Menzel fa7d2a07fe soc/intel/common/block/lpc: Make integer literal unsigned long
```
    CC         romstage/soc/intel/common/block/*/lpc_lib.o
src/soc/intel/common/block/lpc/lpc_lib.c:91:17: warning: The result of the '<<' expression is undefined
                alignment = 1 << (log2_ceil(window_size));
                            ~~^~~~~~~~~~~~~~~~~~~~~~~~~~~
```

Change-Id: I9bf2283e23ca7739a7e5b0993d9b6034ea28fb78
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/22201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-11-03 07:54:01 +00:00
Paul Menzel 64e83409a1 soc/intel/common/block: Make integer literal unsigned long
Fix the warning below by making the integer literal unsigned.

```
    CC         bootblock/soc/intel/common/block/*/lpc_lib.o
src/soc/intel/common/block/lpc/lpc_lib.c:91:17: warning: The result of the \
'<<' expression is undefined
                alignment = 1 << (log2_ceil(window_size));
                            ~~^~~~~~~~~~~~~~~~~~~~~~~~~~~
```

Found-by: Clang static analyzer scan-build
          (clang version 4.0.1-6 (tags/RELEASE_401/final))
Fixes: e237f8b7 (soc/apollolake/lpc: Open I/O to LPC based on resource allocation)

Change-Id: I094fb469f020f3c1fae936e304b4458858842a8e
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/22198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-11-03 07:52:52 +00:00
Paul Menzel b843c5e3f3 lib/reg_script.c: Remove unused assignment
Fix the warning below.

```
    CC         bootblock/lib/reg_script.o
src/lib/reg_script.c:375:11: warning: Value stored to 'value' during its \
initialization is never read
        uint64_t value = msr.hi;
                 ^~~~~   ~~~~~~
```

Found-by: Clang static analyzer scan-build
          (clang version 4.0.1-6 (tags/RELEASE_401/final))
Fixes: fd461e39 (regscript: Add support for MSR type)
Change-Id: I218e45d12f2f00e2ad4cfe5410029f407b57568d
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/22197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-11-03 07:51:56 +00:00
Paul Menzel 57ea9b41e7 soc/mediatek/mt8173/Kconfig: Use plural of *message*
Change-Id: I07e70f7e4b3c1244559b834a91ac143cd36f75bd
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/22282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-03 07:42:07 +00:00
Paul Menzel 0d0be39bb9 soc/mediatek/mt8173: Remove unneeded header inclusion
Change-Id: If2135ca74de5e9336349bdb0e034f484b7e3dd26
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/22281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-03 07:41:24 +00:00
Paul Menzel 22db82d91d soc/mediatek/mt8173: Fix typo in debug message
Change-Id: I431a23129af8744f51edfee450f3c6e5cb0f3898
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/22280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-03 07:41:00 +00:00
Paul Menzel 454cfa00b9 soc/mediatek/mt8173: Correct multi-line comment format
Make the format of two multi-line comments compliant with the coding
style.

Change-Id: I8bc7b1eb175957b76ca19acdcb29b06ae86429b4
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/22279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-11-03 07:40:55 +00:00
Mario Scheithauer 545593d62c soc/intel/apollolake: Add APL CPU device ID
Add Apollo Lake CPU device ID for E0 stepping.

Change-Id: I28fa222cd28b783d22c347cdbbd769e66bf10c30
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/22149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-03 07:14:20 +00:00
Mario Scheithauer ee2dae2f17 siemens/mc_apl1: Enable I2C0 with 100kHz
The default setting for I2Cx is 400kHz. On this mainboard there is a
device on I2C0 which requires a lower clock rate to work correctly. For
this reason we set the frequency to 100kHz.

Change-Id: I637a58a0c89ead55ca1176d6aecdfaba5897d64f
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/22140
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-03 07:12:08 +00:00
Mario Scheithauer dda58a2a3c siemens/mc_apl1: Set coreboot ready LED
This mainboard has its own coreboot ready LED. The LED is switched on
via GPIO CNV_RGI_DT.

Change-Id: I179d013746c1334337dc9e6b7f09ac54eff0cd77
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/22136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-11-03 07:11:55 +00:00
Mario Scheithauer d958300590 siemens/mc_apl1: Add legacy IRQ routing for PCI devices
On this mainboard there are PCI devices, which are connected to the PCIe
root port via a PCIe-2-PCI bridge. One of the devices only supports
legacy interrupt routing. For this reason we have to adjust the PIR6
register (0x314c) which is responsible for PCIe device 13h and 14h. This
means that the interrupt routing will also be the same for both PCIe
devices. The bridge is connected to PCIe root port 4 (Device 14.0).

The following routing is required:
INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#->PIRQA#

Change-Id: I5464c9a2669773bc1e6cd4b4d29d1be838dbfa27
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/22139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-11-03 07:11:47 +00:00
Mario Scheithauer d0e51330ed soc/intel/apollolake: Set CPU to Max Non-Turbo Ratio
If the Running Average Power Limits (RAPL) feature is disabled, the CPU
should be set to the Max Non-Turbo Ratio. RAPL is switched off by
CONFIG_APL_SKIP_SET_POWER_LIMITS. Furthermore, a frequency change should
be prevented by disabling Enhanced Intel Speedstep Technology (EIST). So
the CPU should run with constant frequency with this setting.

Change-Id: I67020f7e75700255629294fd9bcf67ee01765a01
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/22148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-03 07:11:37 +00:00
Chris Wang 36e40e40a7 google/nautilus: enable elan touchpad support
add elan touchpad in devicetree.

BRANCH=master
BUG=b:66462881
TEST=emerge-nautilus coreboot

Change-Id: I30e6797ef06351690ff0b5c78ea76918547167a7
Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/22187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: shkim <sh_.kim@samsung.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-03 05:32:41 +00:00
Chris Wang cb25974f5a google/nautilus: Update GPIO table
Update GPIO settings to meet nautilus's schematic design.

BRANCH=master
BUG=b:66462881
TEST=emerge-nautilus coreboot

Change-Id: I11930df62130431764702371a3ba84949a65ba30
Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/22183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: shkim <sh_.kim@samsung.com>
2017-11-03 05:32:33 +00:00
Chris Wang cf24da4c53 google/nautilus: add spd data by ram id
update with nautilus memory spds.

RAM_ID = 0 => K4E8E324EB-EGCF
RAM_ID = 1 => K4E6E304EB-EGCF
RAM_ID = 2 => K4EBE304EB-EGCG

BRANCH=master
BUG=b:66462881
TEST=emerge-nautilus coreboot

Change-Id: I29d8a76b170aee64bb0125276df0e4709012daba
Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/22175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: shkim <sh_.kim@samsung.com>
2017-11-03 05:32:27 +00:00
Tim Chen 5473c1a947 mainboard/google/coral: Override VBT selection for santa
Current VBT setting for T8 is only 1ms which is under Innolux N116BCA-EA1
panel's spec.

Modify T8 to 100ms.
(Innolux's panel's spec requires T8 needs to be greater than 80ms)

BUG=b:67756548
BRANCH=master
TEST=emerge-coral depthcharge coreboot chromeos-bootimage
     Run on DUT and check panel sequence meets spec.
CQ-DEPEND=CL:*493633

Change-Id: I7934b0f6d40b15796c55d360995c5eb0c5049222
Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/22294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-02 15:57:48 +00:00
Aaron Durbin f4258dec63 cpu/x86/mtrr: fix fls() and fms() inline assembly
The x86 bsf and bsr instructions only allow for a memory
or register operand. The 'g' constraint includes immediate
operands which the compiler could choose to emit for the instruction.
However, the assembler will rightfully complain because the
instruction with an immediate operand is illegal. Fix the constraints
to bsf and bsr to only include memory or registers.

Change-Id: Idea7ae7df451eb69dd30208ebad7146ca01f6cba
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22291
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-11-02 15:46:19 +00:00
Marshall Dawson 383ef6eef8 amd/stoneyridge: Remove duplicate LPC decode setup
Delete the LPC I/O decode configuration from fixme.c.  This code is
superseded by early_setup.c.

Change-Id: I86ac5e997c98fea853659bc66b13128f0872f571
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-01 21:59:08 +00:00
Marshall Dawson 7d06a3fe5a amd/stoneyridge: Add pci_dev macros
Add #defines that will allow easy use of PCI devices across stages.
Future work can convert soc/amd/stoneyridge to use these and clean
up the DEV_D18F4 macro still in place.

Change-Id: I78c297d9610009e7b9e2233984e1a167f0ab88c7
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-01 21:58:59 +00:00
Marshall Dawson cbb78cd752 amd/stoneyridge: Add definitions for various NB registers
Add #define values for the first MMIO base/limit, the first I/O
base/limit, and VGA enable registers.

Change-Id: I2c209224d356cf3f83a0ddb37974831611a89760
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-01 21:58:44 +00:00
Marshall Dawson 14ef26b07b amd/stoneyridge: Consolidate duplicate comment
Change-Id: Ifaf8815dff595eb723f1b864b8f827768cb43847
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-01 21:58:34 +00:00
Marshall Dawson 7a694318e5 amd/stoneyridge: Add definition for HPET to southbridge
Add #define values for the HPET device.  In Stoney Ridge, the base
address is fixed and cannot be relocated.

Change-Id: Id36fd9ecc90d54a92144f2cca7cec6d84abfdabd
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-01 21:56:12 +00:00
Marshall Dawson 76db7886f4 cpu/amdfam15.h: Add definition for MMIO config MSR
Change-Id: Ide7f37e957964d8011438057e58c3d3a43829010
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-01 21:56:03 +00:00
Bora Guvendik 154cd41037 intel/cannonlake_rvp: enable CNVi wifi
Leaving the wifi related gpios unmodified for now
due to FSP problem. If H0-H3 is configured as native mode
and GPIORXDIS, GPIOTXDIS bits in DW0 are cleared, it causes
FSP to assert when wifi module is attached. coreboot gpio
macros clears these 2 bits because they are suppose to be
"don't care" in native mode.

TEST=Boot to OS and verify wifi

Change-Id: Ica5e1c43802d04a9471cdfa0087e86f669122fff
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/22094
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-01 20:02:02 +00:00
Vadim Bendebury 9a506d5c9a spi/tpm: Make sure AP properly syncs up with Cr50
When Cr50 TPM is being reset, it continues replying to the SPI bus
requests, sends wrong register values in response to read requests.

This patch makes sure that the TPM driver does not proceed unless
proper value is read from the TPM device identification register.

If the read value is still wrong after 10 retries taken with 10 ms
intervals, the driver gives up and declares TPM broken/unavailable.

BRANCH=cr50
BUG=b:68012381
TEST=ran a script resetting the Fizz device as soon as the "index
     0x1007 return code 0" string shows up in the AP console output.
     The script keeps rebooting the Fizz indefinitely, before this
     script Fizz would fail to read TPM properly and fall into
     recovery after no more than four reboots.

Change-Id: I7e67ec62c2bf31077b9ae558e09214d07eccf96b
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/22231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-01 18:02:43 +00:00
Bora Guvendik d2c636582d soc/intel/cannonlake: Use SCS common code
This patch uses common SCS library to set up sd card.

Change-Id: I7978bebaeba3a04fbfd01b3a5e5a37af61d2f4ce
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/21604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-01 17:42:30 +00:00
Gaggery Tsai 65623efda5 drivers/net/r8168: Add customized LED mode
This patch adds a function to program a customized LED setting
for Realtek 81xx family. It reads the settings from devicetree under
target board and programs the setting to offset 0x18 and 0x19.

BUG=b:65437780

TEST=Add customized_leds register in devicetree.cb under target board,
	enable RT8168_SET_LED_MODE flag. Make sure the setting is
	programmed correctly to offset 0x18 and 0x19. Observed the
	LEDs were behaving as expected. Executed suspend/resume and
	the LEDs were still working as expected.

Change-Id: Ib3d4f2cd98ac391e1661a891d604bdd1974d07f6
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/21862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-01 17:36:38 +00:00
Kane Chen a26c94e854 google/fizz: enable SPD read by word
This is to enable SPD word access to reduce boot time. It can save
80 ~ 100 ms per DIMM.

BUG=b:67021853
BRANCH=None
TEST=system boot, and boot time is reduced

Change-Id: Ic527a539ed634e15b939b18fff4b4e08ebb3ec57
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/22267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-01 16:27:24 +00:00
Sheng-Liang Pan 19ba2e0210 mainboard/google/coral: Update touchscreen device ACPI nodes
For Raydium, export reset GPIO as well as PowerResource.
Let EN_PP3300_TOUCHSCREEN signal will goes to low at S3 mode.

BUG=b:67879912
BRANCH=coral
TEST=emerge-coral coreboot

Change-Id: Ibf501b40ecfc957fd8be7ebffd2357dfa0e07757
Signed-off-by: Pan Sheng-Liang <Sheng-Liang.Pan@quantatw.com>
Reviewed-on: https://review.coreboot.org/22252
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-01 16:25:34 +00:00
Kane Chen 66f1f382cd intel/common/smbus: increase spd read performance
This change increases the spd read performance by using smbus word
access.

BUG=b:67021853
TEST=boot to os and find 80~100 ms boot time improvement on one dimm

Change-Id: I98fe67642d8ccd428bccbca7f6390331d6055d14
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/22072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-31 15:49:55 +00:00
Kevin Chiu 2c0696ad0f mainboard/google/snappy: Update touchscreen device ACPI nodes
For MELFAS/Raydium, export reset GPIO as well as PowerResource

BUG=b:68141940
BRANCH=reef
TEST=emerge-snappy coreboot
Change-Id: I1915ff8207502b80ecba6b63ce2ce1b866faf4c4
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/22146
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-31 15:08:40 +00:00
Jonathan Neuschäfer ec48c749c2 AMD boards: Fix function name (soft_reset) in message
Change-Id: Ia21a3e93712bd6b6780fe7308c6cf79c553f4e1b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-10-31 09:57:06 +00:00
Marc Jones 6e70d67824 soc/amd/common: Add weak call for platform PCIE slot reset
Since it is fairly uncommon, add a weak call that may be done by
the platform if it has the support.

BUG=b:66690176
BRANCH=none
TEST=coreboot builds.

Change-Id: I50008da6f85039a428184bf9e7642c0aa6610247
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-31 02:22:02 +00:00
Marc Jones c68d410ef7 x86/lapic: Use the existing lapicid() function
coreboot has a lapicid() function, so use it.

Change-Id: I7f536c229f271674c34d722b5db96ce665b720f1
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-31 02:21:35 +00:00
Ronald G. Minnich 8db7f8bad7 LB_TAGS: change the value of CB_TAG_MAC_ADDRS to 0x33
When building the Go version of cbmem I found that
LB_TAG_MAC_ADDRS has the same value as LB_TAG_VERSION_TIMESTAMP.

I am guessing that this tag was little used. In any event, move it
forward to 0x33.

Change-Id: I038ad68e787e56903a2ed9cb530809a55821c313
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/22218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-29 18:07:51 +00:00
Arthur Heymans 73abfead52 cpu/intel/model_1067x: Select UDELAY_LAPIC
This was moved out of northbridge/gm45 but was accidentally? commented
out in c5d972d073 "Move select UDELAY_LAPIC from nb/gm45/Kconfig to
cpu/model_1067x/Kconfig"

The intel eagleheights mainboard also uses UDELAY_LAPIC with this
change and is untested.

Change-Id: I70e51fa50935baf187cef60f2e636251b40d6475
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22172
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-29 14:16:30 +00:00
Arthur Heymans b1cee62512 nb/intel/i3100: Don't select UDELAY_IO
This partially reverts 2510e2aa "northbridge/intel/i3100: Unify UDELAY
selection" which moved all supported boards from UDELAY_TSC to
UDELAY_IO. Since UDELAY_IO is the default this changes nothing.

Change-Id: I42856e5929a7ba047987414a25cd0ae9712434a7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22173
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-29 14:16:13 +00:00
Furquan Shaikh 2d65d20436 arch/x86: Restore forwarding table on resume for non EARLY_EBDA_INIT
In commit c06a3f72 (arch/x86: initialize EBDA in S3 and S0/S5 path),
BDA and EBDA are wiped in the resume path. It results in coreboot
forwarding table address being wiped out since it is stored in the
BDA. This issue was resolved for platforms using EARLY_EBDA_INIT in
commit f46a9a0d (arch/x86: restore forwarding table on resume for
EARLY_EBDA_INIT). However platforms that do not use EARLY_EBDA_INIT
still run into the same issue and hence cbmem does not work on
resume. This change fixes the issue by using the stash/restore of
forwarding table address for all platforms using BDA.

BUG=b:68412690
TEST=Verified that cbmem works on S3 resume for coral.

Change-Id: I42ae2ccb0b4ce8e989b1032d82b9bb34d0d84db0
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-29 01:59:18 +00:00
Nico Huber 504d1eff4b 3rdparty/lib{hwbase,gfxinit}: Update to latest master
Simplifies our C interface function gma_gfxinit(), due to the following
changes:

* *libgfxinit* knows about the underlying PCI device now and can
  probe MMIO addresses by itself.
* The framebuffer mapping is now completely handled inside the
  library where we validate that we neither overflow
  - the stolen memory,
  - the GTT address space, the GTT itself nor
  - the aperture window (i.e. resource2 of the PCI device)
    that we use to access the framebuffer.

Other changes:

* Fixes and a quirk for DP training.
* Fix for DP-VGA adapters that report an analog display in EDID.
* Fixes for Skylake support with coreboot.
* DDI Buffer drive-strength configuration for Haswell, Broadwell and
  Skylake.
* `gfx_test` can now be run from X windows (with glitches).
* Compatibility with GCC 7 and SPARK GPL 2017.

TEST=Booted lenovo/t420 and verified that everything works as usual.

Change-Id: I001ba973d864811503410579fd7ad55ab8612759
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-28 19:46:17 +00:00
Nico Huber 18228168a5 drivers/intel/gma: Put gma_gfxinit() into its own header
The current header `i915.h` is too invasive to be used everywhere where
we want to use *libgfxinit*.

Change-Id: Iba57256d536e301e598d98182448d2daa1bf9a89
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-28 19:45:15 +00:00
Nico Huber 625160fd6a lib: Prepare for libhwbase' generated config file
Add new libhwbase options and add a class for files generated during
build. This follows the same pattern as for libgfxinit.

Change-Id: Ie5b84992fa687e4e94b6d959a64086c638f66eb8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-28 19:45:06 +00:00
Martin Roth 6fea323ffe mainboard/google/Kahlee: Combine BiosCallOuts files
There's no need to have these separated.

BUG=b:64932381
Test=Build & Boot

Change-Id: I22898d3bf95d5e9a8fc2643bfccae1e2f5b29e44
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-28 11:20:46 +00:00
Lijian Zhao 8aba24d3e1 soc/intel/apollolake: Switch to common p2sb
Using common p2sb driver instead of private one.

TEST=Boot up into OS, and read back registers through PCR by iotools,
return is not 0xffffffff.

Change-Id: I30f3ef7bc37a8cb268af6fe2e4da3ec835c17633
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-27 20:13:59 +00:00
Lijian Zhao 899f5ffbdd soc/intel/cannonlake: Use common p2sb driver
Add common p2sb driver support.

TEST=Boot up into OS and read back pcr mmio address by iotools, return
is not 0xffffffff.

Change-Id: Ida66663e6daabfcb94d7e3224d75b118fc7cf829
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-27 20:13:33 +00:00
Lijian Zhao a3cbbf7652 intel/common/p2sb: Add common p2sb driver
Add common p2sb device driver that will use fixed resource instead
dynamic assigned by PCI enumeration.

TEST=None

Change-Id: Ie3f7036a5956e3db1662678aaf43023ff79ae10e
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22189
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-27 20:13:27 +00:00
Marc Jones bb59f67ee8 soc/amd/common: Remove agesa_LateRunApTask() callback
agesa_LateRunApTask() is not a callback, but a AGESA call. This is a mistake
in the AGESA spec and the function is in the wrong section.

bug=b:66690176, b:67210418
branch=none
test=none

Change-Id: I900e7db13a58e73a7b054e06088bc77c89445876
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-10-27 16:58:45 +00:00
Shaunak Saha 95b61752db soc/intel/cannonlake: Add support for C state and P state
This patch adds the C state and P state configurations for
cannonlake soc.

TEST = Boot and test the CPU states for all the cores are
       present in "powertop" tool output.

Change-Id: I4ba156354f87646b25d0f9114ebf0583eedf72df
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/21891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-26 15:55:37 +00:00
Patrick Georgi 66b5acc54b soc/intel/cannonlake: remove duplicate power_state migration
Common PMC code comes with its own.

Change-Id: Ic055f046a2da1c56af4cc7936602d6191ffe7eef
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/22182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-26 15:54:19 +00:00
Matt DeVillier a547e40992 purism/librem_skl: add new variant Librem 15 v3
Add new board librem15v3 as a variant of the librem_skl baseboard.

Changes from the librem13v2:
- Change board name and version
- Change GPIO A18, A19, A20, D9, D10 and D11 from NC to GPIO
- Enable PCI device 1c.4
- Change USB port definitions in devicetree

TEST: build w/SeaBIOS, boot PureOS on Librem 15 v3 hardware

Change-Id: I7c762a34f5b961c908e4a29ec331da4b0dea9986
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22048
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-26 06:40:33 +00:00
Patrick Georgi c6202e8c00 soc/intel/apollolake: avoid double accounting for power state
intel/common's pmclib already keeps track of the power state (since
commit f073872e22 and doing it twice can
mess up the data that ends up in cbmem (and from there, everything else),
so don't.

BUG=b:67976359
BRANCH=none
TEST=builds

Change-Id: I69c804a2a3bee43add940d8c827b7250f2fe9024
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/22179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-26 04:57:49 +00:00
Matt DeVillier 435299461f purism/librem13v2: convert to variant setup
Convert the Purism Librem13v2 board to a variant setup,
in preparation of adding the librem15v3 as a new variant.
The 13v2 and 15v3 are nearly identical, so this minimizes new
code to add support for the latter.

Change-Id: I5d648cdb8f63c03de5474253203b3d0853673294
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22047
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-26 04:06:03 +00:00
Furquan Shaikh f5e8fe5d95 soc/intel/apollolake: Fix broken GNVS offset for chromeos
Change 03a235(soc/intel/apollolake: Add GNVS variables and include SGX
ASL) added new GNVS variables but did not adjust the unused array size
and thus broke chromeos offset.

This change fixes the above issue by reducing the size of unused array.

BUG=b:68254376
TEST=Verified that chromeos offset is correct. crossystem is able to
read all variables.

Change-Id: I279bfc4c702e46b88c1c7a067a24326ff8fed368
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22177
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-25 17:12:40 +00:00
Furquan Shaikh af88398887 soc/intel/skylake: Fix broken GNVS offset for chromeos
Change 90ebf9 (soc/intel/skylake: Add GNVS variables and include SGX
ASL) added new GNVS variables but did not adjust the unused array size
and thus broke chromeos offset.

This change fixes the above issue by reducing the size of unused
array.

BUG=b:68254376
TEST=Verified that chromeos offset is correct. crossystem is able to
read all variables.

Change-Id: I5f76f5bba4f0f50a23a863450743385ad2a82b2b
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22176
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-25 17:06:06 +00:00
Keith Hui 74d8ed0cb8 superio/acpi/pnp.asl: Fix PNP_READ_DMA/PNP_WRITE_DMA macros
These macros, broken since day one, should CreateByteField instead
of CreateWordField. Without the fix, any ASLs that try to use it
will fail to compile with a "ResourceTag smaller than Field"
warning.

Change-Id: Ieeb509aece8836785998b23fdc805a747d40a77a
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/22066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-25 14:32:39 +00:00
John Zhao b8d66bb6fd mainboard/intel/cannonlake_rvp: Enable variant gpio configuration
This patch refers to variant_gpio_table for board gpio configuration.

Change-Id: If5b4c20ceccb32fc1ab4246482d8fecb491777c4
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2017-10-24 15:54:14 +00:00
Chris Ching aa8e5d36b1 soc: Add Kconfig for each soc vendor
Allows explicit ordering for vendors that share a common configuration
that must be sourced last.

The issue is that chips in soc/{amd,intel}/[ab].* will be able to
override defaults set in this file, but Kconfig files that get sourced
later (soc/amd/[d-z].*) will NOT be able to override these defaults.

Note: intel and amd soc chips now need to be added manually to the new
Kconfig file

BUG=b:62235314
TEST=make lint-stable

Change-Id: Ida82ef184712e092aec1381a47aa1b54b74ed6b6
Signed-off-by: Chris Ching <chingcodes@google.com>
Reviewed-on: https://review.coreboot.org/22123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-23 17:18:32 +00:00
Nicola Corna 5da1e3156c mb/sapphire/pureplatinumh61: Remove S3 resume delay
It seems that recent changes in coreboot have fixed the raminit issues
on this board; the workaround of 10 ms delay after the S3 resume is not
needed anymore and can be removed.

Change-Id: If8fb97ecf3eb797f53270a053201fafd32031678
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/21485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-23 17:04:26 +00:00
Matt DeVillier fd0a891ee9 drv/intel/gma/opregion: fix opregion version for Windows
Although Intel's current spec[1] shows the OpRegion structure version 
as being the top 16 bits of the field, Intel's Windows drivers
require the OpRegion structure version to be in the top 8 bits of
the field when not using a VGA BIOS (eg, NGI or GOP driver).

As the Linux i915 driver only checks that the version is >= 2,
there is no change in functionality there.

This change effectively matches Intel's implementation in TianoCore,
where the version is set to 0x0200 << 16.

[1] https://01.org/sites/default/files/documentation/skl_opregion_rev0p5.pdf

TEST: Boot Windows [8.1,10] in UEFI mode w/GOP graphics init and
Legacy mode with libgfxinit, observe Intel GPU driver functional.

Change-Id: Ic2903ee4829689ec4117aec93dce0b87cec6f313
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-10-23 16:58:35 +00:00
Matt DeVillier fb1cd09596 purism/librem13v2: migrate from FSP 1.1 to 2.0
Migrate the Librem13v2 from using FSP 1.1 to
the public/GitHub FSP 2.0 Skylake/Kabylake release:

- select FSP 2.0 in Kconfig
- adjust romstage/ramstage functions as required
- refactor pei_data functions
- remove VR_RING domain from devicetree (unsupported in FSP 2.0)
- add SataSpeedLimit parameter to work around power-related issue
  when operating at SATA 6.0Gbps speed

TEST: build/boot Librem13v2, observe successful boot, lack of
SATA-related errors in dmesg.

Change-Id: Iedcc18d7279409ccd36deb0001567b0aa5197adf
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-23 16:56:37 +00:00
John Zhao 9b6384c1a5 soc/intel/cannonlake: Increase stack size from 4KiB to 8KiB
Backtracking stack used BEFORE each function call:
1. cbfs_boot_locate(&file_desc, "vbt.bin", NULL): 4104 (stack overrun)
2. locate_vbt: 4068
3. vbt_get: 4036
4. platforms_fsp_silicon_params_cb: 3924
5. do_silicon_init(&fsps_hdr): 3684 (3684-1092=2592 due to fsps)
6. fsp_silicon_init: 1092

Increase the stack size from 4kiB to 8kiB to prevent stack overrun.

TEST=No stack overrun is observed and it boots to OS properly.

Change-Id: I7e458b4489cea32449f197621ec81009ea7dd0bd
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21977
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-23 16:40:01 +00:00
ren kuo 2f1b7aaa3e mainboard/google/coral: Add USB2 phy setting override for Astronaut
In order to pass type C USB2 eye diagram for sku Astronaut,
USB2 port#1 PHY register needs to be overridden.

sku ID:0,1 Astronaut (USB)
port#1:
PERPORTPETXISET = 7
PERPORTTXISET = 2

sku ID:61,62 Astronaut (LTE)
port#1:
PERPORTPETXISET = 7
PERPORTTXISET = 5

BUG=b:68120012
BRANCH=master
TEST=emerge-coral coreboot chromeos-bootimage

Change-Id: Icf5c9e5f4dae15630ec4d6ca6648cae78ca910c6
Signed-off-by: Ren Kuo <ren.kuo@quantatw.com>
Reviewed-on: https://review.coreboot.org/22135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-23 15:12:10 +00:00
Patrick Rudolph bb98b38b93 nb/intel/pineview: Port ACPI opregion to pineview
Port the ACPI opregion implementation that resides in
drivers/intel/gma to older platforms. It allows to include a vbt.bin and
allows GNU/Linux to load the opregion as ASLB is being set.

Windows' Intel will likely ignore it as it relies on legacy VBIOS
to be loaded at 0xc0000.

Change-Id: Ifc9fc52d84dcbb0da577e61467ece8a48752f44b
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-22 02:21:23 +00:00
Vagiz Trakhanov 177f7731aa superio/ite/common: Make PECI a thermal mode
Instead of setting "peci_tmpin" in the devicetree, THERMAL_PECI is now
a mode of TMPIN like THERMAL_RESISTOR and THERMAL_DIODE. Since the logic
to set temperature offsets and limits is in the function that sets
thermal modes, it makes sense to treat PECI as yet another mode.

As of this commit, there are no boards that actually use peci_tmpin from
ite/common. There are three boards that have a similar device tree
option, but those boards use it8772f, which implements all superio
functions on its own.

The first user will probably be Gigabyte GA-Z77-DS3H.

Change-Id: I39da50c124ad767f8681302733cf004622975e81
Signed-off-by: Vagiz Trakhanov <rakkin@autistici.org>
Reviewed-on: https://review.coreboot.org/22076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-22 02:20:34 +00:00
Vagiz Trakhanov cc9c0cbc7e superio/ite/common: Add temperature limits
Add devicetree options to set temperature limits that are used to alarm
user when temperature exceeds defined values.

Audio alerts by superio are not implemented yet, but since limits are
visible to userland, some software might use them as is. For instance,
lm-sensors displays "ALERT" when temperature exceeds limits.

Change-Id: I56e041fb78f518d6a9640dc2b3985459991242b9
Signed-off-by: Vagiz Tarkhanov <rakkin@autistici.org>
Reviewed-on: https://review.coreboot.org/21844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-10-22 02:19:56 +00:00
Vagiz Trakhanov 17c5771530 superio/ite/common: Add temperature offset
Add a devicetree option to set temperature adjustment registers
required for thermal diode sensors and PECI. However, this commit does
not have the code needed to make PECI interface actually use these
registers. It only applies to diodes.

As a temporary workaround, one can set both THERMAL_DIODE and peci_tmpin
to the same TMPIN, e.g. TMPIN3.mode="THERMAL_DIODE" and peci_tmpin="3".
PECI, apparently, takes precedence over diode, so the adjustment register
will be set and PECI activated. Or simply use the followup patch, which
makes THERMAL_PECI a mode like THERMAL_DIODE.

I don't have hardware to test THERMAL_DIODE mode, but in case of PECI,
without this patch I had about -60°C on idle. Now, with offset 97,
which was taken from vendor bios, PECI readings became reasonable 35°C.

TEST=Set a temperature offset, then ensure that the value you set is
reflected in /sys/class/hwmon/hwmon*/temp[1-3]_offset

Change-Id: Ibce6809ca86b6c7c0c696676e309665fc57965d4
Signed-off-by: Vagiz Tarkhanov <rakkin@autistici.org>
Reviewed-on: https://review.coreboot.org/21843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-10-22 02:19:15 +00:00
Lijian Zhao c85890d0d8 soc/intel/cannonlake: Change max root port to 16
Cannonlake SOC support up to 16 PCI express root port.

BUG=CID 1381813;1381814;

Change-Id: I4df610e3fb01bd8e62be7e9c62144125f2a96c25
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-22 02:17:24 +00:00
Philipp Deppenwiese fea2429e25 security/vboot: Move vboot2 to security kconfig section
This commit just moves the vboot sources into
the security directory and fixes kconfig/makefile paths.

Fix vboot2 headers

Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-22 02:14:46 +00:00
Matt DeVillier 9e0d69bf1e soc/intel/skylake: pass SataSpeedLimit param to FSP2
The Librem13v2 needs to set this parameter to work around
power-related issues with some SATA devices.

Change-Id: I7fcef36ec8662e18834394b72427a0633c6b7e92
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22045
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-22 01:58:22 +00:00
Youness Alaoui c25c998888 purism/librem13v2: Update microcode length in CBFS
Microcode blob has been updated, so update the length to match

Change-Id: I46ac10e5c6cd6492c98a7034649797f301101abc
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-22 01:58:16 +00:00
Youness Alaoui a8b35be75e purism/librem13v2: Fix USB settings and set OC pin
The USB settings were wrong in some places, or missing and the
USB_OC values were taken from the schematics.

Change-Id: I29b564a4161c486f5e8556b1726471bfa2351b7a
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/22043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-22 01:58:11 +00:00
Youness Alaoui c5b9658961 purism/librem13v2: Update devicetree settings
Disable SataDevSlp and update other values to match vendor/AMI firmware.

Change-Id: I6f278be54b86450575c366d68bfa6a67575b0fdd
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-22 01:58:06 +00:00
Youness Alaoui 3d60718f82 purism/librem13v2: Change DRAM Rcomp/DQS values
The RComp values have been updated to match what is shown in the schematics.

Extracting the Memory configuration blob from the original BIOS (A blob
which contains the correct binary sequence matching the RComp values appears
in object with GUID 2D27C618-7DCD-41F5-BB10-21166BE7E143), I could find
and confirm the DQ and DQS mapping.

Small code cleaning in romstage.c with no effect.

Change-Id: I35c734269b365fd759e9bd56224a80a8a8df5a57
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/22041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2017-10-22 01:58:01 +00:00
Youness Alaoui c0a32cad28 purism/librem13v2: Add reading of serial number from CBFS
Check CBFS for 'serial_number' field, and use value if exists;
otherwise use value set at compile time.

Change-Id: I4b50f6310ca32b9dd372db075a5b5729e3b06619
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/22040
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-22 01:57:56 +00:00
Youness Alaoui e0603e3183 skylake/me: Add debug output of HFST registers
The ME status is the interpretation of the status registers, but
having the actual status registers printed is important and it doesn't
hurt to show them.

Change-Id: I6ef3401b36fedfa8aed14f4a62bdbec3d8c6d446
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/21960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-22 01:48:59 +00:00
Marshall Dawson 251e8a8d8a google/kahlee: Add PSP to devicetree.cb
Add the missing device and ensure it shows up in the devicetree prior
to PCI enumeration.

Change-Id: Ia2c4ba1200422b36c533e86065a4fcd10c4b2722
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22055
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-22 01:45:39 +00:00
Marshall Dawson cb23e0f71d amd/gardenia: Add PSP to devicetree.cb
Add the missing device and ensure it shows up in the devicetree prior
to PCI enumeration.

Change-Id: I44c7df6a2be149ed61094f67ef1c578736e5b55c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-22 01:45:35 +00:00
Marshall Dawson 3191e0fcf5 soc/amd/common: Revert PI blob search hack
Remove the check for CONFIG_VBOOT when finding the binaryPI blob and
rely on the cbfs search 100% of the time.  The change was initially
put in to avoid a hang when vboot presearched memory for the blob.
The implementation now supports early cbmem init and cbmem_top() is
careful to return 0 if DRAM has not yet been set up.  As a result the
hang no longer occurs and the hack may be removed safely.

BUG=b:67747902

Change-Id: I1f38709fcce250b0902a639ebf0554219bc47cf8
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-22 01:45:23 +00:00
Philipp Deppenwiese 1899fbe420 src/security: Add security kconfig stub
Change-Id: I965bf87d8673e22c088093f0fa17e93dbb9a00d9
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-22 01:43:54 +00:00
Nico Huber ec69c48353 mb/google/link: Enable libgfxinit
Beside the high-resolution eDP panel, it features a dual-mode
mini-DP port.

Change-Id: Iae60c1f930f5778ee3b5d9d19227168257e9ae06
Tested-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2017-10-22 01:39:37 +00:00
Chris Ching 268e1f9119 soc/amd/stoneyridge: Remove duplicate macros in pci_devs.h
BUG=b:68046770
TEST=build

Change-Id: Iea0df0dc7baa384cac45a300fdcc8d59f0aac798
Signed-off-by: Chris Ching <chingcodes@google.com>
Reviewed-on: https://review.coreboot.org/22114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-22 01:38:50 +00:00
Werner Zeh bd31642ad8 intel/i210: Set bus master bit in command register
There are still Ethernet drivers out there in the wild which expect
that the master enable bit was set by firmware. A missing master
enable bit will lead to a non-functional driver. Though it is clear the
task of the driver to set this bit it is too late now. So work around
this issue on firmware level...again!

Change-Id: I677b22c643b73634b1a2129d948b991446e1f8fd
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/22036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2017-10-22 01:38:12 +00:00
Marc Jones b6ac3a2997 kahlee: Set Kahlee GPEs
Add GPE configuration table.

Remove GPE3 from the power button ASL and set the EC to GPE3(AGPIO22).

Set the EC and PCIE/WLAN SCI GPIO signals.

Set GPE ASL methods for:
  PCIE/WLAN      8h
  EHCI          18h
  XHCI          1fh
Note EC GPE3 methods are in the EC ASL.

BUG=b:63268311
BRANCH=none
TEST=Test lidswitch powers the device on and off at the login screen.

Change-Id: I27c880ee84b6797d999d4d5951602b654ede948e
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22096
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-20 22:57:43 +00:00
Shelley Chen 794d222886 cr50_enable_update: Add printk before EC hibernate
Add printout before EC hibernates during a cr50 update to clarify that
failure is due to EC rather than cr50.  Ran into a situation where DUT
shut down during cr50 update and the EC was the culprit.

BUG=None
BRANCH=None
TEST=None

Change-Id: I54813fec123de69604d1da4dfc65eaeb77d1662e
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/22120
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-10-20 22:49:50 +00:00
Shelley Chen bdfc5f5790 google/fizz: Set PL2 value based on sku id/charge max power
Set PL2 based on either 90% of usb c charger's max power or sku id if
using a barrel jack.

BUG=b:37473486
BRANCH=None
TEST=output debug info for different skus and make sure
     PL2 set correctly.

Change-Id: I487fce4a5d0825a26488e71dee02400dbebbffb3
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/21772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-20 22:49:42 +00:00
Shelley Chen ebd533065f chromeec: Add function to retrieve usb c charger info
Add google_chromeec_get_usb_pd_power_info(), which will
call the EC_CMD_USB_PD_POWER_INFO host command to retrieve
the current and voltage info of the usb c charger.
Returns power info in watts.

BUG=b:37473486
BRANCH=None
TEST=output debug info to make sure that correct power
     is returned.

Change-Id: Ie14a0a6163e1c2699cb20b4422c8062164d92076
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/21771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-20 22:49:31 +00:00
Aaron Durbin bd885c5bac lib/gpio: constify array inputs
The arrays of gpio_t are not manipulated in any way within the
gpio library. Add const to indicate that.

Change-Id: Ie32ab9de967ece22317e2b97b62e85b0757b910d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-20 22:49:27 +00:00
Marc Jones e8e72bd0ca stoneyridge: Add SCI/GPE configuration
Add functions for configuring the GPE ACPI SCI events.

BUG=b:63268311
BRANCH=none
TEST=With the Kahlee GPE setup patch, test lidswitch powers
the device on and off at the login screen.

Change-Id: I5c282268edbd7b92a3f2ca7c72896406c8f8512f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-20 21:32:29 +00:00
Marc Jones f1c8ea35b3 soc/stoneyridge: Remove _PRW ASL
Remove _PRW GPE settings from GPP and USB ASL. The mainboard sets
the GPEs.

In addition, Stoney Ridge GPPs don't generate a GPE/SCIs.

Change-Id: Ib6a07a997bc3508109a67867014210091efc0c99
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-20 21:32:23 +00:00
Marc Jones 2e8476c35d stoneyridge: Fix USB ASL
Stoney Ridge has one EHCI controller and one XHCI controller.
Also, update the Kahlee and Gardenia mainboards ASL to match.

Change-Id: I5749ca0640796732e74e551147f8c4446317b77e
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-20 21:32:16 +00:00
Lijian Zhao c866f878bc intel/cannonlake_rvp: Update board name
Change the board name from cannonlake U DDR4 to U LPDDR4 to match
actual platform.

TEST=NONE

Change-Id: Id350e3cbc299d49431197ef5f914ea9a7310a0a5
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-10-20 20:52:50 +00:00
Lijian Zhao 6a09eee4ad soc/intel/cannonlake: Add platform.asl
Include common platform.asl to have generic indication of power
transition state of system.

TEST=Enter and resume from S3, check the post code had been changed to
0096 and 0097.

Change-Id: Ic38ac6d7e60441caeba5c088c9dbe4d901355782
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22111
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-10-20 20:52:46 +00:00
Pratik Prajapati 418535e222 soc/intel/skylake: update GNVS with SGX data
- Call sgx_fill_gnvs to update GNVS data, if
  CONFIG_SOC_INTEL_COMMON_BLOCK_SGX is set.
- With this patch SGX ACPI device would get pached with enumaretd values
  of ECP device status, base address and length

Change-Id: Ief0531fbab34838a3f8adb9cdc7d3fe19203c432
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-20 20:06:33 +00:00
Pratik Prajapati d06c7646ac soc/intel/apollolake: update GNVS with SGX data
Call sgx_fill_gnvs to update GNVS data, if
CONFIG_SOC_INTEL_COMMON_BLOCK_SGX is set.

Change-Id: I692f466d2c6f537d44aa042c4890ee8055c982c8
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-20 20:06:26 +00:00
Pratik Prajapati 0e5eb46bb7 intel/common/block/sgx: Add API to enumerate SGX resources and update GNVS
Intel SDM: Table 36-6. CPUID Leaf 12H, Sub-Leaf Index 2 is called
to enumerate SGX resources.

Change-Id: I62f3fd8527e27040336c52bc78768035f4b7e5a9
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-20 20:06:21 +00:00
Pratik Prajapati 90ebf96df5 soc/intel/skylake: Add GNVS variables and include SGX ASL
- Add GNVS variables for SGX
- Include SGX ASL if CONFIG_SOC_INTEL_COMMON_BLOCK_SGX is set
- With this patch SGX ACPI device would get created and kernel SGX
  driver would let loaded

Change-Id: Ie95eb79a01e1c0005e0f137b015b7fe000c1ab2a
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-20 20:06:15 +00:00
Pratik Prajapati 03a2353df6 soc/intel/apollolake: Add GNVS variables and include SGX ASL
- Add GNVS variables for SGX
- include SGX ASL if CONFIG_SOC_INTEL_COMMON_BLOCK_SGX is set
- With this patch SGX ACPI device would get created and kernel SGX
  driver would let loaded

Change-Id: I112cad3cd871082b1884787084c4cc0ebdc7d08f
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-20 20:06:02 +00:00
Pratik Prajapati 771d4833d1 intel/common/acpi: Add common SGX ASL
- Add EPC device for SGX. Kernel SGX driver expects EPC device.
- Hid is INT0E0C
- version of the object is 1.0, so _STR is "Enclave Page Cache 1.0"

Change-Id: I9efba46469a125ea99241b04fe1ae550d6e03598
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-20 20:05:53 +00:00
Martin Roth ba142c5ef0 vendorcode/amd/pi/00670F00: Remove S3 restore functions
These functions are not currently used, and were not in the original
AGESA source code drop.

The structs involved here were marked "private" in AGESA headerfiles
and should not be exposed. They could be handled as anonymous structs
and required allocation size is communicated by other means.

BUG=b:64766233
TEST=Build in cros tree and upstream coreboot, with old headers
and updated headers.

Change-Id: Iec346205470150257fd9d09131d54231b321740b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-10-20 17:49:02 +00:00
Martin Roth 2960043155 soc/amd/common: Set AltImageBasePtr to 0
In the original AGESA headers, AltImageBasePtr is a UINT32, so don't
set it to VOID.  0 works for either UINT32 or VOID *, as demonstrated
by the other 7 places in this file where it's already set to 0 instead
of NULL.

Change this location to 0 to support either version of the headers.

BUG=b:64766233
TEST=Build in cros tree and upstream coreboot, with old headers
and updated headers.

Change-Id: Ib6f3883e08231a6ca896c2ee2ef631c77feafedd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-20 17:48:56 +00:00
Martin Roth 7eb363c505 Stoney Ridge Platforms: cast AGESA tables to void *
In the original AGESA headers, these tables are not defined as const.
Cast them to void * so that they'll work with either version of the
headers.

BUG=b:64766233
TEST=Build in cros tree and upstream coreboot, with old headers
and updated headers.

Change-Id: I75387b57caf5a3c6c25655120aafd942254b5c73
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22059
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-20 17:48:49 +00:00
Martin Roth c450fbe909 Stoney Ridge Platforms: Make AGESA callout tables common
There was no reason to have the AGESA callout tables in each mainboard,
so move them to soc/amd/common.

Move chip specific functions into the stoneyridge directory:
- agesa_fch_initreset
- agesa_fch_initenv
- agesa_ReadSpd

Combine agesa_ReadSpd and agesa_ReadSpd_from_cbfs, and figure out which
to use.

Soldered-down memory still needs to be supported in a future commit, as
stoney supports both DDR3 & DDR4.  A bug has been filed for support for
the upcoming Grunt platform.

BUG=b:67209686
TEST=Build and boot on Kahlee

Change-Id: Ife9bd90be9eb0ce0a7ce41d75cfef979b11e640b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-20 17:48:37 +00:00
Kamil Wcislo 70b92456eb mainboard/pcengines/apu2: add apu3 and apu5 variants
Apu3 and apu5 are additional variants of apu2 board.
Apu3 has no LPC connector exposed, but has additional USB header. It has
also 2 slots for SIM cards and one of the gpios is used to control
switching between them.
Apu5 is differing by having 6 SIM card slots (3 SIMSWAP switches).

This patch adds support for those other variants by not introducing
additional code redundancy.

Change-Id: I4fded98fed7a8085062cdea035ecac3d608cd2a0
Signed-off-by: Kamil Wcislo <kamil.wcislo@3mdeb.com>
Reviewed-on: https://review.coreboot.org/21981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-10-20 02:19:23 +00:00
Chris Ching 6a35fab272 soc/amd/stoneyridge: Use macros for PCI_DEVFN calls
* Change all calls to PCI_DEVFN to macros
 * Remove CBB and CDB Kconfig since these are static for stoneyridge

BUG=b:62200746
TEST=build

Change-Id: I001c4ccd0ad7cf2047870b3618e13642144ddf56
Signed-off-by: Chris Ching <chingcodes@google.com>
Reviewed-on: https://review.coreboot.org/22110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-19 21:07:10 +00:00
Richard Spiegel c5ecd3e14d soc/amd/stoneyridge: Replace magic registers
Replace southbridge registers and register values from magic numbers to
literals, provided these registers are currently defined publicly or in
NDA datasheet.

Registers available only internally to AMD are left unchanged.

BUG=b:62199625

Change-Id: I9187ba1c41ebb1201ddc177e8184672c60cd5f5d
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-19 20:52:51 +00:00
Lijian Zhao 025e0ccc59 intel/fsp: Update cannonlake FSP header
Update cannonlake FSP header file to revision 7.x.15.46. The following
item had been updated:
1. Remove/Hide restricted structure.
2. Add EBR as extention of RMT features.
3. Add cpu wakeup timer UPD.
4. Remove XHCI access lock UPD.

TEST=NONE

Change-Id: I065edbeffdaf555ea7d54ec3fdce56d026789c52
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19 19:56:06 +00:00
Lijian Zhao e7a1e7d3c4 soc/intel/cannonlake: Fix HECI error on reset
Move HECI init from bootblock to romstage, the HECI bar saved by
CAR_GLOBAL, which will be lost on different stage. HECI BAR in ramstage
will be read back from PCI. Also add fail safe option to reset in case
of HECI command not successful.

TEST= Force global reset from FSP and read back HECI bar in debug print.

Change-Id: I46c4b8db0a80995fa05e92d61357128c2a77de4b
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19 19:48:43 +00:00
Subrata Banik ed1694157c soc/intel/cannonlake: Use EBDA structure to store soc reserve memory size
Avoid calling calculate_dram_base() function to get chipset reserved
memory size during pci resource allocation. Rather use EBDA to store
chipset reserved memory size while calling cbmem_top_int().

This patch avoids one extra calculate_dram_base() call.

BRANCH=none
BUG=b:63974384
TEST=Ensures DRAM based resource allocation has taken care of Intel
SoC reserved ranges.

Change-Id: I2771ea55253ca7d16cd2e2951889ab092b47a9b1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22099
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-19 17:36:16 +00:00
Subrata Banik f506cf0b8d soc/intel/skylake: Use EBDA structure to store soc reserve memory size
Avoid calling calculate_dram_base() function to get chipset reserved
memory size during pci resource allocation. Rather use EBDA to store
chipset reserved memory size while calling cbmem_top_int().

This patch avoids one extra calculate_dram_base() call.

BRANCH=none
BUG=b:63974384
TEST=Ensures DRAM based resource allocation has taken care of Intel
SoC reserved ranges.

Change-Id: I52f359db5a712179d7f2accb4d323d759f3b052b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19 17:36:06 +00:00
Abhay Kumar b0c4cbb7af soc/intel/cannonlake: Add IGD Support and pre-OS display code
1. Add IGD opregion initialization.
2. Use frame buffer return by FSP for display.
3. Derived from "src/soc/intel/apollolake/graphics.c" with changes
   needed for CNL.

TEST=Pre-OS screen comes up and VBT is getting passed to kernel.

Change-Id: I19c0cf6cfc03fc9df9e98c75af4e486cb5a19e32
Signed-off-by: Abhay Kumar <abhay.kumar@intel.com>
Reviewed-on: https://review.coreboot.org/21999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-19 15:19:36 +00:00
Werner Zeh 0e35eb2434 siemens/mc_bdx1: Initialize GPIOs
Add GPIO initialization for mc_bdx1 mainboard. Call init_gpios() as
early as possible as FSP will set up things (like hiding PCI devices)
rather early. If connections on the mainboard are dependent on GPIO
settings then FSP can screw things up (e.g. disabling not yet connected
PCI root ports).

Change-Id: I003277cfb871f861900b7fcdc5ec851d4c1c1e6a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/22035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19 15:13:45 +00:00
Werner Zeh 4bf11ce2b5 soc/fsp_broadwell_de: Add support for GPIO handling
Add functionality to initialize, set and read back GPIOs on FSP based
Broadwell-DE implementation.

Change-Id: Ibbd86e2142bbf5772eb4a91ebb9166c31d52476e
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/22034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19 15:13:40 +00:00
John E. Kabat Jr e77d588ee4 cpu/x86: add AMD registers to SMM save state
In amd64_smm_state_save_area_t break out fields in reserved4 to allow access.

BUG=b:65485690

Change-Id: I592fbf18c166dc1890010dde29f76900a6849016
Signed-off-by: John E. Kabat Jr <john.kabat@scarletltd.com>
Reviewed-on: https://review.coreboot.org/22092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-19 15:13:18 +00:00
Vagiz Trakhanov 216ad2170c sb/intel/bd82x6x: Add new USB currents
These currents were found on Gigabyte GA-Z77-DS3H with vendor bios.

Change-Id: I547c4ab3a2ce507d013ed527ab81291a916ce9b5
Signed-off-by: Vagiz Tarkhanov <rakkin@autistici.org>
Reviewed-on: https://review.coreboot.org/21845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-10-19 15:07:16 +00:00
Vagiz Trakhanov 771be480a6 nb/sandybridge: Add a kconfig option to ignore XMP max DIMMs
XMP profiles can have a restriction on max supported DIMMs per channel,
but many configurations work with more DIMMs.

This is relevant on mainboards with 2 DIMM slots per channel (usually 4
in total). Populating both slots with DIMMs that support XMP profiles only
with 1 DIMM per channel turns off said XMP profiles.

TEST=On a system with two DIMM slots per channel populate both slots on
one channel and ensure that DIMMs run with XMP profiles enabled.

Change-Id: I1f22d981afcef0ee73785823b0a943cf3d3564e3
Signed-off-by: Vagiz Trakhanov <rakkin@autistici.org>
Reviewed-on: https://review.coreboot.org/21841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-10-19 15:06:13 +00:00
Martin Roth 15cb5be5b0 src/vendorcode/amd: Use AR variable in Makefiles
Change-Id: I5158f1bcc18eb5b15f310d0cf50fb787c12317c8
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-19 14:03:51 +00:00
Kyösti Mälkki e097585fdf AGESA f14: Fix DDI maps in OemCustomize.c
Creates identical object files.

Change-Id: Ie8adb21a753cee6a72dae5eeb64a255e6ead2fe7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-19 11:24:19 +00:00
Kyösti Mälkki 9fee35c6c4 AGESA: Split long lines in OemCustomize.c
Change-Id: I907f55622e6aaba401471239f706ab24cd26319f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-19 11:24:09 +00:00
Kyösti Mälkki c700829cd3 AGESA f14: Drop PlatformGnbPcieComplex.h
These were OEM configurations hidden inside a header file, notation
was already dropped for f15tb and f16kb.

Change-Id: Id64fa861fd516e9f7cae9eba9b8145e033fe9bdd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-19 11:23:53 +00:00
Michał Żygowski 57760e3cdf pcengines/apu2: Add timestamps to romstage
This change adds timestamps to romstage in order to keep
PC Engines apu2 platform in active codebase.

Change-Id: Ie0286d4982623da9d035c47df6077edaf51e5110
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/22071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-19 11:23:29 +00:00
Paul Menzel 4e4a763703 Enable time stamp collection by default on x86
Collecting time stamps is useful, especially for board status uploads,
and doesn’t come with any downsides. So enable it by default on as many
boards as possible.

The boards below currently fail to build properly, so only enable it by
default on x86.

1.  board.CUBIETECH_CUBIEBOARD
2.  board.EMULATION_QEMU_POWER8
3.  board.EMULATION_QEMU_UCB_RISCV
4.  board.EMULATION_SPIKE_UCB_RISCV
5.  board.LOWRISC_NEXYS4DDR
6.  board.TI_BEAGLEBONE

Change-Id: Ib01176fc2a4dffe37827c136bb8214083ce61180
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/11864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-10-19 09:10:49 +00:00
Furquan Shaikh 1432cbc4da google/chromeec: Do not set wake mask before logging EC events
Earlier the EC expected the host to set appropriate masks before
reading host events. However, with recent change in EC, this is no
longer required. This change removes the setting of wake_mask before
and after reading the host events. However, in order to support older
versions of EC, a new feature flag is added on the EC side that
informs the host whether or not it is using the new way of reporting
host events without having to set wake mask.

CQ-DEPEND=CL:719578
TEST=Verified that EC wake events are correctly logged with both old
and new versions of EC.

Change-Id: Ib17e1296fb7d3bbc84fc7581fd0a9bd179ac87b9
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22006
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-19 00:44:31 +00:00
Furquan Shaikh 4854761ba4 mb/google/poppy: Log EC events during S0ix resume
This change adds support for logging EC events during S0ix resume.

BUG=b:67874513
TEST=Verified that EC events are correctly logged during S0ix resume:
284 | 2017-10-16 20:45:12 | S0ix Enter
285 | 2017-10-16 20:45:16 | S0ix Exit
286 | 2017-10-16 20:45:16 | Wake Source | Power Button | 0
287 | 2017-10-16 20:45:16 | EC Event | Power Button
288 | 2017-10-16 20:45:35 | S0ix Enter
289 | 2017-10-16 20:45:40 | S0ix Exit
290 | 2017-10-16 20:45:40 | Wake Source | GPIO | 112
291 | 2017-10-16 20:45:40 | EC Event | Lid Open
292 | 2017-10-16 20:50:51 | S0ix Enter
293 | 2017-10-16 20:50:59 | S0ix Exit
294 | 2017-10-16 20:50:59 | Wake Source | GPIO | 112
295 | 2017-10-16 20:50:59 | EC Event | Mode change

Change-Id: I9f6dcb8852d94ebf90bb5b63a17fde524d58d49f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19 00:43:56 +00:00
Furquan Shaikh 70b257f1b4 ec/google/chromeec: Export google_chromeec_log_events in ec.h
This change makes google_chromeec_log_events available to callers
outside ec.c.

BUG=b:67874513

Change-Id: I36cc1e66e035eda707297d8153cd3fabeadfee45
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19 00:43:51 +00:00
Furquan Shaikh dd825fe73e soc/intel/skylake: Probe XHCI for wake source for Internal PME
If GPE_STS indicates that the wake source is internal PME, but none of
the controllers have the PME_STS bit set, then try probing individual
XHCI ports to see if one of those was a wake source. In some cases
e.g. gsmi logging with S0ix, pci_pm_resume_noirq runs before gsmi
callback and clears PME_STS_BIT in controller register. In such cases,
xhci port status might provide a better idea about the wake source.

BUG=b:67874513

Change-Id: I841bb2abccfa9bd6553c1513e88a6306b40315e4
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19 00:43:45 +00:00
Furquan Shaikh 7284efe594 soc/intel/skylake: Prevent false logs in pch_xhci_port_wake_check
1. Ensure that port_status read is not all 1s to ensure that read from
mmio address returned valid data.
2. If device connect/disconnect shows that it was a wake source, there
is no need to check for usb activity.

BUG=b:67874513

Change-Id: Id8b4a1fec7bfe530fe435a0f52944b273cdd89ad
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19 00:43:39 +00:00
Furquan Shaikh 8f2eadd8d0 soc/intel/skylake: Define mask for SMI handlers that can be run in SCI mode
This change adds a mask to allow SMI handlers to be run even in SCI
mode. This prevents any SMI handlers from accidentally taking
unnecessary action in SCI mode.

Add APM_STS and SMI_ON_SLP_EN_STS to this mask to allow gsmi and sleep
to work in SCI mode.

BUG=b:67874513

Change-Id: I298f8f6ce28c9746cbc1fb6fc96035b98a17a9e3
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19 00:43:34 +00:00
Furquan Shaikh c565bd44d1 soc/intel/skylake: Support logging wake source in SMM
This change adds support for logging wake source information in gsmi
callbacks. With this change, all the elog logging infrastructure can
be used for S0ix as well as S3 on skylake.

BUG=b:67874513

Change-Id: Ie1f81e956fe0bbe2e5e4c706f27997b7bd30d5e0
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19 00:43:30 +00:00
Furquan Shaikh 3efeeb2c8f soc/intel/skylake: Move power_state functions to pmutil.c
This change moves soc_fill_power_state and soc_prev_sleep_state to
pmutil.c. It allows the functions to be used across romstage and smm.

BUG=b:67874513

Change-Id: I375ac029520c2cdd52926f3ab3c2d5559936dd8c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22085
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-19 00:43:22 +00:00
Furquan Shaikh 2ce4ec0dcb soc/intel/skylake: Use PCH_DEV_* instead of PCH_DEVFN_*
This change allows the same functions to be used across ramstage and
smm without having to add checks for what stage is using it.

BUG=b:67874513

Change-Id: I3b10c9e8975e8622d8cb0f66d90d39a914ba7e1c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19 00:43:17 +00:00
Furquan Shaikh a2480184e0 soc/intel/skylake: Use newly added pmc_read_pm1_control
BUG=b:67874513

Change-Id: I298065f30647ae9bba8f6a8481bd34eec64f1d8e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19 00:43:11 +00:00
Furquan Shaikh 43810d9332 soc/intel/apollolake: Use newly added pmc_read_pm1_control
BUG=b:67874513

Change-Id: I6d5a76122b7d6e508e5ff3f4099e5d706fb48f9d
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19 00:43:05 +00:00
Furquan Shaikh ab6201835a soc/intel/common/block/pmc: Add helper routines to read/write PM1_CNT
This change adds and uses helper routines for reading and writing
PM1_CNT register.

BUG=b:67874513

Change-Id: I69b9347ab54a392b67ba733eb00922583dc1ee5f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22081
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-19 00:42:58 +00:00
Furquan Shaikh e48fb54b16 soc/intel/common/block/pmc: Add new function pmc_fill_pm_reg_info
This change creates a new function pmc_fill_pm_reg_info that fills
chipset_power_state structure with all the PM register
information. On the other hand, already existing pmc_fill_power_state
calls into pmc_fill_pm_reg_info and then checks and returns previous
sleep state information. This allows caller to get all the PM register
information when previous sleep state is not relevant.

BUG=b:67874513

Change-Id: Idc91e4aef5379549355aceb685f7afafa6a220c5
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22080
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-19 00:42:53 +00:00
Furquan Shaikh 2dc5eadccc elog: Support logging S0ix sleep/wake info in elog
1. Add support for new GSMI commands to log S0ix entry/exit
information in elog.
2. In case of resume, provide callbacks to allow platform and
mainboard to log any wake source information.

BUG=b:67874513

Change-Id: I593e8a9e31cad720ac1f77aab447a0dbdbe9a28b
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19 00:42:49 +00:00
Vaibhav Shankar f36ed21c57 mainboard/intel/cannonlake_rvp: Enable hardware P state control
This patch provides configuration parameter to enable/disable
Intel Speed Shift Technology.

Change-Id: I95a240e8be6e19ac0e14698ab33543c491a8c974
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/22049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-18 20:07:45 +00:00
Aaron Durbin f46a9a0d3a arch/x86: restore forwarding table on resume for EARLY_EBDA_INIT
In commit c06a3f72 (arch/x86: initialize EBDA in S3 and S0/S5 path)
the BDA and EBDA are wiped in the resume path. However, the coreboot
table forwarding entry wasn't taken into account so that was wiped
which resulted in cbmem not working on the resume path. Fix this
by stashing the forwarding table in cbmem and restoring it on
the resume path.

Change-Id: I142503535a78635fbb1c698fc7d032c1a2921813
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-10-18 19:56:21 +00:00
Lijian Zhao c672043766 soc/intel/cannonlake: Set platform Debug Probe Type
Add option for user to select what kind of probe can be used for
platform debug.

TEST=Set to XDP and boot up system with XDP hooked, able to halt.

Change-Id: Ib6add93e3f1c8a646aa625a4cea9be0acecc0487
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21942
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-18 19:56:09 +00:00
Lijian Zhao 584af87483 intel/cannonlake_rvp: Enable Audio DSP
Enable Audio DSP by default on cannonlake rvp platform.

TEST=Boot up into OS and check Audio driver debug print.

Change-Id: I6892c6d349019550c967ef30b84d385f396fc388
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-18 19:55:49 +00:00
Lijian Zhao 0b21ad9e80 intel/cannonlake_rvp: Declare PCIE clock usage
Define PCI express clock usage for cannonlake u and cannonlake y rvp
based on board design.

TEST=Bootable into OS.

Change-Id: I7d71d9a87d87ce6a3e3270f67518afdd54a48db4
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-18 19:46:33 +00:00
Lijian Zhao 580bc412c7 soc/intel/cannonlake: Update PCIE CLKREQ programing
UPD of PCI express clock request was updated in FSP 7.0.14.11,
change that in coreboot accordingly.

TEST=NONE

Change-Id: I2261deccfb489c0de577d580997744a484f07a04
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21878
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-18 19:46:10 +00:00
Lijian Zhao 6cf501c3ae soc/intel/cannonlake: Add finalize function
Before OS boot up, the following actions need to be taken.
1. Lock down PMC/SPI/DMI/TCO register.
2. Disable Sideband Access.
3. Disable Heci interface.
4. Disable PMtimer base on config settings.

TEST=Boot up into OS properly on both cannonlake y and cannonlake u rvp
board.

Change-Id: Icfa05b50fd76fbaeb856d398918990aedac4c5e6
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21943
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-18 17:52:11 +00:00
Kevin Chiu 53660ed499 google/snappy: Override USB2 strength by SKUID
14" BigDaddy needs to override USB2 TxiSet additionally to
enhance driving strength.

Otherwise EA test will fail on USB2 eye pattern.

BUG=b:67820719
BRANCH=reef
TEST=emerge-snappy coreboot
Change-Id: I674c121a71866a5d44439eeb49e07f917d816de8
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/22037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-18 16:01:30 +00:00
Gaggery Tsai c869cd2f44 mb/google/fizz: skip reading SPD data when DUT resumes from S3
This patch skips SPD data reading when system resumes from S3 since
MRC cahce is adopted and validated in fsp_memory_init.

BUG=b:67021596
TEST=Run suspend/resume on Fizz and make sure the systems are
	working well when system resumes from S3. Checked dmidecode
	information and SMBIOS type 17 data is the same with cold
	boot.

Change-Id: I1692fca8456290d1471973b746537b5fec504e03
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/21987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-18 02:13:18 +00:00
Subrata Banik caca9c7c62 soc/intel/cannonlake: Calculate soc reserved memory size
This patch implements soc override function to calculate reserve memory
size (PRMRR, ME stolen, PTT etc). System memory should reserve those
memory ranges.

BRANCH=none
BUG=b:63974384
TEST=Ensures DRAM based resource allocation has taken care
of intel soc reserved ranges.

Change-Id: I3052a255c4496dc81c8dfc6882d3ad504abae9c6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-18 01:14:04 +00:00
Subrata Banik 47569cf3a9 soc/intel/cannonlake: Use EBDA area to store cbmem_top address
This patch uses BIOS EBDA area to store relevent details
like cbmem top during romstage after MRC init is done.
Also provide provision to use the same EBDA data across
various stages without reexecuting memory map algorithm.

BRANCH=none
BUG=b:63974384
TEST=Ensures HW based memmap algorithm is executing once in romstage
and store required data into EBDA for other stage to avoid redundant
calculation and get cbmem_top start from EBDA area.

Change-Id: I763ad8181396ea8d8c0d5cf088264791ba62dceb
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-18 01:13:51 +00:00
Subrata Banik d2cadc39f3 soc/intel/cannonlake: Refactor memory layout calculation
This patch split entire memory layout calculation into
two parts. 1. Generic memory layout 2. SoC specific
reserve memory layout.

usable memory start = TOLUD - Generic memory size -
                   - soc specific reserve memory size.

Change-Id: I56e253504a331c0663efb2b90eaa0567613aa508
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-18 01:10:41 +00:00
Subrata Banik 319e3b4cce soc/intel/cannonlake: Create acpi_get_sleep_type() to get previous sleep state
This patch uses PMC common function to get previous sleep state
using cbmem or chipset_power_state global structure.

acpi_get_sleep_type is needed in PRE_RAM stage when soc selects
CONFIG_EARLY_EBDA_INIT kconfig option.

Change-Id: Ib9f8bdc1c682807450b6c01941b9a0927789b2d8
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-18 01:10:37 +00:00
Furquan Shaikh c1ca65df3f google/chromeec: Drain all MKBP events while clearing host events
EC maintains a FIFO of all MKBP events and sets host event whenever
a new entry is added to the FIFO. Clearing only the host event for
MKBP creates an inconsistent state where there are pending MKBP events
in the FIFO but host event for MKBP is cleared. In order to maintain a
consistent view, host should clear all MKBP events in the FIFO if host
event is being cleared.

This change drains out all the MKBP events in the FIFO when
clear_pending_events is called.

TEST=Verified by adding debug logs in EC to verify that all the MKBP
events that occur before clear_pending_events is called get cleared
from the FIFO.

Change-Id: I131722dc01608dff30230fe341e6b23ae4cc409e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-10-18 00:38:49 +00:00
Furquan Shaikh e01bf6452f google/chromeec: Add new helper function to read MKBP events
This change adds a new helper function google_chromeec_get_mkbp_event
that allows coreboot to query EC for the next available MKBP event.

Change-Id: Ia6d64586ca62378d08025c96c2689c00c816041f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-10-18 00:38:35 +00:00
Bora Guvendik 530c6f9cc8 intel/cannonlake_rvp: enable HS400
Set SCS emmc HS400 enable FSP parameter.

TEST=Boot to OS, verify HS400 SDHCI print

Change-Id: I3ef8a6740ef985a0c51115d9b0ea753b5db2c70d
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/22008
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-10-17 22:49:43 +00:00
Martin Roth de897a6dba soc/amd/stoneyridge: clean up chip.h
Remove obsolete register entries.

BUG=None
TEST=build

Change-Id: Ia9beb9d42f0ee5d63d9e9073507fc606a9d45c46
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-17 18:29:14 +00:00
Furquan Shaikh efe1e2d2d4 soc/intel/common/block/pmc: Move pmc_disable_all_gpe to romstage
Instead of disabling all GPEs during PMC init in bootblock, this
change moves it to pmc_fill_power_state which allows romstage to
correctly fill up GPE_EN registers in chipset_power_state. This is
essential for correctly identifying the wake source.

Disabling all GPEs was added recently in change 74145f76
(intel/common/pmc: Disable all GPEs during pmc_init) because keeping
GPEs enabled in coreboot while enabling SMI could lead to
side-effects as explained in the change. Moving pmc_disable_all_gpe to
pmc_fill_power_state should be safe as that happens before SMI is
enabled in coreboot.

TEST=Verified that GPE-based wake source is correctly
identified. Also, no issues observed while resuming from S3.

Change-Id: I8e992ad09ffdefba62de11fa572e783715776bf1
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22033
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-17 14:45:12 +00:00
Paul Menzel c81bb2cd36 amd/agesa: Remove redundant UDELAY_LAPIC selection
This is already selected in `src/cpu/amd/agesa/Kconfig`.

Change-Id: I691a2ade10ee461b6bc34ea24d57a911281791f3
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/22011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-17 01:40:08 +00:00
Vagiz Trakhanov e200c1cf6f sandybridge/acpi: remove unnessary check of PCI IDs
DRAM Controller is always 00.0. No need to check its PCI ID.

Change-Id: I9c5f3e5658905e464491579f8da01aa6a03bd3b7
Signed-off-by: Vagiz Tarkhanov <rakkin@autistici.org>
Reviewed-on: https://review.coreboot.org/21754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-10-16 20:24:44 +00:00
Vagiz Trakhanov 1dd448c0cf nb/intel: Add Ivy Bridge Server (Xeon-E3v2) PCI IDs
Change-Id: I1899dbe9498a0cc83b65b4bc1c6c0a555637fd05
Signed-off-by: Vagiz Tarkhanov <rakkin@autistici.org>
Reviewed-on: https://review.coreboot.org/21753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-10-16 20:11:46 +00:00
Aaron Durbin c06a3f72f8 arch/x86: initialize EBDA in S3 and S0/S5 path
It's more consistent to re-initialize EBDA in all boot paths.
That way, the data living in EBDA is cleared prior to be
accessed (assuming it's after setup_ebda()).

Change-Id: I05ff84f869f7b6a463e52b4cb954acc5566475cd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2017-10-16 16:56:19 +00:00
Aaron Durbin c714137d95 soc/intel/common: sanity check ebda signature
It's possible for chipsets utilizing ebda to cache the cbmem_top()
value to be called prior to the object being entirely setup. As
such it's important to check the signature to ensure the object
has been initialized. Do that in a newly introduced function,
retrieve_ebda_object(), which will zero out the object if the
signature doesn't match.

Change-Id: I66b07c36f46ed9112bc39b44914c860ba68677ae
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2017-10-16 16:56:15 +00:00
John E. Kabat Jr d45011c9c6 drivers/elog: Fix debug build errors
Add hexdump.c to Makefile.inc and change an elog_debug format to
use %z for size_t arguments.  This corrects build errors when ELOG_DEBUG
is used.

Change-Id: I3d5547eed8ada7c4bdcbbb8bb9d6965ade73beda
Signed-off-by: John E. Kabat Jr <john.kabat@scarletltd.com>
Reviewed-on: https://review.coreboot.org/21769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-16 16:10:51 +00:00
Lijian Zhao 14cb828f4f intel/cannonlake_rvp: Modify memory parameters to support LP4 board
Replace the support for Cannonlake U DDR4 board to Cannonlake U LPDDR4
platform.

TEST=Able to boot up on CNL U LPDDR RVP.

Change-Id: I2a3dd39875705dcb93a60ceba7c143e3e5328148
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-16 15:23:37 +00:00
Paul Menzel 1d6002a27c cpu/amd: Fix spelling of *implementation*
Change-Id: I3ef810ee59492c8d7147934e61523c8fd223863b
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/22013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-16 02:05:16 +00:00
Nico Huber ceb52711d7 cpu/x86/mtrr: Remove var-MTRR alignment optimization
The code used to split up ranges >64MiB into 64MiB-aligned and
unaligned parts. However in its current state the next step,
calc_var_mtrr_range(), results in the same allocation, no mat-
ter if we split the range up before. So just drop the split-up.

Change-Id: I5481fbf3168cdf789879064077b63bbfcaf122c9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-16 01:34:06 +00:00
Patrick Georgi a41277d1d3 google/reef: Add more special cases for coral nasher
BUG=b:65386429
BRANCH=none
TEST=panel lights up

Change-Id: I9871969314b9b64bee2b20332e35bfc6fbd2ddda
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/22002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-16 01:32:57 +00:00
Richard Spiegel 9305704454 src/mainboard/google/kahlee: Remove legacy tables
Remove IRQ and MP tables. Modern OS use ACPI instead of legacy tables.
Use Kconfig for reversable configuration if using old OS.

BUG=b:62241143

Change-Id: I5fc833c8af47b5f6fad757e129250e6202810dbb
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-16 01:32:28 +00:00
Youness Alaoui b6b1b237eb console/flashconsole: Enable support for postcar
If FSP 2.0 is used, then postcar stage is used and the flashconsole
as well as spi drivers needed to be added.

Change-Id: I46d720a9d1fe18a95c9407d08dae1eb70ae6720e
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/21959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-16 00:21:49 +00:00
Kane Chen 6708d3abc7 mb/google/fizz: enable AER for PCIe root ports
Enable PCIe Advanced Error Reporting for PCIe
root port 2, 3, 4 ,8.

BUG=b:64798078
TEST="lspci" shows that AER is enabled in the capabilities list.

Change-Id: I6438250d674e7d06cdecd8f25fadebca1973721e
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/21946
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-16 00:20:07 +00:00
Shaunak Saha ec1a24ca02 src/soc/skylake: Fix Null pointer dereferences
Fix bug detected by coverity to handle the NULL pointer dereference

Coverity Issues:
* 1379849
* 1379848

TEST=Build and run on skylake platform

Change-Id: Iec7a88a03531bbfeb72cedab5ad93d3a4c23eef5
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/21909
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-16 00:19:44 +00:00
Naresh G Solanki f329f0c3af intel/common: CAR setup CQOS
Enable CQOS on Geminilake.

In Apololake, CBM_LEN is 0x7. Whereas the same in Geminilake is 0xF.

Thus get CBM_LEN using cpuid instruction & generate CBM_LEN_MASK.

Later use the CBM_LEN_MASK when writing to IA32_L2_MASK_* to set right
bits.

BUG=None
TEST= Build for Geminilake platform i.e., glkrvp & check for successful
CAR setup. Even verified the same on APL platform i.e., on Reef

Change-Id: Ic736dba1a46629ff5bf3183082799c0c1468e6d9
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com
Reviewed-on: https://review.coreboot.org/21701
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-16 00:16:53 +00:00
Frank Vibrans 7151778847 soc/amd/common: Clean up file includes
Remove unnecessary header file includes.

Change-Id: I9ad9e86f3c75903e278e898602caec04351f64b6
Signed-off-by: Frank Vibrans <frank.vibrans@scarletltd.com>
Reviewed-on: https://review.coreboot.org/21989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-16 00:13:23 +00:00
Kamil Wcislo c5d3944ad5 mainboard/pcengines/apu2: use GENERIC_SPD_BIN
Use GENERIC_SPD_BIN method of adding the SPD bins to final rom.

Change-Id: I242e393bafac41aa7743f83b52cadf027019ee6e
Signed-off-by: Kamil Wcislo <kamil.wcislo@3mdeb.com>
Reviewed-on: https://review.coreboot.org/21980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-10-16 00:13:03 +00:00
Marshall Dawson a5f225f288 soc/amd/stoneyridge: Check UART index
The Stoney Ridge APU has only two internal UARTs.  Add checks for
invalid settings.  When enabling the UART, return if the console is
on any UART not equal 0 or 1.  The base address returned is 0 if an
invalid configuration is used.  All callers check the return value
before using the returned value.  Finally, provide an assert at the
earliest availability of the console to get the notice into the
cbmem console.

BUG=b:62201567
TEST=Build with UART = -1, 0, 2.  Inspect objdump and boot to OS.
     Build without ST UART and inspect with objdump.

Change-Id: I9432571712bae15a604f4280ea5e0f81fd68604d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-16 00:12:48 +00:00
Marshall Dawson 78130663e5 drivers/uart8250mem: Check for zero base address
Before adding a new UART to the coreboot/lb table, verify that it
has a non-zero base address.  This is consistent with all other
functions that use the uart_platform_base() function.

This was tested on google/kahlee by using an invalid UART number
and forcing the base address to 0.  Execution was able to complete
through depthcharge and into the OS.

Change-Id: I6d8183a461f0fedc254bf88de5ec96629a2a80ef
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21996
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-16 00:12:35 +00:00
Martin Roth 30f9b953a8 soc/amd/stoneyridge: Update AMD firmware placement options
- Don't force the selection of placing the firmware outside of cbfs
when using vboot.
- Set a prompt to allow the option of placing it outside of  cbfs.
- Leave all Kconfig defaults the same.
- Place the AMD firmware directory table in the specified location
even when using the 'outside of cbfs" option.
- Print where the firmware is being placed when placing it outside
of cbfs.

BUG=b:65484600
TEST=Assign PSP firmware location, build & test.  Firmware shows up
inside CBFS.  Set 'outside of cbfs' option, verify firmware gets
written to the correct location.

Change-Id: Ia8258b5c2ecfaaa42d623e3376ec3233115aed58
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21867
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-16 00:11:46 +00:00
Martin Roth fc9d5011a9 src/mainboard/kahlee: Default AMD FW position to 1MB
For Kahlee, the AMD firmware directory should be in the 1MB location
so that it's in the RO cbfs section.

BUG=b:65484600
TEST=Build & boot

Change-Id: I650d8bc0bfa773f5fb5dc11167fe3db3b9550b68
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22003
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-16 00:11:37 +00:00
Paul Menzel 95c4aa5121 arch/x86/gdt: Correct format of multi-line comment
Change-Id: I87148315cdf7e420eac2f3f680251f8e963a9707
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/21956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-10-16 00:10:33 +00:00
Kyösti Mälkki 1d24b96310 amd/inagua: Drop unused Broadcom 5785 support code
Remove sample configuration code for internal
Broadcom GbE device in AMD A55E aka Hudson-E1.

Change-Id: Ib0262805aafc62513d9237019ade473cb1efbf1c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-15 23:44:58 +00:00
Marshall Dawson 813462ec31 amd/stoneyridge: Add function to find PmControl register
Find the PmControl register's I/O address by checking the hardware in
PMx62.  Don't rely on the address being the coreboot default.  PmControl
is the first register in the AcpiPm1CntBlk.

Change-Id: Ibb608dcaa7801af067d6edd86f92c117c2ac08a6
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-15 23:43:27 +00:00
Marshall Dawson f8bf9a7eaa google/kahlee: Add SMI sleep handler
Notify the EC the system is going to sleep.

Change-Id: I025e268a4f806d827348d91effff43a6a339a148
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-15 23:43:21 +00:00
Marshall Dawson 79df1fb090 google/kahlee: Add SMI apmc handler
Forward the apmc call to the chromeec.

Change-Id: Id724c1abf15617ad1ba28f2c0247455b014c1867
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-15 23:43:17 +00:00
Marc Jones 7e710e047f amd/soc/common: Print an error if an AGESA callout isn't supported
Let the developer or user know that a callout isn't supported.

Change-Id: I73a6c6930a6661627ad76e27bbb78be99e237949
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21998
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-15 22:33:37 +00:00
Matt DeVillier f4dc596a38 google/wizpig: add new board as variant of cyan baseboard
Add support for google/wizpig (white label Chromebook) as
a variant of the cyan Braswell baseboard.

- Add board-specific code as the new wizpig variant
- Add new shared SPD file to the baseboard

Sourced from Chromium branch firmware-strago-7287.B,
commit 02dc8db: Banon: 2nd source DDR memory (Micro-MT52L256M32D1PF)

Change-Id: I424d2256eb79ca3ea0a62620954c57c09ae0c0b2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-15 22:23:18 +00:00
Matt DeVillier 94bc265b64 google/ultima: add new board as variant of cyan baseboard
Add support for google/ultima (Lenovo Yoga 11e G3) as
a variant of the cyan Braswell baseboard.

- Add board-specific code as the new ultima variant

Sourced from Chromium branch firmware-ultima-7287.131.B,
commit 3ef9e73: Revert "Revert "soc/intel/braswell: Put SERIRQ in quiet mode""

Change-Id: Ib38b110f50f4d6ae6eda40e787cd3c1c8dd5ece7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2017-10-15 22:23:05 +00:00
Matt DeVillier 81b5bde7e4 google/setzer: add new board as variant of cyan baseboard
Add support for google/setzer (HP Chromebook 11 G5) as
a variant of the cyan Braswell baseboard.

- Add board-specific code as the new setzer variant
- Add new I2C touchscreen device and SPD files to the baseboard
for potential reuse by other variants

Sourced from Chromium branch firmware-strago-7287.B,
commit 02dc8db: Banon: 2nd source DDR memory (Micro-MT52L256M32D1PF)

Change-Id: Ibcebebeb469c4bd6139b8ce83a1ca5ca560c2252
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-15 22:23:01 +00:00
Richard Spiegel aa1838577d soc/amd/stoneyridge/lpc.c: Refactor lpc_enable_childrens_resources
Factor out the code into separate functions.

Create set_lpc_resource that will set the resource for a particular child while
lpc_enable_childrens_resources finds all children and calls set_lpc_resource
for each child found. This creates well defined boundaries for each function.

Change-Id: I265cfac2049733481faf8a6e5b02e34aadae11f5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-15 22:10:02 +00:00
Michał Żygowski 1a81a4d135 pcengines boards: Update board_info files
This updates board info of PC Engines platforms, changes board names
to official manufacturer's names and adds info about ROM. Removing 
"Clone of" option for ALIX platforms makes them independent.

Change-Id: Ie76d65ea84f14b9043a8e5b86678a9da4c187cc9
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/21722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-15 21:37:24 +00:00
Damien Zammit fe5030eceb biostar/a68n_5200: Fix hang with board due to SPI
SPI mode needs to be set early to normal and Quad I/O disabled
on this board for some reason

Change-Id: I4dbc52010eebf492087d0b1c155a24a307bcc8b0
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/21945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-10-14 08:02:16 +00:00
Damien Zammit b93fb1ab16 biostar/a68n_5200: Do actual port
TESTED on Biostar A68N-5200: boots to GNU/Linux

With proprietary VBIOS, even the gfx works in SeaBIOS.

Change-Id: Id44b81345ba189f82413042760d570a746294a1e
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/21872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-10-14 08:01:51 +00:00
Damien Zammit d2b5b734e8 biostar/a68n_5200: Clone amd/olivehill
Altered Kconfig board names to make it pass lint

Change-Id: I9ccfe014a0e3a70148463fc9f8de02b500fac69e
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/21871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-10-14 08:00:34 +00:00
Youness Alaoui 66030fa5ab intel/skylake: Use Sata related registers from devicetree
Enable the use of the SataPortsEnable and SataPortsDevSlp registers
which were being ignored from the devicetree and were not affecting
the resulting UPD parameters.

SataPortsEnable was only being copied for the first SATA port, while
the other ports were left ignored.

Change-Id: Iae70a4d6375fa5d1b05ee89f6b97c65dbbf28dda
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/21958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-10-14 00:25:08 +00:00
Marc Jones 43a285f983 google/kahlee: Add AGESA_DO_RESET in bootblock
Support the required AGESA_DO_RESET in bootblock.

BUG=b:64719937
BRANCH=none
TEST=Check AGESA reset request in booblock does a reset in the serial
console or ec console.

Change-Id: I462a1f81b8d209c15417946a314f2bfb9b226e4d
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-13 16:48:49 +00:00
Marc Jones 4f886cc19a amd/stoneyridge: Make all AGESA reset requests immediate
The AGESA RESET_WHENEVER request were never doing a reset in coreboot.
We don't have a way to collect a whenever and reset at some later time,
so just do the reset immediately.

BUG=b:64719937
BRANCH=none
TEST=Check AGESA reset request in booblock does a reset in the serial
console or ec console.

Change-Id: If2654ec0c5c5dbdcea6fc9374371c3388d29fdc7
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21978
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-13 16:48:33 +00:00
Shelley Chen 3918887c18 google/fizz: Enable cr50 over SPI
We are changing the bootstraps in the EVTs so that the SOC
communicates with cr50 over SPI instead of cr50.  SPI is more reliable
than I2C.  Thus, disabling cr50 over I2C and enabling cr50 over SPI.

BUG=b:65056998, b:62456589
BRANCH=None
TEST=make sure that we can boot into kernel
     run cold_reset and warm_reset and make sure both
     boot successfully.
CQ-DEPEND=CL:714237

Change-Id: I85b9a61f0305e3c7ccada79d7702234a285a6d2a
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/21970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-10-13 16:29:20 +00:00
Aamir Bohra 2188f57a80 src/device: Update LTR configuration scheme
This patch moves out LTR programming under L1 substate
to pchexp_tune_device function, as substate programming
and LTR programming are independent.

LTR programming scheme is updated to scan through entire
tree and enable LTR mechanism on pci device if LTR mechanism
is supported by device.

BRANCH=none
BUG=b:66722364
TEST=Verify LTR is configured for end point devices and max
snoop latency gets configured.

Change-Id: I6be99c3b590c1457adf88bc1b40f128fcade3fbe
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/21868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-13 15:21:48 +00:00
Matt DeVillier c8374e3292 google/relm: add new board as variant of cyan baseboard
Add support for google/relm (white label Chromebook) as
a variant of the cyan Braswell baseboard.

- Add board-specific code as the new relm variant
- Add new shared SPD files to baseboard

Sourced from Chromium branch firmware-strago-7287.B,
commit 02dc8db: Banon: 2nd source DDR memory (Micro-MT52L256M32D1PF)

Change-Id: Ife10f5f75435f356cd896588dd6f425e54f3c88e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2017-10-13 15:19:55 +00:00
Matt DeVillier 35213664cf google/kefka: add new board as variant of cyan baseboard
Add support for google/kefka (Dell Chromebook 11 3180) as
a variant of the cyan Braswell baseboard.

- Add board-specific code as the new kefka variant
- Add new shared SPD file to baseboard

Sourced from Chromium branch firmware-strago-7287.B,
commit ef41a46: Kefka: Modify USB2 settings to match the eye diagram

Change-Id: Ic6c8c5e5b6029bb99039c64b0182214e93552fa2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-13 15:19:44 +00:00
Matt DeVillier d6735b0f14 google/cyan variants: fix non-functional typo in gpio.c
Typo found/fixed in to-be-merged boards; applying same fix to
already-merged boards.

Change-Id: I15f97467a5442888165399be997b0b690a3c312a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-13 14:30:27 +00:00
Matt DeVillier a34cf52469 google/cyan variants: fix single/dual channel reporting
Fix typos in determining single/dual channel in cyan variants
which resulted in all boards being reported as 4GB/dual channel
in the cbmem console log.
These typos were found and fixed in yet-to-be-merged variants;
this patch applies the same fixes to already-merged boards.

Change-Id: I615463668e77bd817d5270f0f04d4d01f74e3b47
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-13 14:30:21 +00:00
Patrick Rudolph f6aa7d94c8 nb/intel/*/gma: Port ACPI opregion to older platforms
Port the ACPI opregion implementation that resides in
drivers/intel/gma to older platforms.

It allows to include a vbt.bin and allows GNU/Linux to load the
opregion as ASLS is being set.

Windows' Intel will likely ignore it as it relies on legacy VBIOS
to be loaded at 0xc0000.

Tested successfully on DG43GT (x4x) with vbt.bin,
with X200 (gm45) with vendor option rom and
D945GCLF (i945) with fake vbt.

Change-Id: I1896411155592b343e48cbd116e2f70fb0dbfafa
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-13 05:19:03 +00:00
Matt DeVillier 53e4195625 drv/intel/gma/opregion: Add common init_idg_opregion()
Add a new common method to initialize ACPI OpRegion.
* Try to locate vbt.bin in CBFS.
* Try to locate VBIOS in CBFS.
* Keep existing code to probe at 0xc0000.

Tested on Lenovo T430 (sandybridge) using vbt.bin, tested using buggy
VBIOS with wrong vbt_offset, tested with fake vbt written by NGI at
0xc0000.

Tested with https://review.coreboot.org/#/c/21766/ on i945 (using fake
vbt at 0xc0000), x4x (using vbt.bin) and gm45 (using vendor VBIOS).
In all cases linux was successfully provided with VBT from ACPI
opregion.

Change-Id: I8ee50ea9900537bd9e3ca5ab0cd3f48d2acec970
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-13 05:17:45 +00:00
Furquan Shaikh 74145f7615 intel/common/pmc: Disable all GPEs during pmc_init
If GPEs are not cleared during pmc_init, it could result in issues if
standard wake events are generated while coreboot is
initializing. e.g. (Observed on soraka):
1. Suspend to S3
2. Lidclose
3. Lidopen
4. EC wakes up the host using WAKE# pin
5. On wakeup, pmc_init occurs which does not clear GPEs
6. MP init enables SMI
7. In order to add wake event to elog, coreboot sets wake mask on the
EC, which causes the EC to assert WAKE#.
8. Since WAKE# is asserted, it results in an SMI#. However, EC does
not de-assert WAKE# until host queries and clears the host event
bit (which does not happen since coreboot is stuck in handling the
SMIs).

This is one of the issues that can occur when GPEs are unnecessarily
enabled in coreboot. Before the move to PMC common library, SKL PMC
driver set all GPEs to 0 and hence this issue did not occur.

This change explicitly disables all GPEs during pmc init in order to
avoid any side-effects.

BUG=b:67712608
TEST=Verified that device resumes fine using lidclose/lidopen to
suspend and resume.

Change-Id: Ic5be02a23a8dbf43c4d7adf00251639ded4a94c9
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21969
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-12 22:13:42 +00:00
Furquan Shaikh c4e652ff57 soc/intel/common: Clean up PMC library GPE handling API
1. Update gpe handling function names to explicitly mention if they
are operating on:
 a. STD GPE events
 b. GPIO GPE events
 c. Both
2. Update comment block in pmclib.h to use generic names for STD and
GPIO GPE registers instead of using any one platform specific names.

BUG=b:67712608

Change-Id: I03349fe85ac31d4215418b884afd8c4b531e68d3
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21968
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-12 22:13:39 +00:00
Martin Roth bbd5ee4187 vboot: Exclude platform specific files from RW cbfs
Add a Kconfig option to allow platforms to exclude specific files
from being copied from RO into RW sections.

BUG=b:65484600
TEST=Exclude apu/amdfw from the RW cbfs sections

Change-Id: I7723b63392c1620b75ceb6d8e25fe1ce2c75cf18
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-12 18:33:42 +00:00
Bora Guvendik 630b644cec soc/intel/cannonlake: add length information for communities
TEST = Boot to OS, check if pinctrl probed successfully

Change-Id: Ib20c955d535cd9c48175b4d3934b4699b6186874
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/21974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-10-12 18:26:52 +00:00
Vaibhav Shankar b4e275f97b mainboard/intel/cannonlake_rvp: Add Sleep states
Add sleep state to DSDT table.

Change-Id: Ic14e34e29d5f881949765dee5c6b433c1499c491
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/21976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-10-12 18:26:38 +00:00
Vaibhav Shankar 4df1c4cedb soc/intel/cannonlake: Add ACPI platform sleep capability
Add the required ACPI sleep states

Change-Id: I7750062554f087e4f88da56790e4122d5fa20529
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/21975
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-10-12 18:26:33 +00:00
Richard Spiegel 63300f7292 soc/amd/stoneyridge: Clean up sata.c
Clean up ahci_ptr declaration. Remove incorrect PCI device IDs.

BUG=b:62200375

Change-Id: I9058d9102fc8ea0bd03ea089ba98da4590dd3533
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21973
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-12 16:33:20 +00:00
Werner Zeh c0d1e31617 siemens/mc_bdx1: Add delay to wait for legacy devices
Like happend in commit efd0eb35af
(siemens/mc_apl1: Add delay to wait for legacy devices) add the
feature to mc_bdx1 as it uses the same legacy devices.

Change-Id: I355a53ce7aea70098d7bc08f24dc6a4e43d1d618
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/21933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2017-10-12 16:20:56 +00:00
Werner Zeh 0ccc3c49e4 intel/fsp_broadwell_de: Add timestamp functionality
Add a little code to enable timestamps on FSP based implementation
of Broadwell-DE. I have tested it by reading back the timestamps
with cbmem utility once the board has booted into Lubuntu.

Change-Id: Idaa65a22a00382bf0c37acf2f5a1e07c6b1b42d9
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/21932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-12 16:20:50 +00:00
Arthur Heymans 0315b6740a sb/amd/sb700/lpc.c: Optimize code flow for less indentation
This changes the code flow so less indentation has to be used.

This also changes some lines to limit their length.

Change-Id: I50ca99a759a276e9d49327c6ae6c69eeab2a8c90
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21234
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-12 08:08:22 +00:00
Arthur Heymans 6af8aab539 nb/intel/sandybridge/raminit: Fix setting scramble seed for CH1
The scramble seed intended for CH1 were written to the regs of CH0.

Write the scramble seed for CH1 at the correct offset.

TESTED on Lenovo T430, HP 2760P, Asrock B75PRO3-M.

Change-Id: I3778947e96b3298c38e6d5b74988e617e1ffea7b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Iru Cai <mytbk920423@gmail.com>
2017-10-12 08:07:18 +00:00
Kane Chen f73bc0b2d1 soc/intel/skylake: Enable bus master for sata
The bus master needs to be enabled so that
the busy bit in AHCI PORT_TFDATA will be cleared
by controller when depthcharge tries to wait
for sata to complete spin-up during AHCI init.

Otherwise, the timeout will happen and cause
5 seconds delay in depthcharge.

BUG=b:37639063
BRANCH=none
TEST=verify that the sata timeout is gone in
     depthcharge

Change-Id: I19eadbb2943fda8a5babc82ca87b1ecaab5e2ed8
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/21890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-10-12 02:45:41 +00:00
Martin Roth 6754e4ea20 mainboard/google/kahlee: Add EC_IN_RW flag
Depthcharge was complaining that the GPIO for this flag wasn't set.
The GPIO also needs to be an input, not an output.

BUG=b:67614692
TEST=Depthcharge no longer complains that there is no GPIO set for flag5.
The system boots again.

Change-Id: Ib854e97b0a3aa42a95ceb8a42a9776f0345ff8b1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-11 17:53:09 +00:00
Lijian Zhao 0c8237aa0d soc/intel/cannonlake: Change default UART number to 2
Set default UART number to 2 if 32bit PCI got selected, the proper debug
print can be seen from serial port in case of switch between platforms,
especially when change to lpss uart from legacy uart or vise versa.

Change-Id: If2e0e8c8ac86e49a245f3d1d4722d40be9c01e25
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21544
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-11 17:26:07 +00:00
Gaggery Tsai bc37c67837 mainboard/google/fizz: Enable Devslp for SATA port 1
This patch is to enable the support of device sleep
for SATA port 1 and disable unused SATA port 0.

BUG=b:65808359
BRANCH=None
TEST=Ran "suspend_stress_test -c 2500" and passed the test.

Change-Id: I33b8f5fd0c51d83e154ef7daac3274ff377bc8b3
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/21765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Shelley Chen <shchen@google.com>
2017-10-11 16:09:06 +00:00
Patrick Georgi bf375e3943 vboot: use cbfstool truncate
Instead of a shell based parser for cbfstool print -k output.

BUG=b:65853903
BRANCH=none
TEST=`abuild -x -t GOOGLE_KEVIN -p none` creates a valid-looking image.

Change-Id: I33b7e1c483a69e66e82541c09582be2a71356a10
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-10-10 15:16:25 +00:00
Furquan Shaikh d6c0af6c54 soc/intel/skylake: Fix broken suspend/resume for deep S3
Change d3476809 (soc/intel/skylake: Add support in SKL for PMC common
code) changed the logic for obtaining previous sleep state by
unconditionally checking for PWR_FLR and SUS_PWR_FLR. In case of deep
S3, SUS_PWR_FLR is set in gen_pmcon_b (just like resume from deep
S5/G3) and hence the check for power failure should be done only when
WAK_STS bit is not set. This is necessary to differentiate wakes from
deep S3 and G3.

This change restores the original logic by performing power failure
check only in cases where WAK_STS bit is not set.

BUG=b:67617726
TEST=Verified following:
1. When WAK_STS bit is not set and SUS_PWR_FLR is set, coreboot
correctly identifies that the system prev sleep state was S5.
2. When WAK_STS bit is set and SUS_PWR_FLR is set, coreboot correctly
identifies that the system prev sleep state was S3.

Change-Id: Ic97bbc9911ba34aa21f4728c77fc20c5bb08f6f9
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-10 14:43:54 +00:00
Chris Wang 5547c371c1 mb/google/poppy/variants/nautilus: add nautilus board
Create Nautilus board which derives from Poppy, a KBL reference board.

BRANCH=master
BUG=b:66462881
TEST=Build (as initial setup)

Change-Id: I6ca5ab821a7ba1746b37dfd3ea1ed367094d4f52
Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/21895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-10-10 13:48:14 +00:00
Paul Menzel 8ce7bc18fa ec/lenovo/h8: Serialize control method _CRS
```
dsdt.aml   1461:  Method (_CRS, 0)
Remark   2120 -             ^ Control Method should be made Serialized (due to creation of named objects within)
```

Change-Id: Iaf9455b16b061b32248139a85890f49de7467261
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/21921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-10-10 11:35:31 +00:00
Furquan Shaikh 219ebb969b skylake mainboards: Use PAD_CFG_GPI_GPIO_DRIVER instead of PAD_CFG_GPI
Change 1760cd3e (soc/intel/skylake: Use common/block/gpio) updated all
skylake boards to use common gpio driver. Common gpio code
defines PAD_CFG_GPI without GPIO_DRIVER ownership. However, for
skylake PAD_CFG_GPI set GPIO_DRIVER ownership by default. This
resulted in Linux kernel failing to configure all GPIO IRQs since the
ownership was not set correctly. (Observed error in dmesg: "genirq:
Setting trigger mode 3 for irq 201
failed (intel_gpio_irq_type+0x0/0x110)")

This change fixes the above issue by replacing all uses of PAD_CFG_GPI
in skylake mainboards to PAD_CFG_GPI_GPIO_DRIVER.

BUG=b:67507004
TEST=Verified on soraka that the genirq error is no longer observed in
dmesg. Also, cat /proc/interrupts has the interrupts configured
correctly.

Change-Id: I7dab302f372e56864432100a56462b92d43060ee
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-09 20:20:40 +00:00
Bora Guvendik e9d8959c4f mainboard/intel/cannonlake_rvp: enable NVMe SSD
Turn on PCIe express port 9 of PCIe controller 3,
to enable NVMe SSD via M.2 socket 3 on RVP board.

TEST=Boot to OS using Intel NVMe SSD Pro 6

Change-Id: I2fd1cdcf2d9718bf2042262b0c9813811a706b4a
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/21908
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-09 18:44:11 +00:00
Patrick Georgi 22579596ff soc/intel/*lake: Load vbt when it's needed
That removes the need for another global variable.

Change-Id: I25e12ba724836de4c8afb25cd347cafe6df8cea9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21907
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-09 07:10:54 +00:00
Matt DeVillier f2fc497228 google/cyan: fix variant memory/silicon init params override
The mainboard_memory_init_params() and mainboard_silicon_init_params()
methods already have weak definitions in drivers/intel/fsp1_1,
so having them declared as weak in the cyan baseboard has the effect
of them not being called at all unless overridden at the variant level.

Therefore, remove the weak declarations in the baseboard and ensure
that each variant has its own init functions if needed.

TEST: build/boot google/cyan

Change-Id: I1c76cb5838ef1e65e72c7341d951f9baf2ddd41b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-10-08 22:34:47 +00:00
Furquan Shaikh ef1a5ede6c mb/google/poppy/variants/soraka: Add 10ms reset delay for WCOM device
Change 868b3761 (mainboard/google/soraka: Reduce Wacom resume time)
removed the delay after taking device out of reset since it seemed
unnecessary in system resume case (because there is enough time after
taking device out of reset and before communication with device
starts).

However, without the delay, kernel driver runs into issue while
talking to the device during boot-up and runtime
suspend/resume. (Observed this error in dmesg: "i2c_hid
i2c-WCOMCOHO:00: failed to change power setting."). Thus, add 10ms
delay after taking device out of reset. Verified on multiple Soraka
system that with 10ms delay, kernel driver does not run into any issue
talking to the WCOM device during boot-up, runtime suspend/resume and
system suspend/resume.

BUG=b:65358919
TEST=No more errors talking to WCOM device in kernel dmesg.

Change-Id: I485b753cbae4b653e74337e048aea4d26ffdbb81
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21910
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Rajat Jain <rajatja@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-08 19:38:51 +00:00
Furquan Shaikh 2749c52080 ec/google/chromeec: Add library function google_chromeec_events_init
mainboard_ec_init implemented by all x86-based mainboards using
chromeec performed similar tasks for initializing and recording ec
events. Instead of duplicating this code across multiple boards,
provide a library function google_chromeec_events_init that can be
called by mainboard with appropriate inputs to perform the required
actions.

This change also adds a new structure google_chromeec_event_info to
allow mainboards to provide information required by the library
function to handle different event masks.

Also, google_chromeec_log_device_events and google_chromeec_log_events
no longer need to be exported.

Change-Id: I1cbc24e3e1a31aed35d8527f90ed16ed15ccaa86
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-10-08 19:38:28 +00:00
Nick Vaccaro 687b023d97 google/zoombini: adapt to schematic changes
Adapt code to latest schematic changes, revision 1.1.

Configure GPD2 for EC_PCH_WAKE_ODL,
        GPP_D5 for EC_I2C_SENSOR_SDA,
        GPP_D6 for EC_I2C_SENSOR_SCL,
        GPP_D7 for WWAN_SAR_INT_ODL,
        GPP_D9 for touchscreen power enable,
        GPP_D10 for wifi power enable,
        GPP_D11 for wwan power enable,
        GPP_D13 change to "No Connect" (was VOL_UP_ODL),
        GPP_D14 change to "No Connect" (was VOL_DOWN_ODL).

BUG=b:66265441
BRANCH=None
TEST=None

Change-Id: Ic9e76ed3e958c1f96deb6356d6480c6ba7cfe699
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/21900
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-06 18:11:24 +00:00
Patrick Georgi c6a0050198 soc/intel/skylake: use locate_vbt directly instead of calling a wrapper
Change-Id: I65c423660ab1778f5dd9243e428a4d005bd1699a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-06 17:07:23 +00:00
Patrick Georgi 9d3de2649f soc/intel/common: refactor locate_vbt and vbt_get
Instead of having all callers provide a region_device just for the
purpose of reading vbt.bin, let locate_vbt handle its entire life cycle,
simplifying the VBT access API.

Change-Id: Ib85e55164e217050b67674d020d17b2edf5ad14d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21897
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-06 16:59:31 +00:00
Patrick Georgi cba7316c26 soc/intel/common: refactor locate_vbt
All callers of locate_vbt just care about the file content and
immediately map the rdev for its content.
Instead of repeating this in all call sites, move that code to
locate_vbt.

Change-Id: I5b518e6c959437bd8f393269db7955358a786719
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-06 16:59:20 +00:00
Patrick Georgi c1ef5c1752 mainboard/google/reef: Override VBT selection in coral
Change-Id: I7fd667b1cf0b7c2a5e4ab7ac7748d9636a52ae54
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21725
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-06 15:53:03 +00:00
Patrick Georgi f614277099 soc/intel/common: Allow overriding CBFS filename of VBT
When reusing the same image across multiple devices, they sometimes need
different VBTs, so provide a hook for mainboard code to specify which
file is required.

Change-Id: Ic7865dc0e0c9ea3077b749d9d0482079877e9c4f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21724
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-06 15:52:59 +00:00
Lijian Zhao a06f55b8e4 soc/intel/cannonlake: Enable MRC cache
Enable MRC cache by default.

TEST=Warm reset and check coreboot serial log, MRC related log can be
seen.

Change-Id: I76ece361867737c01cc848c24d8893d43a3d292e
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-06 15:25:45 +00:00
Aaron Durbin 4a8f45f9ad soc/intel/cannonlake: reduce bootblock size
Reduce the bootblock size to 16KiB from the default 64KiB.
Not all that space is necessary.

Change-Id: I5c15d0af0f85282b84c8983f0a015aeb45c00a07
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-10-06 15:25:35 +00:00
Aaron Durbin d61f723590 soc/intel/common: remove invalid path from Kconfig include
The src/soc/intel/common/basecode/Kconfig path does not exist.
Remove the inclusion of the invalid path.

Change-Id: Icbd8f310cad4246b72bc869bcf4a089ae2f0c5a3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-10-06 15:25:32 +00:00
Kyösti Mälkki 2b9f5b5c12 AGESA f16kb: Enable MRC cache equivalent fastboot
Try restoring previous memory training results from SPI flash
to improve raminit speed.

Change-Id: I6f4c2342e2eea6c1ecfb71da8564225b6230f51e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-06 05:35:35 +00:00
Patrick Georgi 8269096bd9 drivers/intel/fsp2_0: use common code to fetch vbt.bin
No need for having two of everything in the coreboot codebase.

Change-Id: Ie1cdd1783dd5dababd1e97436a4ce1a4f068d5b3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-05 21:19:47 +00:00
Lijian Zhao ae565463b6 soc/intel/cannonlake: Add all the SOC level DSDT tables
Add all the SOC level DSDT tables, reference from skylake/kabylake. 

Change-Id: Ia72bbe87b32d37db01f8768bd8447cb6ee1567a9
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-05 21:16:46 +00:00
Shaunak Saha d347680995 soc/intel/skylake: Add support in SKL for PMC common code
Change-Id: I3742f9c22d990edd918713155ae0bb1853663b6f
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/20499
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-05 21:11:39 +00:00
Shaunak Saha f073872e22 soc/intel/common/block: Manage power state variable from common PMC block
This patch helps managing power state variables from within the
library. Adds migrate_power_state which migrates the chipset
power state variable, reads global power variable and adds it
in cbmem for future use. This also adds get_soc_power_state_values
function which returns the power state variable from cbmem or
global power state variable if cbmem is not populated yet.

Change-Id: If65341c1492e3a35a1a927100e0d893f923b9e68
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/21851
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-05 21:11:27 +00:00
Martin Roth a75d6808ca soc/amd/stoneyridge: Pass firmware dir location to amdfwtool
The amdfwtool now outputs firmware that is correctly built for the
new location.

BUG=b:65484600
TEST=Assign PSP firmware location, build & test.

Change-Id: Ifa2e99ea031fc0d9f165ae44ff6b1afef369eb28
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-05 18:17:36 +00:00
Jonathan Neuschäfer d61c670705 src/mainboard/Kconfig: Add support for 10240 KiB ROM chips
The Dell Optiplex 790 desktop board has a logical 10MiB flash, so it
needs to select BOARD_ROMSIZE_KB_10240. Provide it, so it can be used.

Change-Id: I6365b0cda67fa1213c20337890157e5d658094d1
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-05 17:53:16 +00:00
Rizwan Qureshi 7f72c64195 soc/intel/{common,apollolake}: Add checks to handle negative values
Fix issues reported by coverity scan in the below files.

src/soc/intel/common/block/i2c
	1375440: Improper use of negative value
	1375441: Improper use of negative value
	1375444: Improper use of negative value

src/soc/intel/apollolake/i2c.c
	1375442: Unsigned compared against 0

Change-Id: Ic65400c934631e3dcd3aa664c24cb451616e7f4d
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/21875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-05 17:47:02 +00:00
Rizwan Qureshi b3e18c7a43 soc/intel/skylake: Add config for mbx command for Intersil VR C-state issues
Config for activating VR mailbox command for Intersil VR C-state issues.
0 - no mailbox command sent.
1 - VR mailbox command sent for IA/GT rails only.
2 - VR mailbox command sent for IA/GT/SA rails.

BUG=b:65499724
BRANCH=none
TEST= build and boot soraka.

Change-Id: Ibcced31b7ba473ffa7368c90c945d07a81a368d4
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/21680
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-05 17:46:15 +00:00
Balaji Manigandan B bd55c02a23 vendor/intel/skykabylake: Update FSP header files to version 2.7.2
Update FSP header files to version 2.7.2.

New UPDs added
	FspmUpd.h:
	 *CleanMemory

	FspsUpd.h:
	 *IslVrCmd
	 *ThreeStrikeCounterDisable

Structure member names used to specify memory configuration
to MRC have been updated, SoC side romstage code is updated
to handle this change.

CQ-DEPEND=CL:*460573,CL:*460612,CL:*460592
BUG=b:65499724
BRANCH=None
TEST= Build and boot soraka, basic sanity check and suspend resume checks.

Change-Id: Ia4eca011bc9a3b1a50e49d6d86a09d05a0cbf151
Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/21679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-10-05 17:45:46 +00:00
Patrick Georgi 53b8a82e72 mb/google/reef: Cache EC's SKU ID on Coral
Change-Id: I1925f51d63290b8d08366b622d5df3aab3a7484e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21737
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-10-05 16:35:50 +00:00
Kyösti Mälkki 0e1ea279d0 AGESA vendorcode: Add ENABLE_MRC_CACHE option
When selected, try to store and restore memory training
results from/to SPI flash. This change only pulls in
the required parts from vendorcode for the build.

Change-Id: I12880237be494c71e1d4836abd2d4b714ba87762
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-05 13:23:27 +00:00
Kyösti Mälkki 6287a69530 AGESA: Re-enable HAVE_ACPI_RESUME
Note: For some of the boards affected ACPI S3 support
was never tested but feature was just copy-paste from
reference design.

Change-Id: I2a54d605fa267a7501f57efd79a16b3bfa49891e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Damien Zammit <damien@zamaudio.com>
2017-10-05 13:23:14 +00:00
Daisuke Nojiri b0b4fd45e5 google/fizz: Configure GPP_C23 early
GPP_C23 is read by vboot_handoff to set the WP flag. Thus, it has
to be configured in early_gpio_table.

BUG=b:67030973
BRANCH=none
TEST=Verify by wpsw_boot and wpsw_cur match.

Change-Id: I96f2b53d7bc0901ffccce46b2d8ddae80c002fdc
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/21876
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-04 23:13:44 +00:00