Commit Graph

41257 Commits

Author SHA1 Message Date
Subrata Banik 7d85d43f18 mb/google/brya: Update ddr config
Fixed ddr config to override the FSP default value.

BUG=b:182772421
TEST=Built image and passed memory training.

Without this change:
RcompTarget on Lpddr4x = { 40, 40, 30, 30, 30 }

With this change:
RcompTarget on Lpddr4x = { 40, 30, 30, 30, 30 }

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Ib07ff36496828b5de78ed928b294a400ad08865f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-26 04:53:36 +00:00
Subrata Banik efe858b170 soc/intel/alderlake: Add provision to override Rcomp settings
Add function to allow overriding the RcompResistor and
RcompTarget UPDs from mainboard if required.

Mainboard users can pass required rcomp from memory.c file.

Refactor ddr_config structure to take out rcomp related variable
outside for all memory type to override if required.

BUG=b:182772421
TEST=Able to override the default RcompResistor and RcompTarget
values.

Change-Id: Ie8528bbf0517728534d47f9adaabfc9a2c469609
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-26 04:53:18 +00:00
Subrata Banik c8ac8f5ce9 soc/intel/alderlake: Align RcompResistor definition as per MRC
List of changes:
1. Alder Lake MRC is expecting a RcompResistor value of word width.
Reference RCOMP resistors on motherboard are ~ 100 Ohms but coreboot
is passing an array of RcompResistor which is not completely in use.

Note: Rcomp resistor value represents rcomp resistor attached to
the DDR_COMP pins on the SoC.

2. Also, remove usage of '&' with memcpy the required value into
RcompTarget array.

3. Also, update RcompResistor value for ADLRVP.

BUG=b:183341229
TEST=Enable FSP debug log to verify the override value for
RcompResistor is reflecting correctly.

Change-Id: I69c7cec55b65036fc039c33374a3fd363ef7004e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-26 04:52:57 +00:00
Zheng Bao 74406e1053 mb/amd/majolica: Enable IO port 2E/2F
MEC1701 can be accessed by IO port 2E/2F

Change-Id: I31f1b147476ec487e64f3c30b3cf514b45ced416
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-25 19:24:34 +00:00
Julian Schroeder e286ef9f41 mb/google/zork/variants/baseboard: USB2 HS phy settings
Set default USB2 HS disconnect threshold to maximum to avoid false
disconnects that eventually lock up the xHCI controller

BUG=b:174538960

TEST=suspend_stress_test -c 50 on vilboz and morphius.
     Sample set of USB2 HS devices connect and disconnect
     successfully

Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: Ic921d850a0bdd717a2a7e50e9e6f65e39e0607bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51265
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-25 19:16:28 +00:00
Felix Held a16a09f869 soc/amd/common/block/i2c: fix control flow bug
commit 4f87ae1d4a introduced a regression
in the I2C initialization resulting in soc_i2c_misc_init never getting
called, since the continue statement was indented like it belonged to
the if above, but due to the missing curly braces it was outside the if
block.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Found-by: Coverity CID 1451395, 1451387
Change-Id: Id1f17ad59cba44e96881f5511df303ae90841ab3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51786
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-25 16:23:23 +00:00
Joe Tessler 549abfb5ab mb/google/hatch/var/genesis: Fix PCIe root ports
The previous "PCIe port" numbering was incorrect and resulted in several
PCIe devices failing to enumerate. With lane reversal, these numbers are
all backwards. This explains the confusing mapping of Clock Source #1 to
Root Port #9 in https://review.coreboot.org/c/coreboot/+/50101. We were
confusing "Root Port" vs "PCIe Lane".

This change addresses the port vs. lane confusion in the device tree
configurations. It also adds more detailed documentation to a future
reader (i.e., me) to avoid this blunder.

BUG=b:181633452,b:181635072,b:177752570
TEST=build AP firmware; flash device
BRANCH=none

Change-Id: I47edf0b0af1bdcf86b89f17ad2a1f128ef9e9f7a
Signed-off-by: Joe Tessler <jrt@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-25 08:36:29 +00:00
Joe Tessler b15a15aabe mb/google/hatch/var/genesis: Add missing GPIOs
After revisiting the genesis GPIO table and schematics for EVT closure,
I discovered several missing and/or incorrectly documented GPIO pin
mappings.

Now the GPIO pin names and functions should match what's written in the
latest schematics.

BUG=b:181633452,b:181635072,b:177752570
TEST=build AP firmware; flash device
BRANCH=none

Change-Id: I73e6733bce761b00717091834c7a49e85154f80b
Signed-off-by: Joe Tessler <jrt@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51677
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-25 08:36:22 +00:00
Angel Pons f5ec52a522 nb/intel/haswell: Move USB config API into Lynx Point
Both EHCI and xHCI USB controllers are inside the PCH (southbridge).
Now that mainboard USB configuration no longer depends on pei_data.h
definitions, the API declarations can be placed in southbridge code.

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: Ia21991b225482b33c5bc0dc52884674d301b28ba
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-25 07:51:50 +00:00
Angel Pons d0f971fe9a nb/intel/haswell: Decouple mainboard USB config from MRC
With this change, only raminit.c uses pei_data.h definitions. With MRC
cornered, making it optional is just a matter of writing a replacement.
USB config definitions will be moved to Lynx Point code in a follow-up.

Tested on Asrock B85M Pro4, still boots and still resumes from S3.

Change-Id: I4bc405213e9b0828d9ced18677335533c7dd381d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-25 07:51:38 +00:00
FrankChu 6902263dca mb/google/volteer: Collis: Update SPD table
Add memory table to "mem_list_variant.txt", and command to generate files:
go run ./util/spd_tools/lp4x/gen_part_id.go src/soc/intel/tigerlake/spd src/mainboard/google/volteer/variants/collis/memory/ src/mainboard/google/volteer/variants/collis/memory/mem_list_variant.txt

DRAM Part Name                 ID to assign
MT53D512M64D4NW-046 WT:F       0 (0000)
H9HCNNNCRMBLPR-NEE             0 (0000)
MT53D1G64D4NW-046 WT:A         1 (0001)
H9HCNNNFBMBLPR-NEE             2 (0010)

BUG=b:182227204
TEST=emerge-volteer coreboot

Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I773c65c0b6d5e868572530305ab8a61a0dd1532d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-03-25 07:50:17 +00:00
Dtrain Hsu 2bb7896c36 mb/google/dedede/var/cret: Enable touchscreen
Add ELAN and Weida touchscreen into devicetree for cret.

BUG=b:180547621
BRANCH=dedede
TEST=Build the cret board.

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Icdb7aabe4a9ecd7b5a057c4644799aa537adb6ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-25 07:50:03 +00:00
Dtrain Hsu d5dde22758 mb/google/dedede/var/cret: Configure I2C ports and touchpad
1. Support Elan touchpad.
2. Support JYT touchpad.
3. Follow schematic to disable I2C1 and I2C3.

BUG=b:183454249, b:180547781
BRANCH=dedede
TEST=Build the cret board.

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I8c150c3f65d0e057d5ba1b07ec1c20886f02ef6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51726
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-25 07:49:49 +00:00
Dtrain Hsu aacfa24457 mb/google/dedede/var/cret: Generate SPD ID for supported parts
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
1. H9HCNNNBKMMLXR-NEE
2. MT53E512M32D2NP-046 WT:F
3. K4U6E3S4AA-MGCR

BUG=b:183057749
BRANCH=dedede
TEST=Build the cret board.

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Iacfdd9a27f126ba4b97d1a6493bcc09bb31454a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51619
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-25 07:49:36 +00:00
Dtrain Hsu 57c013eb11 mb/google/dedede/var/cret: Configure USB port settings
Follow schematic to modify USB port settings.

USB2 [0]: USB Type C Port 0
USB2 [1]: None
USB2 [2]: USB Type A Port 0
USB2 [3]: LTE
USB2 [4]: None
USB2 [5]: Camera UFC
USB2 [6]: Camera WFC
USB2 [7]: Integrated Bluetooth

USB3 [0]: USB Type C Port 0 (M/B side)
USB3 [1]: None
USB3 [2]: USB Type A Port 0 (M/B side)
USB3 [3]: LTE

BUG=b:182973703
BRANCH=dedede
TEST=Build the coreboot image.

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I80447d6ac3422f858a9022f550b4f42353819405
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-25 07:49:26 +00:00
Dtrain Hsu 4119391a8e mb/google/dedede/var/cret: Configure GPIO
Follow schematic to modify some GPIO pins.

GPP_C12 - NC Pin, UP_20K
GPP_C18 - NC Pin
GPP_C19 - NC Pin
GPP_C22 - NC Pin, UP_20K
GPP_D12 - NC Pin
GPP_D14 - NC Pin
GPP_D15 - NC Pin
GPP_D19 - NC Pin
GPP_D20 - NC Pin
GPP_E0  - NC Pin
GPP_E2  - NC Pin
GPP_H1  - NC Pin
GPP_H6  - NC Pin
GPP_H7  - NC Pin
GPP_G0  - NC Pin
GPP_G1  - NC Pin
GPP_G2  - NC Pin
GPP_G3  - NC Pin
GPP_G4  - NC Pin
GPP_G5  - NC Pin, UP_20K
GPP_G6  - NC Pin
GPP_G7  - NC Pin

BUG=b:183078393
BRANCH=dedede
TEST=Build the cret board.

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Id966884f3e36303b636fa13ef9baecccae87604a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-25 07:49:17 +00:00
Karthikeyan Ramasubramanian e3f816c7bb soc/amd/common/block/gpio_defs: Wake from either S0i3 or S3
Add a helper bit mask to enable wake from either S0i3 or S3.

BUG=None
TEST=Build the Guyrbush mainboard.

Change-Id: I934abad78135260081a61aee4c496b362e483de1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-25 01:24:33 +00:00
Matt DeVillier 640f549eac mb/purism/librem_mini: Drop superfluous devices from devicetree
The 'device pci 00.0 on end' entries are not necessary for socketed
devices unless a chip driver needs to be bound to a device, so remove
them from the devicetree. Also remove the `drivers/wifi/generic` chip
driver as it was not necessary either.

Change-Id: Id5f2e34d98b236f9cfac9f0afd8a8017e349603f
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-24 20:31:08 +00:00
Mathew King 156be2db5a mb/google/guybrush: Temporary fix to set eSPI mux
This change allows guybrush EC communication while other patches
in the SOC code are worked on.

BUG=b:183149183
TEST=Boot guybrush with EC comunication

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I56fb64d4c065cf0665025346218cc66d77dacb52
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51665
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-24 19:47:08 +00:00
Kangheui Won 39ef890336 mb/google/guybrush: disable KBRSTEN
GPIO129 is muxed with KBRST, so setting GPIO129 to low causes reset
when KBRSTEN is set to 1. Since reset value of KBRSTEN is 1 we need a
logic to clear it.

BUG=b:183340503
TEST=build

Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I194e8432a14d6105f6bcf12111647f5aad4e2de2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-24 19:37:09 +00:00
Wayne3 Wang 6d837df908 mb/google/volteer/variants/drobit: Modify touchpad power sequence
Modify power sequence of touchpad to meet the definition in the spec.

BUG=b:178353432
BRANCH=firmware-volteer-13672.B
TEST=build test firmware and verified by EE team.

Change-Id: I8b8e383223d017223c36044efdf21738fe26d2ea
Signed-off-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51514
Reviewed-by: Hao Chou <hao_chou@pegatron.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-24 17:43:36 +00:00
Tim Wawrzynczak 53d08b6ee2 sb/intel/common: Use new acpigen_write_PRT_*_entry functions
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I9f573b9bd40260ab963c5a4a965a6ac483af91ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-24 16:09:16 +00:00
Tim Wawrzynczak 290979f960 acpi: Add acpigen_write_PRT* helpers for generating _PRT entries
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ia666bd0e5db40d7873532dc22bc89be9854b903a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-24 16:08:57 +00:00
Marc Jones 93a4e0135c cpu/x86/smm: Fix SMM start address passing
This fixes an issue introduced in
    commit ad0116c032
    cpu/x86/smm_loaderv2: Remove unused variables

It removed one variable that was needed to set the SMM start address
that is used to set the SMM stack location.

Change-Id: Iddf9f204db54f0d97a90bb423b65db2f7625217f
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51721
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-24 15:36:36 +00:00
Patrick Rudolph 1834fbb83b device/azalia_device.c: Program beep verbs
Change-Id: I11b362d5e586194501de5dbd11f9c934a9d53940
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-03-24 07:55:15 +00:00
Angel Pons 5d31dfa8df device/azalia_device.c: Introduce AZALIA_MAX_CODECS
Add the AZALIA_MAX_CODECS Kconfig option and use it.

Change-Id: Ibb10c2f2992257bc261e6cb35f11cc4b2d956054
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-03-24 07:55:03 +00:00
Angel Pons 6da78660d0 device/azalia_device.c: Correct STATESTS access width
The HD Audio spec states that the STATESTS register is 16 bits wide.

Change-Id: If7859ed33e58d907a91c4ac8675892e37998cf41
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-03-24 07:54:46 +00:00
Angel Pons fa1befcb57 device/azalia_device.c: Unify `wait_for_valid` timeouts
The timeout is never reached when the codec is functioning properly.
Using a small timeout value can result in spurious errors with some
codecs, e.g. a codec that is slow to respond but operates correctly.
When a codec is non-operative, the timeout is only reached once per
verb table, thus the impact on booting time is relatively small. So,
use a reasonably long enough timeout to cover all possible cases.

Remove the unconditional 25 µs delay and increase the timeout delay.
The new value of 1 ms is the maximum of all existing implementations.
Currently, the only boards using this code are AMD reference boards:
- AMD Bilby
- AMD Mandolin
- AMD Padmelon

Change-Id: Ia5e4829d404dcecdb9e7a377e896a319cb38531a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-24 07:54:34 +00:00
Benjamin Doron 8c5994f92d mb/emulation/qemu-q35: Fix format specifier for a `size_t`
Fix compilation on GCC 10.2.1

Change-Id: I47d29ef065f57f171f429bb6a368bc86e31acee9
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-24 07:54:05 +00:00
Tim Crawford 427487b173 mb/system76/gaze15: Add System76 Gazelle 15
Tested with TianoCore payload (UefiPayloadPkg).

Working:

- PS/2 keyboard, touchpad
- Both DIMM slots
- Both NVMe ports
- SATA port
- All USB ports
- Webcam
- Ethernet
- Integrated graphics using Intel GOP driver
- Internal microphone
- Internal speakers
- S3 suspend/resume
- Flashing with flashrom
- Booting to Ubuntu Linux 20.10 and Windows 10

Not working:

- Discrete/Hybrid graphics

This requires a new driver to work correctly, which will be added and
enabled later.

Change-Id: I10667fa26ac7c4b8eb67da11f3e963062bd0db47
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47822
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-24 07:53:40 +00:00
Usha P f02fa4a1a8 mb/intel/adlrvp: Enable CnviBtAudioOffload
This change enables CnviBtAudioOffload. FSP is invoked to configure
BT over USB and BT I2S pins for cAVS connection.

BUG=None
TEST=Verified BT offload working on ADL RVP

Signed-off-by: Usha P <usha.p@intel.corp-partner.google.com>
Change-Id: I1185a6c2295bae7d469be4da86502506adbeb8cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-03-24 07:52:48 +00:00
Yu-Ping Wu 71c5ca764f soc/mediatek: Use MRC cache API for asurada
Use the MRC cache API for asurada, and sync dramc_param.h with dram
blob (CL:*3674585). With this change, the checksum, originally stored in
flash, is replaced with a hash in TPM. In addition, in recovery boot,
full calibration will always ne performed, and the cached calibration
data will be cleared from flash.

This change increases ROMSTAGE size from 236K to 264K. Most of the
increase is caused by TPM-related functions.

Add new API mtk_dram_init() to emi.h, so that 'dramc_parameter' can be
moved to soc folder.

With this CL, there is no significant change in boot time. Normal AP
reboot time (fast calibration) is consistently 0.98s as before, so
this change should not affect the result of platform_BootPerf.

BUG=b:170687062
TEST=emerge-asurada coreboot
TEST=Hayato boots with both full and fast calibration
BRANCH=none

Cq-Depend: chrome-internal:3674585, chrome-internal:3704751
Change-Id: Ief942048ce530433a57e8205d3a68ad56235b427
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-03-24 05:43:50 +00:00
Yu-Ping Wu 25ef410423 soc/mediatek/mt8192: Enlarge ROMSTAGE to 272K
Enlarge ROMSTAGE from 256K to 272K for the upcoming change of MRC cache
(CB:51620). To have more compact space usage, reduce BOOTBLOCK size from
64K to 60K (only 44K needed), and move starting address of DRAM blob
(DRAM_INIT_CODE) to 0x210000 (64K-aligned).

BUG=b:170687062
TEST=emerge-asurada coreboot
TEST=Hayato boots
BRANCH=asurada

Cq-Depend: chrome-internal:3704751
Change-Id: I7aaf9faf048e0adcb3a7d856d40891762c9a6604
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-03-24 05:43:05 +00:00
Derek Basehore cbe266142e mb/google/octopus: Wake up AP on AC plug and unplug
This patch makes all Octopus variants resume from S0ix/S3 on AC plug
and unplug.

Change-Id: Iab054d77368bf2047b6d523188b8c401a7643aaa
Signed-off-by: Derek Basehore <dbasehore@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-23 22:50:04 +00:00
Ronak Kanabar abfd165c86 vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2081_02
The headers added are generated as per FSP v2081_02.
Previous FSP version was v2081_02.
Changes Include:
- Adjust UPD Offset in FspmUpd.h and FspsUpd.h
- Add UPDs in Fsps.h and Fspm.h

BUG=b:180918805
BRANCH=None
TEST=Build and boot ADLRVP

Change-Id: I69611de8286a570c59a6b4a44b9164384e9be81f
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51632
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-23 20:23:05 +00:00
Felix Held 227c649522 soc/amd/cezanne: select HAVE_EM100_SUPPORT
This makes the EM100 option visible in Kconfig that makes sure that the
SPI settings that coreboot applies are valid for the EM100 that has some
limitations on the maximum SPI frequency and possibly on the supported
SPI modes. For the PSP SPI settings, the mainboard still might need to
provide EM100-specific settings for EFS_SPI_READ_MODE, EFS_SPI_SPEED and
EFS_SPI_MICRON_FLAG. Haven't checked if those PSP settings are correctly
integrated for Cezanne.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5dec9ce69628ca3623b5009d47f4b3dc020a3dad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-23 20:08:59 +00:00
Karthikeyan Ramasubramanian c3c7f8fc60 soc/amd/common/block/gpio_defs: Support wake and debounce configuration
Add a pad configuration macro to support configuring both wake and
debounce. This support is required by Pen Detect GPIO.

BUG=b:180539900
TEST=Build Guybrush mainboard.

Change-Id: I3343a4e80fd5aa3047d76ff9f91ea57c3763bbca
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-23 19:56:26 +00:00
Angel Pons 76def38abb nb/intel/haswell: Limit mainboard USB config array lengths
There are at most 14 USB2 ports and 6 USB3 ports on LynxPoint-H, and
there are at most 10 USB2 ports and 4 USB3 ports on LynxPoint-LP. Limit
the array lengths accordingly to cause build errors on invalid configs.

Change-Id: Ieda7a1320d78dbbcb651f1715a87cd1d202a79f2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51451
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-23 11:00:06 +00:00
Angel Pons 36714d9fe6 haswell boards: Use zero length for disabled USB ports
For disabled USB ports, the length setting does not matter. In future
commits, disabled USB ports will end up with length field set to zero.

Change-Id: I7613e1b0c89c0b58eca790ca14fcd1633c8a93af
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2021-03-23 10:59:40 +00:00
Angel Pons c4ee714881 nb/intel/haswell: Use unshifted SPD addresses in mainboards
It's common to use the raw, unshifted I2C address in coreboot. Adapt
mainboards accordingly and perform the shift in MRC glue code.

Tested on Asrock B85M Pro4, still boots and still resumes from S3.

Change-Id: I4e4978772744ea27f4c5a88def60a8ded66520e1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51458
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-23 10:59:26 +00:00
Angel Pons d99b693c96 nb/intel/haswell: Confine `pei_data` uses to raminit.c
Reorganize romstage.c to resemble sandybridge, and move everything that
needs `pei_data` into raminit.c function `perform_raminit`. Barring USB
settings, coreboot code no longer depends on pei_data.h definitions. It
still depends on MRC, though. For now.

Tested on Asrock B85M Pro4, still boots and still resumes from S3.

Change-Id: I433f88db5fe7a7533ab6837015647ec31fb45e88
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51449
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-23 10:59:15 +00:00
Sunway 8d529421d3 mb/google/kukui: Add a new config 'Makomo'
A new board introduced to Kukui family.

BUG=None
TEST=make # select Makomo
BRANCH=kukui

Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com>
Change-Id: I42b84e2c0926e755ba210fc8baac19f8ed2c4e57
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51565
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-23 01:45:41 +00:00
Ravi Sarawadi c6bc3a56d6 mb/google/volteer/variants/delbin: Disable PmcUsb2PhySusPgEnable
eDP panel flicker during system idle state is observed.
Disabling USB2 SUS well power gating can remove flicker symptom.
Please refer to doc#634894 for more details.

BUG=b:182323059
BRANCH=None
TEST=Boot and confirm no display flicker.

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: Icadf9c494fab82b219317c3ca3b04f633b543083
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2021-03-23 00:03:15 +00:00
Nick Vaccaro 7ef6aeec14 mb/google/volteer/variants/eldrid: Include SPD for H4AAG165WB-BCWE
Add SPD support to eldrid for DDR4 memory part H4AAG165WB-BCWE.

Eldrid should use DRAM_ID strap ID 4 (0100) on SKUs populated
with H4AAG165WB-BCWE DDR4 memory parts.

BUG=b:181732562
TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds
successfully.

Change-Id: I38cfe3eb26b00563ce17df3a3ac2a0a846f2ae00
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51667
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22 21:18:27 +00:00
Ian Feng 7be232a21c mb/google/dedede: Create cret variant
Create the cret variant of the waddledoo reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:181325655
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_CRET

Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I700201cf81b25c6776df3ec9fc843cd9bd8c88c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-03-22 17:31:24 +00:00
Felix Held 9aae28b548 soc/amd/common/block/psp/psp: update psp_status_nobase error message
When the soc_get_mbox_address functions returns 0 after not being able
to find an initialized PSP base address MSR or in case of Stoneyridge
the PSP's BAR3, the code will print an error string. This string needs
to reference both PSP_ADDR_MSR and PSP BAR3 and not only the latter one,
since in Picasso and Cezanne only the former one is present.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I32a1e87e2a7d89c7b53f47c987e7bf0556154cf7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-22 16:38:38 +00:00
hao_chou 9fd2ad1d52 mb/google/volteer/variants/copano: Configure specific DPTF parameters
Configure board specific DPTF parameters for copano

BUG=b:176961219
BRANCH=firmware-volteer-13672.B
TEST=build and verify by thermal team

Change-Id: Ibce67f81503b84b58798bc198947e61907276ad3
Signed-off-by: Hao Chou <hao_chou@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51561
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22 16:32:17 +00:00
Tim Wawrzynczak e433042a8e soc/intel/tigerlake: Add #include guards to soc/early_tcss.h
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I8a630655731b3ee30ef8377296878cce7b8c2201
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51648
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22 15:24:00 +00:00
Angel Pons c1301dd2d2 {lynxpoint/broadwell}: Set Azalia HDCFG.BCLD bit
Lock down several HD Audio registers by setting the HDCFG.BCLD bit.

Tested on Asrock B85M Pro4, the GCAP register becomes read-only.

Change-Id: Id6208289a68baaedc4aad51cc0c5355f996a1b00
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-03-22 13:01:19 +00:00
Angel Pons 1895d1a181 {lynxpoint,broadwell}/hda_verb.c: Drop effect-free write
This bit is hardwired to 1 (Intel High Definition Audio mode).

Change-Id: I3683497c5e2446f1d8319037583890b5d0a8a95c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-03-22 13:01:07 +00:00