53 Commits

Author	SHA1	Message	Date
Furquan Shaikh	20ecf2268b	lp4x: Add new memory parts and generate SPDs ... This change adds the following memory parts to LP4x global list and generates SPDs using gen_spd.go for TGL and JSL: 1. MT53E512M32D2NP-046 WT:E 2. K4U6E3S4AA-MGCR 3. H9HCNNNCPMMLXR-NEE 4. K4UBE3D4AA-MGCR BUG=b:157862308, b:157732528 Change-Id: Ib7538247d39dfe5faab277d646f87f09103d6969 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41989 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>	2020-06-06 09:29:54 +00:00
Furquan Shaikh	4bd95295f1	util/spd_tools/intel/lp4x: Add a global list of LP4x memory parts ... This change adds a JSON file (`global_lp4x_mem_parts.json.txt`) containing global list of LP4x memory parts to live along with the spd tools since the part information is not really any SoC or mainboard dependent and comes directly from the part datasheet. It can be shared by mainboards based on different platforms supported by the tools. BUG=b:155239397,b:147321551 Change-Id: I9e2f98fc9c1c8a7f73c9a1bfab22c996de222a32 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41874 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>	2020-06-06 09:27:59 +00:00
Furquan Shaikh	70001fe1f7	util: Add spd_tools to generate SPDs for TGL and JSL boards ... Serial Presence Detect (SPD) data for memory modules is used by Memory Reference Code (MRC) for training the memory. This SPD data is typically obtained from part vendors but has to be massaged to format it correctly as per JEDEC and MRC expectations. There have been numerous times in the past where the SPD data used is not always correct. In order to reduce the manual effort of creating SPDs and generating DRAM IDs, this change adds tools for generating SPD files for LPDDR4x memory used in memory down configurations on Intel Tiger Lake (TGL) and Jasper Lake (JSL) based platforms. These tools generate SPDs following JESD209-4C specification and Intel recommendations (doc Two tools are provided: * gen_spd.go: Generates de-duplicated SPD files using a global memory part list provided by the mainboard in JSON format. Additionally, generates a SPD manifest file (in CSV format) with information about what memory part from the global list uses which of the generated SPD files. * gen_part_id.go: Allocates DRAM strap IDs for different LPDDR4x memory parts used by the board. Takes as input list of memory parts used by the board (with one memory part on each line) and the SPD manifest file generated by gen_spd.go. Generates Makefile.inc for integrating the generated SPD files in the coreboot build. BUG=b:155239397,b:147321551 Change-Id: Ia9b64d1d48371ccea1c01630a33a245d90f45214 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>	2020-06-06 09:27:44 +00:00