7 commits

Author	SHA1	Message	Date
Arthur Heymans	d6f3dd83dc	nb/intel/x4x: Disable watchdog, halt TCO timer and clear timeout ... Especially on ICH7 failing to do so results in i2c block read being unusable. On ICH10 this problem doesn't manifest itself that much. This moves disabling the watchdog reboot to the northbridge code like i945 (even though it technically is southbridge stuff). TESTED on Intel DG41WV: hacking on raminit is much nicer since no need to do a hard power down for +4s are needed to clear the timeouts. Change-Id: Icfd3789312704f61000a417f23a121d02d2e7fbe Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>	2018-01-05 09:27:53 +00:00
Arthur Heymans	0c67a66d23	sb/intel/i82801jx: Remove dead code ... Setting up default BARs and DMI init code is done in northbridge code. Change-Id: I6cfa3018ca7f5ef351415c4ec6e178ade353f7a7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>	2017-08-10 16:00:59 +00:00
Arthur Heymans	d4ce1ded01	sb/intel/i82801jx: Add romstage smbus and i2c block operations ... Change-Id: I76bf1ed392d3d18059792106fc482d2259a3f084 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/20880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>	2017-08-07 06:59:09 +00:00
Arthur Heymans	16fe79048f	sb/intel/*: Use common SMBus functions ... All Intel southbridges implement the same SMBus functions. This patch replaces all these similar and mostly identical implementations with a common file. This also makes i2c block read available to all those southbridges. If the northbridge has to read a lot of SPD bytes sequentially, using this function can reduce the time being spent to read SPD five-fold. Change-Id: I93bb186e04e8c32dff04fc1abe4b5ecbc4c9c962 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>	2017-08-06 23:26:15 +00:00
Arthur Heymans	e5c8077c94	sb/intel/i82801jx: Add Interrupt pin and routing RCBA offsets macros ... Change-Id: If8e82a291f666d5f310422b100f02d5df17ab74e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>	2017-07-25 15:15:41 +00:00
Arthur Heymans	41114650d0	sb/intel/i82801jx: Add function to detect s3 resume ... File copied from i82801gx. Change-Id: I107087b6448f18b6a5ae21c2ae0392c057dd23b2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>	2017-07-23 20:34:11 +00:00
Arthur Heymans	349e08535a	sb/intel/i82801jx: Add correct PCI ids and change names ... Change-Id: Ic9226098dafa2465aa5fccc72c442de2b94e44c7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>	2017-07-21 15:44:19 +00:00

Renamed from src/southbridge/intel/i82801jx/i82801ix.h (Browse further)