Commit Graph

28538 Commits

Author SHA1 Message Date
Patrick Georgi 237baa1433 util/genbuild_h: Allow operation with older git versions
if git log --no-show-signature is not supported, retry without.

Change-Id: I9ee1f8e887cde5e4d6c5e6958f269c62572cdd53
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32299
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-12 10:19:59 +00:00
Furquan Shaikh 29368167b5 mb/google/hatch: Use GPIO IRQ for sx9310 device
This change uses GPIO IRQ instead of IOAPIC for GPP_A0 pad which is
the interrupt line for sx9310. This is required because IRQ# used by
GPP_A0 is allocated for PIRQ which does not allow IRQ# sharing.

Additionally, this change also configures GPP_A6 for GPIO IRQ. GPP_A6
is currently unused in the devicetree.

BUG=b:129794308
TEST=Verified that there are no interrupt storms on GPP_A0.

Change-Id: Ibb510a647391c0d9cb854d23656bb4b1cb7756ab
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-04-12 02:15:32 +00:00
Furquan Shaikh aea9871a62 drivers/i2c/sx9310: Add support for GPIO IRQ
This change adds support for mainboards to use GPIO IRQ instead of
IOAPIC to accomodate for cases where IOAPIC routing might not be
available for certain pads.

BUG=b:129794308

Change-Id: I3e2bb4280303cea177cc0c803d29140731e2b44a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32273
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-12 02:14:51 +00:00
Furquan Shaikh 55208409bc mb/google/hatch: Configure reset config to PLTRST for IOAPIC pads
This change configures reset config for all pads routed to IOAPIC as
PLTRST. This is required to ensure that the internal logic of the GPIO
gets reset any time the platform enters S3 or powers off and avoids
any interrupt storms on boot-up.

BUG=b:129933011
TEST=Verified that there are no interrupt storms on boot-up from S5.

Change-Id: Ib790280c9f1410fa18746d4d7d2a5027afd7585b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-04-12 02:14:24 +00:00
Furquan Shaikh 09b01de336 soc/intel/cannonlake: Do not use XIP_ROM_SIZE
XIP_ROM_SIZE Kconfig option isn't used on Cannon Lake and
family. Thus, this change selects NO_FIXED_XIP_ROM_SIZE to indicate to
build system so that romstage can be placed in less rigid manner.

BUG=b:129802811

Change-Id: I5f3786396246c89b1039ba1b6b332a32e6a0345d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-12 02:14:07 +00:00
Furquan Shaikh 9007118f32 mb/google/hatch: Skip UART0 config in FSP
UART0 is already configured in coreboot, so this change sets SerialIo
config for UART0 to PchSerialIoSkipInit to skip initialization in FSP.

BUG=b:130325418

Change-Id: Ifc88f4fa11bff2144417d5194776c15f9f7b60ac
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Shelley Chen <shchen@google.com>
2019-04-12 02:13:13 +00:00
Sergey Alirzaev 8f6f3ac199 util/genbuild_h: Do not print PGP verification results in `git log` output
Signed-off-by: Sergey Alirzaev <zl29ah@gmail.com>
Change-Id: I102ecc79bb649a67661c3d22988453dc7741acda
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32129
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-11 12:07:51 +00:00
Nico Huber 5c76ed66b8 libpayload/option table: Don't pad string entries with garbage
set_option_with() expects a buffer of the exact size of the option.

Change-Id: I21332394f88cf2daa4f733a544627d6d3c6ef26c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-11 12:03:07 +00:00
Nico Huber 8110f46fcc libpayload/storage: Add Apollo Lake AHCI ID to tested controllers
Change-Id: Iee244d0cd7d64934fbfc34778a45e21e97646628
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-11 12:02:58 +00:00
Frans Hendriks 31eac4d869 drivers/spi: Move M25Pxx commands to spi_winbond.h
Move Winbond M25PXX command values to spi_winbond.h
file.
The command values will be used for programming SPI
contoller of Intel Braswell, using this include file.

Update winbond.c file with coreboot header.

BUG=N/A
TEST=Facebook FBG-1701 with flashrom

Change-Id: I9c17c4ed7004209bd3c619d47a7474b0b7e17495
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-11 12:00:56 +00:00
Frans Hendriks 1385b7dd10 drivers/intel/fsp1_1: Configure UART after memory init
FSP code will default enable the onboard serial port.
When external serial port is used, this onboard port needs to be
disabled.

Add function mainboard_after_memory_init() function to perform
required actions to re-enabled output to external serial port.

BUG=N/A
TEST=LPC Post card on Intel Cherry Hill

Change-Id: Ibb6c9e4153b3de58791b211c7f4241be3bceae9d
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/28464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-11 11:57:55 +00:00
Maxim Polyakov dd11810367 mb/asrock/h110m: Add virtual LDN for SuperIO to DT
Adds virtual logical devices numbers for the Nuvoton (NCT6791D)
SuperIO to the devicetree.

Change-Id: I7df1633951c30fef14c62c89aaedebd3044b312f
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-04-11 11:37:10 +00:00
Hung-Te Lin 693709bbec google/kukui: Add variant 'Krane'
Add the new configuration 'Krane' that will need at least its own EC.
There's currently no difference in coreboot side.

BUG=b:130011505
TEST=make menuconfig; make -j # select board=Krane
BRANCH=None

Change-Id: Ibb2ec42b08f9a51b22c22f3fe99b203f5eb31627
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-11 11:36:24 +00:00
Elyes HAOUAS b217baa4ee nb/intel/i945: Fix ich7_setup_root_complex_topology
Element Self Description register (ESD) [23:16] is R/WO, so let
write the ESD.CID when we start ich7_setup_root_complex_topology.
This value is also used to program the R/WO 'Target Component ID'
registers of RPxD and HHD.
Once it is done, no need to rewrite on them as they become RO.
(For more information, please see ICH7 datasheet page 271.)

Tested done on 945G-M4 using printk before and after writing.
Before this change, writing on those registers had no effect:
ESD:  0x0104: 0x00000802
ULD:  0x0110: 0x00000001
ULBA: 0x0118: 0x00000000
RP1D: 0x0120: 0x01000003
RP2D: 0x0130: 0x02000003
RP3D: 0x0140: 0x03000002
RP4D: 0x0150: 0x04000002
HDD:  0x0160: 0x0f000002
RP5D: 0x0170: 0x05000002
RP6D: 0x0180: 0x06000002

Using this patche, those R/WO get the "right" values.
i.e., We can see RCBA32(ULBA) is now equal to (uintptr_t)DEFAULT_DMIBAR.
ESD:  0x0104: 0x00020802
ULD:  0x0110: 0x01010001
ULBA: 0x0118: 0xfed18000
RP1D: 0x0120: 0x01020003
RP2D: 0x0130: 0x02020003
RP3D: 0x0140: 0x03020002
RP4D: 0x0150: 0x04020002
HDD:  0x0160: 0x0f020002
RP5D: 0x0170: 0x05020002
RP6D: 0x0180: 0x06020002

Change-Id: I3f2199d6da22ce9995496c2a81363710edde81f3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30993
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-11 11:32:07 +00:00
Eric Lai 7fc25c013b mb/google/sarien: Reserve gpio pins for D3 cold control
Based on HW change, reserve gpio pins for D3 cold control.
A13,A15 for Card reader
H13 for M.2 SSD

BUG=b:123263562
TEST=N/A

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ib4245be8d77c015e56df7b1d53ef82722c51d656
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-04-11 11:28:09 +00:00
Roy Mingi Park 67d630945b mb/google/sarien: Change GPIOs to avoid leakage during S0iX
Three GPIOs are not being used and this change will save 2-3mW
power during S0iX and this power saving is only for Arcada

BUG=b:129990365
TEST= Measure total platform power during S0iX from Arcada

Change-Id: Ie0208bd6c7affb2e87fd76005b727ea7effdf434
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-04-11 11:27:57 +00:00
Jacob Garber f74f6cbde5 nb/intel/{gm45,i945,x4x}: Correct array bounds checks
There will be an out of bounds read if the index is equal
to the array size. Fix the checks to exclude this case.

Found-by: Coverity Scan, CID 1347350, 1347351
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I5b4e8febb68dfd244faf597dfe5cdf509af7a2ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-11 11:27:41 +00:00
Jacob Garber 94d61ecab0 util/inteltool: Swap conditions to prevent uninit reads
Both values in each array are only initialized if
`two_channels` is true, so we need to check that first.

Found-by: Coverity Scan #1370{584,585,588,589,590-596,600}
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I592bc6ae00f834f74a61668d7a3919014ec635f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-11 11:27:11 +00:00
Aamir Bohra e05fe3166e soc/intel/cannonlake: Correct the GPE DWx mapping for GPIO groups
This implementation corrects the GPE DWx mapping for GPIO groups.
The assignments is done in GPIO MISCFG register for all GPIO communities.
And configures the which GPIO communities get register as Tier1.

BUG=b:121212459
TEST: Verified the GPIO MISCFG is getting set as per updated map.

Change-Id: I451997367025a6dc9e5931bd649524e935ad6aca
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32175
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-11 11:26:37 +00:00
Matt Delco 4577cd2403 libpayload: keyboard: Add F11 and F12 support
The firmware is basically ignoring F11 and F12 without this change.

BUG=b:130143385
TEST=local compile and flash to device.  Confirmed that press of F11 and F12
keys now generates appropriate keypress events (and the same codes that
are already generated by these keys on an external USB keyboard).

Signed-off-by: Matt Delco <delco@chromium.org>
Change-Id: Ic43114aa99fc0a1345782c81ed2b90f5569af383
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-11 11:26:08 +00:00
Tim Wawrzynczak 7fd1845991 mb/google/ampton: Fix polarity of EN_PP3300_WLAN_L signal.
WiFi enable signal was configured and driven as active-high, but the signal is                            |To start the server in this Emacs process, stop the existing
actually active-low

BUG=b:130196983
BRANCH=none
TEST=Verified WiFi still works after boot, and also after a suspend/resume cycle.  Device powers down correctly using "poweroff".

Change-Id: I64a67f73564188ad0548a1a770169ef2bca47453
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32255
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-11 11:25:15 +00:00
Hung-Te Lin 0043a3db20 Documentation: Explain FMAP and FMD
The Flashmap (FMAP) was not clearly documented. The new flashmap.md
explains where to find more details about that and how / why it was used
in coreboot. Also explained what is FMD and how to use it (based on
original README.fmaptool).

BUG=None
TEST=None (only documentation)

Change-Id: Ia389e56c632096d7c905ed221fd4f140dec382e6
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-11 11:24:32 +00:00
Joel Kitching a751445de4 vboot: do not set VBSD_BOOT_FIRMWARE_WP_ENABLED flag
The value of "write protect" GPIO shall be read in depthcharge,
and the flag shall be set there instead.

BUG=b:124141368, b:124192753, chromium:1556855
TEST=Build locally
CQ-DEPEND=CL:1556855
BRANCH=none

Change-Id: I4d24a057b1385244a836a67c565ee6726a894fdc
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-11 11:23:33 +00:00
Joel Kitching ae0fb762a2 chromeos: clean up "recovery" and "write protect" GPIOs
The "write protect" GPIO's cached value is never actually
read after entering depthcharge.  Ensure the value from
get_write_protect_state() is being transferred accurately,
so that we may read this GPIO value in depthcharge without
resampling.

The cached value of the "recovery" GPIO is read only on certain
boards which have a physical recovery switch.  Correct some of
the values sent to boards which presumably never read the
previously incorrect value.  Most of these inaccuracies are from
non-inverted values on ACTIVE_LOW GPIOs.

BUG=b:124141368, b:124192753, chromium:950273
TEST=make clean && make test-abuild
BRANCH=none

Change-Id: Ic17a98768703d7098480a9233b752fe5b201bd51
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-11 11:23:26 +00:00
You-Cheng Syu 482eec0e1b google/kukui: Use internal CR50_IRQ pull-up
For Kukui CR50_IRQ pin, we're going to replace external pull-up with
internal pull-up. This change won't break older boards, so we can just
always do that when setting up GPIOs.

BUG=b:124821269
BRANCH=none
TEST=Waveform looks correct.

Change-Id: Ib1a90dce583a6aa0cec8ac8ba96d1362f50c16a8
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-04-11 11:22:11 +00:00
Kane Chen 38dbd68920 mb/google/octopus: Disable WLAN prior the entry of S5
ODM reported issues that some systems can't be shutdown to S5 very
occasionally.

ODM found issue is gone if they remove the WLAN card.
So, this change to disable WLAN before system enters S5.
This change is validated by ODM and it does help issue.

BUG=b:129377927

Change-Id: Ib8e81022b8c9b63bc75e5cc14121233222da7595
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32246
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Chen Wisley <wisley.chen@quantatw.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-11 11:21:58 +00:00
Julius Werner f028604718 kconfig_lint: Make uses of CONFIG() on an unknown option an error
This check had very few false positives which were all easily resolved,
and it's unlikely that further false positives will become problematic
in the future. On the other hand, it does detect a very severe bug (when
you think you're using a Kconfig but you aren't due to a typo), so since
warnings are currently not very visible, let's turn this into an error
because the pros clearly outweigh the cons for that.

Change-Id: I897b5e13d3242fb77b69f0bd3585baa7476aa726
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32257
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-11 11:21:55 +00:00
Elyes HAOUAS 5de93e9011 nb/amd/amdfam10/util.c: Use "CONFIG" only when appropriate
Change-Id: Idcdbbfa883c906db1ebb8d9bc7c9e277e7c0c949
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-11 11:21:42 +00:00
Patrick Rudolph d18a0cbfc1 Documentation: Make lenovo codenames human readable
Use rst parser to convert the csv to markdown tables.

Change-Id: I7fd61bd7a4e8818901520311332ae4027e7a7d02
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-11 11:21:10 +00:00
Patrick Rudolph 1e742217e6 Documentation: Allow the use of CSV
Allow the use of CSV files if properly referenced from markdown.
Sphinx will parse the file and create a human readable table,
allowing easy integration of autogenerated files.

Change-Id: I6fa13acf67ff1c6c9e3985054405c5446808da03
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-11 11:21:05 +00:00
Patrick Rudolph bff6dc7b8c Documentation: Add coreboot architecture
Describe the coreboot stages, given a short introduction what is done
and add a chart for coreboot's vs EDK II bootflow as well as the source
for the SVG.

TODO: Describe stages in detail in a separate commit.

Change-Id: I98cb61b1d0d29ac9d03f5ef3644d51a8e14bad74
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-04-11 11:20:40 +00:00
Andrea Barberio 4a5f7ece3f mb/ocp/monolake: Add board.fmd
Change-Id: I6095c3b30990b530c5bc4e2c808879252680e1d7
Signed-off-by: Andrea Barberio <barberio@fb.com>
Signed-off-by: David Hendricks <dhendrix@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-10 18:46:56 +00:00
Maxim Polyakov bcd23b05c1 Doc/mb/asrock/h110m: update info about PEG
- Now there is no need to additionally configure the FSP
   before building;
 - PEG works with high link speed 8 GT/s (Gen 3);
 - external GPU supported, but dynamic switching between iGPU and PEG
   is not yet supported.

Change-Id: Ie0f9db47c0b88052b090cba139f0ae821758935d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31949
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-10 13:56:54 +00:00
Julius Werner 0de2fa0a62 libpayload: Deduplicate strtol and strtoull
Our strtol() and strtoull() function contain almost exactly the same
code. This is a) bad in general and b) may cause the code to get out of
sync, such as it recently happened with CB:32029.

This patch changes strtol() to be based on strtoull() so that the main
parsing code exists only once, and also adds a strtoll() to round off
the library. Also fix the bounds imposed by strtoul() to be based on the
actual length of a 'long', not hardcoded to 32-bits (which is not
equivalent on all architectures).

Change-Id: I919c65a773cecdb11739c3f22dd0d182ed50c07f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-10 10:44:31 +00:00
Julius Werner 18c1b6b240 libpayload: limits.h: Provide reliable definitions for all XXX_MAX/MIN
Our current limits.h only provides (U)INT_MAX constants. This patch adds
most others expected by POSIX. Since some of these may be different
depending on architecture (e.g. 'long' is 32-bit on x86 and 64-bit on
arm64), provide a definition that will automatically figure out the
right value for the data model the compiler is using (as long as it's
using two's complement for signed integers, which I think we can assume
these days).

Change-Id: I1124a41279abd4f53d208270e392e590ca8eaada
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-10 10:43:27 +00:00
Julius Werner f5b76fe9e9 libpayload: Fix CONFIG_LP_DEBUG_MALLOC for 64-bit archs
New compilers are a little more stringent about defining the same
prototype more than once, so some of our CONFIG_LP_DEBUG_MALLOC wrappers
don't quite work the way they are written anymore. Also, several of the
printf()s weren't written 64-bit safe. And let's add some
double-evaluation safety while I'm here anyway... and I have no idea why
this ever depended on CONFIG_LP_USB, that just seems like a typo.

Change-Id: Ib54ebc3cfba99f372690365b78c7ceb372c0bd45
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/14921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-04-10 10:42:45 +00:00
Francois Toguo 651d8dd4f6 libpayload: Fix potential NULL pointer dereference
Found-by: Klockwork
BUG=NONE
TEST=Boot to OS on GLK Sparky

Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Change-Id: I9d4636f0429de829e746909492c2f543026a02ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-09 17:25:41 +00:00
Jacob Garber e0c181d487 nb/intel/sandybridge: Set uninitialized run length
If the entire array is zero, then the length of the
longest zero run is the length of the array itself.

Found-by: Coverity Scan, CID 1229715
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Id23292087b14182448d70117915fb044e9c579f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-09 17:24:40 +00:00
You-Cheng Syu cc86d8921b google/kukui: Configure AP_IN_SLEEP_L correctly
This pin should be set to its alternative function SRCLKENA0 instead of
GPIO, so that SPM (a power management component of MT8183) can control
it.

BUG=b:113367227
BRANCH=none
TEST=1. Boot. Run 'powerinfo' in EC console and see power state in S0.
     2. Run 'powerd_dbus_suspend --wakeup_timeout=10', and then
        run 'powerinfo' in EC console and see power state in S3.
     3. Wait until AP resume.
     4. Run 'powerinfo' in EC console and see power state back to S0.

Change-Id: I0a7e34f95381dec17eb6d166d6552c12e021bd9a
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32120
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-09 17:23:59 +00:00
Philip Chen 61d365fafd mb/google/hatch: Support 16MiB fmap
Add a fmd file for 16MiB fmap, so that we can support
both 16MiB / 32MiB SPI flash ROM chips.

BUG=b:129464811
TEST=build hatch firmware image with 16MiB fmap and
verify fmap is updated by 'fuility dump_fmap'

Change-Id: Ifc0103c7fd0d99439f40a31d23422401a6dce826
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-09 17:23:33 +00:00
Patrick Rudolph 15589b4e56 arch/x86/smbios: Reference type 7
Fill in the handle to cache entries of type 7 in the type 4 structure.

Tested on Intel Sandy Bridge (Lenovo T520).
All 3 caches are referenced.

Change-Id: Idf876b0c21c65f72a945d26c5898074b140763f8
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-04-09 17:22:41 +00:00
Patrick Rudolph fc5b80943b arch/x86/smbios: Add type 7
The SMBIOS spec requires type 7 to be present.

Add the type 7 fields and enums for SMBIOS 3.1+ and fill it with the
"Deterministic Cache Parameters" as available on Intel and AMD.

As CPUID only provides partial information on caches, some fields are set to
unknown.
The following fields are supported:
* Cache Level
* Cache Size
* Cache Type
* Cache Ways of Associativity

Tested on Intel Sandy Bridge (Lenovo T520).
All 4 caches are displayed in dmidecode and show the correct information.

Change-Id: I80ed25b8f2c7b425136b2f0c755324a8f5d1636d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2019-04-09 17:22:24 +00:00
Patrick Rudolph 835ca8ee64 arch/x86/cpu: Add functions to determine CPU vendor
Add two functions to determine if CPU is made by a specific vendor.
Use Kconfig symbols to allow link time optimizations.

Change-Id: I1bd6c3b59cfd992f7ba507bc9f9269669920b24f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Julien Viard de Galbert <coreboot-review-ju@vdg.name>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-09 17:21:50 +00:00
Tim Wawrzynczak 5ce1698138 mb/google/hatch: Add ACPI support for BT reset functionality
Expose the Bluetooth BT_DISABLE_L signal in Hatch's devicetree,
on both USB2 port 5 and 10.

BUG=b:123293169
BRANCH=none
TEST=compiles, verified kernel is able to find the reset-gpio

Change-Id: I6e4d9786e44f12da71533b6740fdd390f3a57e40
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32216
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-09 17:20:59 +00:00
Nico Huber baa070a81f src: Fix remaining #include <timer.h>
Follow-up to add76f91d5 (src: Use #include <timer.h> when appropriate).

Change-Id: I7813daa0b73039ec76d33a16ce3ae0ce6cc7f2cc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-04-09 17:20:35 +00:00
Martin Roth d727fb5035 util/docker: Update coreboot-sdk Dockerfile for new debian image
libssl1.0-dev is no longer available:
- Update to libssl-dev
- Add libcrypto++-dev to provide additional crypto libraries not
available in libssl-dev.

Change-Id: Ie10e14ebf7ae849301302008ee6ffeec1f40ccab
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-04-09 14:12:54 +00:00
David Hendricks c4f3972f2e mb/facebook/watson: Make turbo mode configurable (disabled by default)
Change-Id: Ief1eaab960c8fdab5bd5041b1a4f0c6ba1dd833f
Signed-off-by: David Hendricks <dhendrix@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32222
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-08 20:55:13 +00:00
Nico Huber 44ad93e970 Docs/kconfig: Update to use CONFIG()
Change-Id: Ica7b601d1c9c3bcf39b8b805d48e969f8a944927
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-04-08 19:01:40 +00:00
Nico Huber 8c11d05a3e nb/amd/pi/agesawrapper: Drop stale comment about IS_ENABLED()
We decided to not care about compile-time errors. So drop the comment,
the code was updated already.

Change-Id: Ib115fa6e2c48bfde7f67c327d42b3fe0e7af8c1f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-08 18:54:25 +00:00
Nico Huber 8f7a53a968 commonlib/cbfs: Check for presence of CONFIG() macro
Check for CONFIG not IS_ENABLED, as we use the former now.

Change-Id: I7e1b67bc0894ca6f0149039054449656b58bcdd3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-08 18:52:38 +00:00