The PCIe subsystem was constantly waking up boards from
S3 and S5. Completely disable PCIe wake ups. It can be made
mainboard-configurable later if needed.
BUG=chrome-os-partner:24004
BRANCH=None
TEST=Both S3 and EC RW->RW update (trip through S5) don't
cause wakeups.
Change-Id: I922e2947c4b6e29277d913f06192601a2954f8fe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176791
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4972
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
GPIOs which trigger SMIs only set the status bits in the ALT_GPIO_SMI
regier. No bits in the SMI_STS register are set. Therefore, the
ALT_GPIO_SMI register needs to be read and cleared on every SMI.
Additionally, the mainboard_gpi_smi() handler needs to be called as
well on every SMI because of this property.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted to recovery screen. Typed 'lidclose' on EC
console. SMI occurred which caused the board to be shutdown.
Change-Id: Ic204d8b928a0cb4f51f108a649f374d9f94e4f47
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176391
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4958
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
In order for gpio pins to trigger an smi/sci the GPIO_ROUT
register needs to be set accordingly. For SMI, the ALT_GPIO_SMI
register needs to be enabled for each gpio as well.
The first 8 gpios from the suspend and core well are the only gpios
that can trigger an SMI or SCI. The settings for the GPIO_ROUT
and ALT_GPIO_SMI register are not commited until the SMM settings
are enabled in the southcluster.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted. Manually triggered SCI by changing GPE0a_EN
and toggling PCH_WAKE_L on the EC console.
Change-Id: Id79b70084edc39fc047475e984494c224bd75d6d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176390
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4957
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Initialize SMM on all CPUs by relocating the SMM region
and setting SMRR on all the cores. Additionally SMI
is enabled in the south cluster.
BUG=chrome-os-partner:22862
BRANCH=None
TEST=Built and booted rambi. Tested with DEBUG_SMI and noted
power button turns off board while in firmware.
Change-Id: I92e3460572feeb67d4a3d4d26af5f0ecaf7d3dd5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173983
Reviewed-on: http://review.coreboot.org/4892
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
