Commit Graph

8900 Commits

Author SHA1 Message Date
Patrick Georgi d2e0dd5bc1 buildgcc: Re-add some break statements
While some of the case .. break statement actually weren't needed,
too are, since otherwise the option parsing loop hangs.

Exit conditions for that endless loop: "--" or no more arguments,
in line with GNU command line parsing rules.

Change-Id: I0dbc35e530fb8c93a0f7de05ac47f325555ad4a4
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/3418
Tested-by: build bot (Jenkins)
Reviewed-by: David Hubbard <david.c.hubbard+coreboot@gmail.com>
2013-06-09 08:34:45 +02:00
Kyösti Mälkki ecbc0c5cb9 usbdebug: Fix use without EARLY_CONSOLE
If EARLY_CONSOLE is not selected, the PCI function for EHCI
host controller must be configured in ramstage instead.

Change-Id: I20f7569f79484c744bc413450bfa139052f3580f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3383
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-06-07 09:50:12 +02:00
Denis 'GNUtoo' Carikli 4062f179a7 Lenovo X60: Add int15 handler
Without that commit, with CONFIG_PCI_OPTION_ROM_RUN_YABEL,
  The VGA option rom doesn't init the right display:
  it initializes the external display, where we have
  a black scren(with backlight on).

This commit is based on the code of mainboard.c in
  src/mainboard/roda/rk886ex.

Change-Id: I8457aaf0503e0efdf0fcba9ff5e8a07ac04c5ca6
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3265
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2013-06-07 02:49:31 +02:00
Denis 'GNUtoo' Carikli 7ed739445b i945: Add Display defines for int15h handler.
Change-Id: I7bc99761c7047e64b4e29c307ad779cec49c17c8
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3306
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-06-07 02:49:06 +02:00
Gerd Hoffmann 8130b1ec1b qemu: copy dsdt tables from SeaBIOS, adapt for coreboot and enable acpi
First copy over from SeaBIOS git repo, then adapt for coreboot:

Disable cpu/pci hotplug bits.  Disable dynamic pci window.
Both depend on stuff in the SSDT tables created by SeaBIOS.

Bits are left in, but deactivated via #if 0, so it's easier
to see the differences when diffing the coreboot tables with
the SeaBIOS tables.

Adapt dsdt DefinitionBlock.

Enable acpi table generation in acpi_tables.c.

With this patch linux boots successfully with ACPI enabled.
It's not bug-free though.  Missing cpu detection leads to
funky messages like this one:

  weird, boot CPU (#0) not listed by the BIOS.

and SMP most likely wouldn't work either.

Change-Id: Ic3803a6f1ef6d54c11cc4ca3844d3032a374ae6b
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3342
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2013-06-06 21:31:51 +02:00
Nico Huber 7bb02512d9 ec/acpi: Add ACPI methods for generic EC access
Port most of the functions found in ec/acpi/ec.c to ACPI Source Language
(ASL). These functions are used to control embedded controllers with the
standard ACPI interface (mostly through i/o ports 0x62 / 0x66).

The following methods are implemented and tested against the power
managements channels of a ITE IT8516E embedded controller:
 * WAIT_EC_SC           Wait for a bit in the EC_SC register
 * SEND_EC_COMMAND      Send one command byte to the EC_SC register
 * SEND_EC_DATA         Send one data byte to the EC_DATA register
 * RECV_EC_DATA         Read one byte of data from the EC_DATA register
 * EC_READ              Read one byte from ec memory (through cmd 0x80)
 * EC_WRITE             Write one byte to ec memory (through cmd 0x81)

To use the provided methods, one should include `ec/acpi/ec.asl` in the
EC device code. Prior doing so, two macros should be defined to identify
the used i/o ports:
 * EC_SC_IO     I/o address of the EC_SC register
 * EC_DATA_IO   I/o address of the EC_DATA register

Change-Id: I8c6706075fb4980329c228e5b830d5f4e9b188dd
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3285
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2013-06-06 21:19:28 +02:00
Olivier Langlois ccc7d1f229 Intel Atom cpu support to msrtool
Added support for Intel Atom cpu to msrtool
Fixed a cut&paste error in nehalem msr bits definition

It has been tested with a N455 cpu and msrtool output can be review at:
http://www.trillion01.com/coreboot/msrtool_atom.txt

Change-Id: I0ecf455b559185e2d16fa1a655bf021efc2ef537
Signed-off-by: Olivier Langlois <olivier@olivierlanglois.net>
Reviewed-on: http://review.coreboot.org/3351
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-06 21:02:09 +02:00
Bruce Griffith e1cddc1278 AMD Trinity: Remove unnecessary lookup table copy
The DDI connector table and the PCIe Port List lookup table are
copied onto HEAP.  This copy is not needed since these are lookup
tables used to define the platform configuration.

Change-Id: If4760f80e08faa8da4fd11337a3812f89cf805f9
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3394
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-06 20:59:59 +02:00
Bruce Griffith 283ba78415 AGESA: Add "const" modifier to function parameters
Add CONST modifiers to read-only pass-by-reference function
parameters in AGESA.  This allows the use of "const" modifiers
on the declaration of lookup tables that are pass-by-reference.
These will be used to identify tables that are copied onto the
HEAP but don't need to be.

Change-Id: Ie1187a427804fddf47b935a110ad23931a3447a9
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3393
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-06 20:59:43 +02:00
Gerd Hoffmann aa588e0273 qemu: wind up new cpu chip
Add boot cpu to the device tree.  Figure the number of CPUs installed
(using the qemu firmware config interface) and add cpu devices for them,
so they show up in all generated BIOS tables correctly.  This gets SMP
going.

Change-Id: I0e99f98942d8ca90150b27fc13c1c7e926a1a644
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3345
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-06 20:52:48 +02:00
Gerd Hoffmann cbf30736b6 qemu: add x86 cpu
This patch adds a qemu x86 cpu chip.  It has no initialization function
as this isn't needed on virtual hardware.  A virtual machine can have
pretty much any CPU: qemu emulates a wide range of x86 CPUs (try 'qemu
-cpu ? for a list), also with 'qemu -cpu host' the guest will see a cpu
which is (almost) identical to the one on the host machine.  So I've
added X86_VENDOR_ANY as wildcard match for the cpu_table.

Change-Id: Ib01210694b09702e41ed806f31d0033e840a863f
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3344
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-06 20:52:30 +02:00
Nico Huber a53266bee0 ec/kontron/it8516e: Add it8516e EC driver
This driver communicates with the IT8516e on the Kontron KTQM77.
Since we don't know if the firmware and protocol are standard for
the chip or customized to the board, call it kontron/it8516e.

Change-Id: I7382172c6d865d60106c929124444821a07a5184
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3390
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-06 20:39:52 +02:00
Nico Huber ea6d6e8c1f intel/bd82x6x: Add option to include ethernet firmware
Change-Id: Idf804ed29a67bad732df19e6981f74c8d0c354b5
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3388
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-06 20:38:41 +02:00
Patrick Georgi 4af2bb5724 intel/bd82x6x: fix building usb debug on SNB/IVB
Change-Id: Ica3afbf8277cb025251da7af181f8de0d0036b45
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/3389
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-06 20:34:27 +02:00
Alexandru Gagniuc 5c4645b0ee (Trivial) early_smbus: fix printsmbus macro
When I've first written this macro in 2011, the correct define for
verbose SMBus message was CONFIG_DEBUG_SMBUS_SETUP. This has since
been changed to CONFIG_DEBUG_SMBUS. I didn't catch that, and this made
the printsmbus macro always evaluate to an empty statement.

Use the proper CONFIG_DEBUG_SMBUS define. This makes printsmbus
functional again.

Change-Id: Iaf03354b179cc4a061e0b65f5b746af10f5d2b88
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/3379
Tested-by: build bot (Jenkins)
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2013-06-06 08:52:57 +02:00
Gerd Hoffmann 3979eda571 qemu: add power management function to device tree
Needed to make 'register "gpo" = ...' work.
While being at it add comments saying which device is which.

Change-Id: I911d5e4a7b6c7abf4ad73e863ab201e9e55ee0d4
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3346
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-05 18:26:20 +02:00
Gerd Hoffmann 4321d60acb console: log qemu debugcon detection result
Change-Id: Ie0507475f33d029d6e8ce59f138e0e7da5156d4f
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3339
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-05 18:25:34 +02:00
Gerd Hoffmann 22f01e611b console: add qemu debugcon detection
The qemu debugcon port returns 0xe9 on reads in case the device is
present.  Use that for detection and write console output to the
port only in case the device is actually present.

Change-Id: I41aabcf11845d24004e4f795dfd799822fd14646
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3338
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-05 18:24:08 +02:00
Gerd Hoffmann d7c6e444ac console: add qemu prefix to debugcon
Change-Id: Ibcc0a94638c022a76cd3c2e3387af6e1ab757ccb
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3337
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-05 18:22:46 +02:00
Gerd Hoffmann 2b9620343b qemu: Initial support for the qemu firmware config interface.
qemu has a special device to pass configuration information
from qemu to the firmware.  This patch adds initial support
the interface, namely some infrastructure, detection code and
a function to query the number of CPUs.

Change-Id: I43ff5f4fbf12334a91422aa38f514a82a1d5219e
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3343
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-05 17:46:14 +02:00
Paul Menzel 019f0fc2c7 Revert "Asus F2A85-M: Activate IOMMU support"
This reverts commit eed28f97b3.

For whatever reason, the dependencies were lost in Gerrit and the
commit [1] was submitted without its dependencies. As a result
buidling the ASUS F2A85-M fails now [2] and therefore commits
based on this commit fail to pass the buid tests by Jenkins.

    […]
    Created CBFS image (capacity = 8387656 bytes)
        LINK       cbfs/fallback/romstage_null.debug
        CC         cbfs/fallback/coreboot_ram.debug
    coreboot-builds/asus_f2a85-m/generated/coreboot_ram.o:(.data+0x16b9c): undefined reference to `GnbIommuScratchMemoryRangeInterface'
    collect2: error: ld returned 1 exit status
    make: *** [coreboot-builds/asus_f2a85-m/cbfs/fallback/coreboot_ram.debug] Error 1
    make: *** Waiting for unfinished jobs....
    coreboot-builds/asus_f2a85-m/mainboard/asus/f2a85-m/buildOpts.romstage.o:(.data+0x3d8): undefined reference to `GnbIommuScratchMemoryRangeInterface'
    collect2: error: ld returned 1 exit status
    make: *** [coreboot-builds/asus_f2a85-m/cbfs/fallback/romstage_null.debug] Error 1
    […]

Therefore revert the commit to get the tree working again and
submit this patch with its dependencies again.

[1] http://review.coreboot.org/#/c/3317/
[2] http://qa.coreboot.org/job/coreboot-gerrit/6618/testReport/junit/(root)/board/i386_asus_f2a85_m/

Change-Id: I911755884da09eb0a0651b8db07ee2a32e6eaaaa
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3373
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-06-05 12:50:23 +02:00
Gerd Hoffmann 082d2a0ab7 qemu: fix IRQ routing setup
Do the setup for all PCI slots, not only the third.

Also remove the bogus message, as slot 3 may carry
any device, not only NICs.

This makes IRQ setup simliar to SeaBIOS.

SeaBIOS assignments (with patch for logging added,
and a bunch of pci devices for testing purposes):

    PCI IRQ [piix]: bdf=00:01.3 pin=1 line=10
    PCI IRQ [piix]: bdf=00:03.0 pin=1 line=11
    PCI IRQ [piix]: bdf=00:04.0 pin=1 line=11
    PCI IRQ [piix]: bdf=00:05.0 pin=1 line=10
    PCI IRQ [piix]: bdf=00:06.0 pin=1 line=10
    PCI IRQ [piix]: bdf=00:1d.0 pin=1 line=10
    PCI IRQ [piix]: bdf=00:1d.1 pin=2 line=10
    PCI IRQ [piix]: bdf=00:1d.2 pin=3 line=11
    PCI IRQ [piix]: bdf=00:1d.7 pin=4 line=11

Coreboot assignments without this patch:

    Assigning IRQ 11 to 0:3.0

Coreboot assignments with this patch:

    Assigning IRQ 10 to 0:1.3
    Assigning IRQ 11 to 0:3.0
    Assigning IRQ 11 to 0:4.0
    Assigning IRQ 10 to 0:5.0
    Assigning IRQ 10 to 0:6.0
    Assigning IRQ 10 to 0:1d.0
    Assigning IRQ 10 to 0:1d.1
    Assigning IRQ 11 to 0:1d.2
    Assigning IRQ 11 to 0:1d.7

Change-Id: Ie96be39185f2f1cbde3c9fc50e29faff59c28493
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3334
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-06-05 12:49:00 +02:00
Denis 'GNUtoo' Carikli fd39ddd635 Intel 945: Select LAPIC_MONOTONIC_TIMER for X86EMU_DEBUG_TIMINGS
X86EMU_DEBUG_TIMING is needed for producing i915tool
  compatible output. So add its dependencies to the
  i945’s Kconfig in order to be able to use X86EMU_DEBUG_TIMINGS,
  which depends on HAVE_MONOTONIC_TIMER which
  LAPIC_MONOTONIC_TIMER provides/selects.

Note that UDELAY_LAPIC is already selected by the Intel CPU.

Change-Id: Ie834ebc92e527eb186a92b39341ebd0a08889fb0
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3356
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-05 01:07:14 +02:00
Rudolf Marek eed28f97b3 Asus F2A85-M: Activate IOMMU support
Activate the IOMMU support for the Asus F2A85-M.

Add the device to `devicetree.cb`.

    $ pci -s 0.2
    […]
    00:00.2 IOMMU: Advanced Micro Devices [AMD] Family 15h (Models 10h-1fh) I/O Memory Management Unit

    $ dmesg
    […]
    [    0.000000] ACPI: IVRS 00000000bf144e10 00070 (v02  AMD   AMDIOMMU 00000001 AMD  00000000)
    [    0.000000] ACPI: SSDT 00000000bf144e80 0051F (v02    AMD     ALIB 00000001 MSFT 04000000)
    [    0.000000] ACPI: SSDT 00000000bf1453a0 006B2 (v01 AMD    POWERNOW 00000001 AMD  00000001)
    [    0.000000] ACPI: SSDT 00000000bf145a52 00045 (v02 CORE   COREBOOT 0000002A CORE 0000002A)
    […]
    [    0.465114] [Firmware Bug]: ACPI: no secondary bus range in _CRS
    […]
    [    0.567330] pci 0000:00:00.0: >[1022:1410] type 00 class 0x060000
    [    0.567364] pci 0000:00:00.2: >[1022:1419] type 00 class 0x080600
    [    0.567427] pci 0000:00:01.0: >[1002:9993] type 00 class 0x03000
    […]
    [    0.597731] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT]
    [    0.597899] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PIBR._PRT]
    [    0.597933] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.SBR0._PRT]
    [    0.597972] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.SBR1._PRT]
    [    0.598073]  pci0000:00: >Requesting ACPI _OSC control (0x1d)
    [    0.603808]  pci0000:00: >ACPI _OSC request failed (AE_NOT_FOUND), returned control mask: 0x1d
    [    0.612397] ACPI _OSC control for PCIe not granted, disabling ASPM
    [    0.620508] Freeing initrd memory: 14876k freed
    […]
    [    0.882674] pci 0000:00:01.0: >Boot video device
    [    0.882876] PCI: CLS 64 bytes, default 64
    [    0.897088] AMD-Vi: Enabling IOMMU at 0000:00:00.2 cap 0x40 extended features:  PreF PPR GT IA
    [    0.905816] pci 0000:00:00.2: >irq 40 for MSI/MSI-X
    [    0.917457] AMD-Vi: Lazy IO/TLB flushing enabled
    [    0.922076] PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
    [    0.928500] software IO TLB [mem 0xbb13d000-0xbf13cfff] (64MB) mapped at [ffff8800bb13d000-ffff8800bf13cfff]
    [    0.938535] LVT offset 0 assigned for vector 0x400
    [    0.943338] perf: AMD IBS detected (0x000000ff)
    [    0.948037] audit: initializing netlink socket (disabled)
    [    0.953432] type=2000 audit(1369659616.800:1): initialized
    [    0.977011] HugeTLB registered 2 MB page size, pre-allocated 0 pages
    […]
    [    7.881938] radeon 0000:00:01.0: >VRAM: 512M 0x0000000000000000 - 0x000000001FFFFFFF (512M used)
    [    7.881941] radeon 0000:00:01.0: >GTT: 512M 0x0000000020000000 - 0x000000003FFFFFFF
    […]
    [    7.885516] radeon 0000:00:01.0: >irq 48 for MSI/MSI-X
    [    7.885525] radeon 0000:00:01.0: >radeon: using MSI.
    […]
    [    8.276775] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae000 flags=0x0010]
    [    8.287363] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acc00 flags=0x0010]
    [    8.297945] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae200 flags=0x0010]
    [    8.308527] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae080 flags=0x0010]
    [    8.319109] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae240 flags=0x0010]
    [    8.329694] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001accc0 flags=0x0010]
    [    8.340276] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ace80 flags=0x0010]
    [    8.350858] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acd80 flags=0x0010]
    [    8.361441] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae280 flags=0x0010]
    [    8.372022] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae180 flags=0x0010]
    [    8.382605] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ace00 flags=0x0010]
    [    8.393188] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acdc0 flags=0x0010]
    [    8.403770] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ace40 flags=0x0010]
    [    8.414353] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae1c0 flags=0x0010]
    [    8.424936] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acc40 flags=0x0010]
    [    8.435518] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acc80 flags=0x0010]
    [    8.446100] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae2c0 flags=0x0010]
    [    8.456684] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae300 flags=0x0010]
    [    8.467265] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae340 flags=0x0010]
    [    8.477849] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae380 flags=0x0010]
    [    8.488431] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae3c0 flags=0x0010]
    [    8.499013] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae0c0 flags=0x0010]
    [    8.509596] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acec0 flags=0x0010]
    [    8.520179] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acd00 flags=0x0010]
    [    8.530761] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad000 flags=0x0010]
    [    8.541343] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae400 flags=0x0010]
    [    8.551925] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae440 flags=0x0010]
    [    8.562509] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acf00 flags=0x0010]
    [    8.573090] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae480 flags=0x0010]
    [    8.583675] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae100 flags=0x0010]
    [    8.594257] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae4c0 flags=0x0010]
    […]
    [    8.604840] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acf40 flags=0x0010]
    [    8.615421] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acd40 flags=0x0010]
    [    8.626004] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad140 flags=0x0010]
    [    8.636587] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad040 flags=0x0010]
    [    8.647169] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad080 flags=0x0010]
    [    8.657751] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae500 flags=0x0010]
    [    8.668335] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad100 flags=0x0010]
    [    8.678917] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad0c0 flags=0x0010]
    [    8.689499] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acf80 flags=0x0010]
    [    8.700080] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acfc0 flags=0x0010]
    [    8.710664] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae140 flags=0x0010]
    [    8.721246] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae040 flags=0x0010]
    [    8.731828] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad180 flags=0x0010]
    [    8.742412] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae540 flags=0x0010]
    [    8.752995] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad280 flags=0x0010]
    [    8.763577] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad340 flags=0x0010]
    [    8.774160] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad200 flags=0x0010]
    [    8.784741] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad300 flags=0x0010]
    [    8.795324] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae5c0 flags=0x0010]
    [    8.805906] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae640 flags=0x0010]
    [    8.816490] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad2c0 flags=0x0010]
    [    8.827072] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad1c0 flags=0x0010]
    [    8.837655] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad240 flags=0x0010]
    [    8.848238] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae580 flags=0x0010]
    [    8.858819] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae600 flags=0x0010]
    [    8.869402] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad3c0 flags=0x0010]
    [    8.879985] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad380 flags=0x0010]
    [    8.890568] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae7c0 flags=0x0010]
    [    8.901151] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae740 flags=0x0010]
    [    8.911732] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae6c0 flags=0x0010]
    [    8.922316] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae780 flags=0x0010]
    [    8.932897] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae700 flags=0x0010]
    [    8.943480] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae680 flags=0x0010]
    [    8.963011] [drm] PCIE GART of 512M enabled (table at 0x0000000000040000).
    [    8.963165] radeon 0000:00:01.0: >WB enabled
    […]

It is not known, what the implications of the `IO_PAGE_FAULT` are.

Change-Id: Ic5fde609322a5fdeb1a48052c403847197752a4b
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/3317
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 23:49:20 +02:00
Denis 'GNUtoo' Carikli 4cdc5d6fc6 Yabel : Add tracing option needed by i915tool.
This patch was made by listenning to what Ron Minnich told
  me to do on #coreboot IRC channel on Freenode with my
  adaptations on top.

i915tool is at https://code.google.com/p/i915tool/ ,
  the one in coreboot is outdated.

Change-Id: I13cd684f4c290114836fbd7babd461153e8d6124
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3277
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 22:57:26 +02:00
Alexandru Gagniuc 67f556c296 viatool: Add utility to read various configuration bits on VIA systems
viatool is a utility for extracting useful for extracting certain configuration
bits on VIA chipsets and CPUs. It is a fork of inteltool.

viatool is currently focused on "quirks". Quirks are device configurations that
cannot be accessed directly. They are implemented as hierarchical configurations
in the PCI or memory address spaces (index/data register pairs). Such
configurations refer to hardware parameters that are board specific. Those
parameters would otherwise be difficult to extract from a system running the
vendor's firmware.

viatool also preserves inteltool's MSR dumps. VIA CPU and Intel CPU MSRs are
nearly identical.

Change-Id: Icbd39eaf7c7da5568732d77dbf2aed135f835754
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/1430
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 22:36:26 +02:00
Ronald G. Minnich a296ce75e3 Move the MARK_GRAPHICS_MEM_WRCOMB to x86 architecture
The MARK_GRAPHICS_MEM_WRCOMB was spreading like a cancer
since it was defined in sandybridge. It is really
more of an x86 thing however, and we now have
three systems that can use it.

I considered making this more general, since it technically
can apply to PTE-based systems like ARM, and maybe we should.
But the 'WRCOMB' moniker is usually closely tied to the x86.

Change-Id: I3eb6eb2113843643348a5e18e78c53d113899ff8
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/3349
Tested-by: build bot (Jenkins)
2013-06-04 22:36:03 +02:00
Denis 'GNUtoo' Carikli 873965e2a7 Lenovo X60: Add CMOS defaults.
After removing power and the CMOS Battery, putting it back
  and booting coreboot we have:
     # ./nvramtool -a
     boot_option = Fallback
     last_boot = Fallback
     baud_rate = 115200
     debug_level = Spew
     hyper_threading = Enable
     nmi = Enable
     boot_devices = ''
     boot_default = 0x40
     cmos_defaults_loaded = Yes
     lpt = Enable
     volume = 0xff
     tft_brightness = 0xbf
     first_battery = Primary
     bluetooth = Enable

The code for handling the invalid CMOS space in mainboard.c
  is now useless and so it was removed.

Change-Id: Ic57a14eeeea861aa034cb0884795b0152757bf5b
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3335
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-06-04 21:35:56 +02:00
Denis 'GNUtoo' Carikli 649f18f834 Asus M4A785T-M: Add CMOS defaults.
After removing power and the CMOS Battery, putting it back
  and booting coreboot we have:
    # ./nvramtool -a
    boot_option = Fallback
    last_boot = Fallback
    ECC_memory = Enable
    baud_rate = 115200
    hw_scrubber = Enable
    interleave_chip_selects = Enable
    max_mem_clock = 400Mhz
    multi_core = Enable
    power_on_after_fail = Disable
    debug_level = Spew
    boot_first = HDD
    boot_second = Fallback_Floppy
    boot_third = Fallback_Network
    boot_index = 0xf
    boot_countdown = 0xc
    slow_cpu = off
    nmi = Enable
    iommu = Enable
    nvramtool: Can not read coreboot parameter user_data because layout info specifies CMOS area that is too wide.
    nvramtool: Warning: Coreboot CMOS checksum is bad.

Change-Id: Idea03b9bc75c5c34c7ce521ce5e5a1c1bb6dfa96
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3324
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-06-04 21:34:52 +02:00
Denis 'GNUtoo' Carikli 03c66202de PC Engines ALIX.1C: Add CMOS defaults.
After Booting the BIOS, flashing coreboot
  and booting coreboot with that patch we have:
    # ./nvramtool -a
    boot_option = Fallback
    last_boot = Fallback
    ECC_memory = Disable
    baud_rate = 115200
    power_on_after_fail = Disable
    debug_level = Spew
    boot_first = HDD
    boot_second = Fallback_Floppy
    boot_third = Fallback_Network
    boot_index = 0xf
    boot_countdown = 0x7f
    nvramtool: Warning: Coreboot CMOS checksum is bad.

Change-Id: Ia87b09003d859f6dee7c09aa963df002c1d02688
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3323
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-06-04 21:31:57 +02:00
Alexandru Gagniuc fcf2a17a86 pci_ids.h: Add PCI IDs for VIA VX900 chipset
Change-Id: I4a75326fef0a10a6290cdd4b1b93d9af8e3ab23d
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/3268
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
2013-06-04 21:21:05 +02:00
Nico Huber e25984b8c8 superiotool: Add dump facility for HWM of W83627DHG-P
Change-Id: I9355996a8cf1b7cb91cc415ec04f5108a1cc42a5
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3358
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-04 21:14:55 +02:00
Nico Huber 28a1324303 superiotool: Add dump facility for ITE IT8516 + I/O 0x20e/f
Change-Id: Iaea08b7eb5aac9ff1e0756f1400a82641bb45b14
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3359
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-04 21:14:44 +02:00
Nico Huber 5d1edf6276 libpayload: Whitelist Mobile Panther Point AHCI controller
Add the Mobile Panther Point (PPT) AHCI controller (DEVID 0x1e03) to
the list of tested controllers. Also comment the only other listed
controller (Mobile ICH9).

The PPT AHCI controller was tested with a QM77 chipset on a Kontron
KTQM77 board.

Change-Id: Ia396761411f4f9289af11ec8e1b144512b2fc126
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3361
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-04 21:14:32 +02:00
Patrick Georgi ce809b9c3a fix tinycurses
Change-Id: I9e7bde7b2c90b8b34c6aa8e90a16cd29dc108fe9
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/3360
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-04 21:13:08 +02:00
Alexandru Gagniuc 359501a7b7 coreboot: Add generic early SMBus API
Early SMBUS code with similar functionality is duplicated for all
southbridges. Add a generic SMBus API (function declarations) designed to
unify the early SMBus structure.

This patch only adds the API. It does not implement any hardware-specific
bits.

Change-Id: I0861b7a3f098115182ae6de9f016dd671c500bad
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/143
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 18:39:06 +02:00
Alexandru Gagniuc 78706fd61f DDR3: Add utilities for creating MRS commands
MRS commands are used to tell the DRAM chip what timing and what
termination and drive strength to use, along with other parameters.
The MRS commands are defined by the DDR3 specification [1]. This
makes MRS commands hardware-independent.

MRS command creation is duplicated in various shapes and forms in any
chipset that does DDR3. This is an effort to create a generic MRS API
that can be used with any chipset.

This is used in the VX900 branch.

[1] www.jedec.org/sites/default/files/docs/JESD79-3E.pdf

Change-Id: Ia8bb593e3e28a5923a866042327243d798c3b793
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/3354
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 18:37:53 +02:00
Alexandru Gagniuc 775551c69e VIA Nano: Add microcode updates files
While we had support for updating microcode on the VIA Nano CPUs for a
while now, we never included the actual microcode. Unlike, Intel and
AMD CPUs, VIA microcode is not available for download, and was
extracted from the vendor BIOS. It was not included in coreboot since
we never had explicit permission to do so. I have just received
confirmation from VIA that we can distribute the microcode.

Change-Id: I4c15b090cd2713cfe5dc6b50db777ff89dbc0f19
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/3357
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-06-04 18:02:11 +02:00
Christian Gmeiner 7bc3575458 AMD Northbridge LX: get rid of #include "northbridge/amd/lx/raminit.c"
Change-Id: I249c63646267ebe8dd8e06980aa6367a16fe7297
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3370
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 17:56:48 +02:00
Christian Gmeiner c4e07bb503 AMD Northbridge LX: convert spd_read_byte() to non-static version
Change-Id: Ie329606852dfd7109acb694e9a9ff851b023cc63
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3369
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 17:56:35 +02:00
Christian Gmeiner 4eb5aa2894 AMD Northbridge LX: move #include "northbridge/amd/lx/raminit.h"
Move the include before static inline int spd_read_byte().

Change-Id: I4cac4b1f55368041b067422d95c09208e15d0f2d
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3368
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 17:56:03 +02:00
Christian Gmeiner e2dc80ceac AMD Northbridge LX: rename get_systop() to get_top_of_ram()
Change-Id: I6126d575b8289f76b38858304836e3037200bcdb
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3367
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 17:55:45 +02:00
Christian Gmeiner 84ae76caf8 AMD Northbridge LX: include northbridge.h in raminit.c
Change-Id: Ic2f50ae184678637c611757d3391826c1d2719a1
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3365
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 17:55:15 +02:00
Christian Gmeiner 194ec4d4d5 AMD Northbridge LX: make GeodeLinkSpeed() function prototype non-static
Change-Id: Id914be1ae4dac96c51f2640f056af4ce58a248eb
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3364
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 17:54:56 +02:00
Christian Gmeiner 6f9f785d9b AMD Northbridge LX: add some missing includes
This commit fixes problems if we build raminit.c
for romstage.

Change-Id: Ic1380f3635ac28b939fa2a8ce614814012455c44
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3363
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 17:54:27 +02:00
Christian Gmeiner eb6322f4b0 AMD Northbridge LX: make sdram_* function prototypes non-static
In order to get rid of the bad #include "northbridge/amd/lx/raminit.c"
line we need to do some prepartion steps. This commit is one of them.

Change-Id: I33173660bbda8894e7672e41e1b994d254d7ae8a
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3362
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 17:53:57 +02:00
Siyuan Wang 29840e234c AMD Fam 15tn: Use all memory on systems with more than 4 GB
Take a Parmer board with 4G memory as an example.

Use 'cat /proc/meminfo' to check memory, it reads 'MemTotal 3327540kB'.
Parmer uses 512M as video memory when it has 4G.
3327540+512*1024 = 3851828(kB), so some memory is lost.

When Parmer has 4G memory, TOM2 low is 0x1F000000, TOM2 high is
0x00000001. But in e820 table or coreboot table, the last item is

    6: 0000000100000000 - 0000000118000000 = 1 RAM

This is not correct, it should be

    6: 0000000100000000 - 000000011f000000 = 1 RAM

This patch changes the memory layout when TOM2 is set.

Change-Id: I4e2d163ae8fe1e65ddc384b520a5112ca067b1d1
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3366
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 17:48:47 +02:00
David Hubbard 5b0420a87b crossgcc/buildgcc: Remove unneeded 'break' statements
Bash case statements are terminated with ';;'.

Unlike C, bash case statements will not continue to the next case. No 'break' is needed.

Change-Id: I62e7e91f3223ac4052728a1ca12a4681af0dc036
Signed-off-by: David Hubbard <david.c.hubbard+coreboot@gmail.com>
Reviewed-on: http://review.coreboot.org/3330
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-04 01:15:20 +02:00
Alexandru Gagniuc f97ff3f72c dram: Add utilities for decoding DDR3 SPDs
Add convenience utilities for decoding DDR3 SPDs and printing the
information to the console. These have proven invaluable when writing the
VX900 memory initialization.

These are used in the VX900 branch

Information printed has the following format:

> SPD Data for DIMM 51
>   Revision: 10
>   Type    : b
>   Key     : 2
>   Banks   : 8
>   Capacity: 1 Gb
>   Supported voltages: 1.5V
>   SDRAM width       : 8
>   Bus extension     : 0 bits
>   Bus width         : 64
>   Optional features : DLL-Off_mode RZQ/7 RZQ/6
>   Thermal features  : ASR ext_temp_range
>   Thermal sensor    : no
>   Standard SDRAM    : no
>   Row    addr bits  : 13
>   Column addr bits  : 10
>   Number of ranks   : 1
>   DIMM Capacity     : 1024 MB
>   CAS latencies     : 6 7 8 9
>   tCKmin            :   1.500 ns
>   tAAmin            :  13.125 ns
>   tWRmin            :  15.000 ns
>   tRCDmin           :  13.125 ns
>   tRRDmin           :   6.000 ns
>   tRPmin            :  13.125 ns
>   tRASmin           :  36.000 ns
>   tRCmin            :  49.125 ns
>   tRFCmin           : 110.000 ns
>   tWTRmin           :   7.500 ns
>   tRTPmin           :   7.500 ns
>   tFAWmin           :  30.000 ns

Change-Id: I30725a75caf74ac637db0a143344562bd9910466
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/3267
Tested-by: build bot (Jenkins)
2013-06-03 22:35:37 +02:00
Alexandru Gagniuc 32610462d1 spd.h: Add all known SPD_MEMORY_TYPE definitions.
This file was missing some definitions, so add them. Also turn the defines
into an enum. The reason for doing this is that functions can now
explicitly take an spd_memory_type as a parameter:

> int do_something_with_dram(enum spd_memory_type type, ...)

Which is a lot more explicit and readable than:

> int do_something_with_dram(u8 type, ...)

These are used in the VX900 branch.

Change-Id: Ic7871e82c2523a94eac8e07979a8e34e0b459b46
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/3266
Tested-by: build bot (Jenkins)
2013-06-03 22:35:21 +02:00