Use the verbatim variable method to define and export test code and
the actual libpci test from flashrom. This improves readability and
will work with stricter compiler (settings).
Change-Id: Iace7d53b0b992c4fde596ce1d606ad715d6dfc2a
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/1575
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
- Separate host bridges/DRAM controllers from LPC controllers in supported_chips_list[].
- Refine some names and macros.
- Clean up some whitespace errors.
- Add IDs and names of 5, 6 and 7 Series southbridges and the three
latest Core CPU families with integrated memory controllers but do
not implement any pretty printing routines for them yet.
The first generation Core family is already supported, although it
was wrongly named after the PCH and used the wrong ID. Also, the BAR
values have been mangled to 32b instead of 64b. Both errors have been
fixed and most basic support for the other two generations was added.
Change-Id: Ief81e57f7c065cafac52e48b6364b57c72fcdf95
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/1574
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
&> is a bashism to redirect both outward streams (stdout and stderr), but
with other shells this introduces a race condition with the rm command
after it, because the compiler execution is done in the background/
in parallel. Found and tested with dash.
Change-Id: I08516494828c9f7af168f954f2df027372657867
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/1573
Tested-by: build bot (Jenkins)
Reviewed-by: Bernhard Urban <lewurm@gmail.com>
Reviewed-by: Peter Stuge <peter@stuge.se>
For BSD, patch and tar are not default GNU. Add a work around
to let the non-gun patch and tar work.
Change-Id: I0a9d0bb0e535aa5e0dde146db330c3c8d7b4d8cb
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1502
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Instead of having the highlevel functions make use of the lowlevel
functions, it implemented the lowlevel stuff in terms of highlevel.
Change-Id: I530bfe3cbc6f57a6294d86fbf1739e06467a2318
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1539
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The used FPGA on the device triggers PIRQD for the membrane
keyboard. The used linux driver for the keyboard uses the fixed
IRQ number of 7. In order not to touch the linux driver and be
compatible with proprietary BIOS change the irq_table in
coreboot.
Change-Id: If5bc929eb48bb1eafd401941ebb7d34cf5862c35
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/1571
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
HPET's min ticks (minimum time between events to avoid
losing interrupts) is chipset specific, so move it to
Kconfig.
Via also has a special base address, so move it as well.
Apart from these (and the base address was already #defined),
the table is very uniform.
Change-Id: I848a2e2b0b16021c7ee5ba99097fa6a5886c3286
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1562
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
This enables building with dash again(?) by using exactly one patch of
SeaBIOS more/newer than previously, which has also the sole purpose of
removing bashism and is a single line change. *sigh*
Change-Id: Ib036894d8b9886f74d6eb0853f1fc0ce1aa39d54
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: http://review.coreboot.org/1568
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
Forcing this rule, chip_ops can be added in the static devicetree
regardless of the existence of the chip.h files.
Change-Id: Iec1c23484e85cab3f80a34f2b082088f38ac4de9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1472
Tested-by: build bot (Jenkins)
Also deletes files not included in build:
src/southbridge/amd/cimx/sb700/chip_name.c
src/southbridge/amd/cimx/sb800/chip_name.c
src/southbridge/amd/cimx/sb900/chip_name.c
Change-Id: I2068e3859157b758ccea0ca91fa47d09a8639361
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1473
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Before change "Simplify VGA card discovery"
(http://review.coreboot.org/#/c/1255/)
coreboot was setting up VGA for the last found VGA device.
After this change it setting up VGA for the first found.
This change broke compatibility to my Supermicro H8QGI board.
Revert order back to old to save compatibility for this board
(and maybe any other boards)
Change-Id: Id5f2be60f95298059651c26133806e2694ff60aa
Signed-off-by: Kostr <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/1561
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
According to file "northbridge.c" in family 15h code
IO-HUB should be placed on link_lsit[0] in devicetree.cb.
This hack in "northbridge.c" was made to satisfy both f10 and f15 cpu's.
Change-Id: I4754235bd38239460347b0dc4a82cd4e58ae7cd0
Signed-off-by: Kostr <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/1540
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
The classes in $(top)/Makefile uses $(abspath) to get the path.
The $(abspath) can not resolve symlink. If the coreboot is located
in a symlink directory, the run_printall produces the absolute
path while the $PWD just produces the path with symlink. Use
`pwd -P` to get the abs path.
Change-Id: Icf6b364d030c14a9c78991767b17dafc701baf3c
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1551
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This is in preparation for sharing interrupt handlers
between YABEL and x86emu.
Change-Id: Iff92c1d899b8ada20972731944341805a49b6326
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1560
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The previous commit provides a mainboard_interrupt_handlers
implementation YABEL with identical semantics to the
x86emu one, so let's use it in both cases.
This eliminates the need for the int15_install()
indirection, so let's drop that, too.
Generated using the following coccinelle patch and
manual cleanups (empty #if/#endif):
@@
type T;
identifier FUNCARR;
expression INT, HANDLER;
@@
-typedef T yabel_handleIntFunc;
-extern yabel_handleIntFunc FUNCARR[256];
-FUNCARR[INT] = HANDLER;
+mainboard_interrupt_handlers(INT, &HANDLER);
@@
@@
-void int15_install(void)
-{
-mainboard_interrupt_handlers(0x15, &int15_handler);
-}
@@
@@
-void int15_install(void)
-{
-mainboard_interrupt_handlers(0x15, &int15_handler); ... mainboard_interrupt_handlers(0x15, &int15_handler);
-}
@@
@@
-int15_install();
+mainboard_interrupt_handlers(0x15, &int15_handler);
Change-Id: I70fd780d7ebf1564a2ff7d7148411673f6de113c
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1559
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Provide (mostly) the same API for registering
interrupt handlers as with x86emu.
Change-Id: I1364b08d9043039550786a1758508ae088813aa3
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1558
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
our code supports tyan s8226 now, which has two cpus on the board
the cpu socket is C32. The details of tyan s8226 is:
http://www.tyan.com/product_SKU_spec.aspx?ProductType=MB&pid=679&SKU=600000190
the test result of this mainboard is:
1) boot Ubunbu 11.10, kernel 3.0.9. there is no err and warnings in
dmesg.
2) boot windows7 x64 successfully.
3) use fwts to test the bios, there are 268 pass and 14 failed
4) pcie and usb slots are ok.
5) all network interfaces are ok.
Change-Id: I7d8534f20b4f3c16322a5c5ba2e3fba4b4f3e608
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/1495
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
After make 3.81 is copied to /usr/local/bin, the old make 3.80, which
doesn't work for coreboot, will replace $MAKE with gnumake. That is not
we want.
Change-Id: I87fbe95c70228a22f2c233ff071df29639b63726
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1550
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
pirq_routing_irqs assumed that only four links are available for PIRQ
routing, INTA to INTD. Some chipsets provide more, up to INTH.
When pirq_routing_irqs found a link number greater than 4 in the pirq table,
it would not assign that IRQ. This is a shame, as it limits the flexibility
of routing IRQs.
Make the maximum number of links a Kconfig variable, and modify the code to
respect it. This works beatifully on the VX900, which provides 8 routable
interrupts.
While we're at it, also refactor pirq_routing_irqs, and add some much
needed comments.
Rename pirq_routing_irqs to pirq_route_irqs to demistify the role of this
function.
The copyrights added were determined from git log filename.
Change-Id: I4b565315404c65b871406f616474e2cc9e6e013e
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/1482
Tested-by: build bot (Jenkins)
Previously we assume that hardware using 8 bits
per char by default, but on Asrock A53 Pro
this is not true (7 bit per char by default).
Forcing use 8n1 now.
Change-Id: Ib701725d2ec6dacd7862016b2045270956b27029
Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-on: http://review.coreboot.org/1541
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Makefile still used SVNDEF on FreeBSD.
Change-Id: I45c7fbc66c33e82a2146ef7df87b63bc7edea4cd
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1554
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
The handling of finalize in uhci_bulk was confusing, and so its
behaviour changed.
If set, the driver is supposed to add a trailing empty packet iff
the last packet is of maximum packet size. This helps the device to
decide if the transfer is completed simply by waiting for a packet
that isn't full length.
Change-Id: I162e8c1e034924d0de6fdcb971c94cf3a5ea31eb
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1555
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
In some cases we request mktemp to create a temporary file in
$(obj)/mainboard/... before it exists.
Let's make sure the directory exists
Change-Id: I51f0065c30b1f25eb501a6fd5edefb3f4c15d0ab
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1532
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Without that fix we have:
CC boot/hardwaremain.ramstage.o
src/boot/hardwaremain.c: In function 'hardwaremain':
src/boot/hardwaremain.c:136:6: error: 'cbmem_post_handling' undeclared (first use in this function)
src/boot/hardwaremain.c:136:6: note: each undeclared identifier is reported only once for each function it appears in
src/boot/hardwaremain.c:137:3: error: implicit declaration of function 'cbmem_post_handling' [-Werror=implicit-function-declaration]
cc1: all warnings being treated as errors
make: *** [build/boot/hardwaremain.ramstage.o] Error 1
When compiling without CONFIG_WRITE_HIGH_TABLES
Change-Id: Ie45f684a6db0ab55ef469bfcef57e539ae7e994c
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/1533
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Fixed masking to run QH shedule.
Fixed final zero filled TD generation for
UHCI bulk transaction.
Change-Id: I9c6ea34d132368922f2eeeaa7aadbbb6aac3e2b8
Signed-off-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-on: http://review.coreboot.org/1553
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
Cygwin's hostname comes from coreutils, which does not support all
the options that some other hostname implementations provide.
Change-Id: Ia6bd9157c351f440ad225046638a6bf3f9cfba11
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1546
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
see the Netbsd manual:
http://netbsd.gw.com/cgi-bin/man-cgi?uname++NetBSD-current
Error output needs to be redirected.
Change-Id: I1853a0162e14be0ee9d7971466499af6c72b2427
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1545
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The Makefile.inc is integraged into coreboot Makefile. It doesn't
need to access to HW like cmos. It doesn't include cmos-hw-unix.c,
which is only for individual tools running seperatedly.
Change-Id: Ib00b5c3da63acb4120cb23eb7d661c5bc75d7c86
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1544
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Some 32 bit machines print integer higher than 0x80000000
as negative number.
Change-Id: Ieb512ed2a7499ce7e91e45e4075d4f119780b57d
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1547
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Change-Id: I86cecf6aee1fcb682cb32bd0f03e014fd1afe594
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1549
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
For some reason the rm -f didn't quite work on my system,
but sending gcc output to /dev/null does.
Change-Id: I7ece9aa9abe564bbc646ae53df1d3cd0c5aa84a2
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1543
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
libpayload already contained a number of functions for convenient
access to CMOS configuration. Add functions to support iteration
over available enum fields.
Change-Id: If95f45d7223d2e19c42f1d8680c12d23f6890a01
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1538
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
... but no-one told intel/sch.
Change-Id: I68eaae6910bd6fc579c35b5bc038b9597cd1b3e7
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1537
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
With this chance it becomes practical to have payload.sh build/update
the payload, and abort abuild if something bad happened.
Change-Id: Iee25de2e8b62153c477b8e5d32e097b59797523c
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1536
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Only relevant on windows (and nvramtool currently fails there), but
it doesn't hurt.
Change-Id: I5d6420c1f9dc49cf3af31e75088e51a90f729e01
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1535
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Try
sh> printf %d 0x005500AA | LC_ALL=C awk '{printf("%c%c%c%c", \
$1 % 256, $1/256 % 256, $1/65536 % 256, $1/16777216);}' | \
od -Ax -t x
On Linux with gawk, we get
000000 005500aa
000004
On FreeBSD with nongnu-awk, we get
000000 000055aa
000002
In awk, all the numbers are floating point number. So division doesn't
round the result from 0.75 (3/4) to 0.
And, There is a fact that, for the FreeBSD awk,
sh> awk 'BEGIN {printf("%c", 0.75)}';
produces nothing, instead of 0.
Here we need to convert the floating point number to
integer by int(X), which is an awk built-in function, instead of GNU
extension.
Change-Id: I3470d5f13e7ea59a978d5575a54c0d56368dc78d
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1529
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
We used sizeof(listp*) at a place where sizeof(listp) is more appropriate:
While these are pointers, they're part of the UHCI design, and don't depend
on ISA details.
Change-Id: I4d3cb571c9a407103bc81fc171a8e73b68f7c7a1
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1530
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Change-Id: I6a7852eef32a3440c9d29e45420cb21d2db8c404
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1528
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
TRACE has redefined warnings in src/southbridge/amd/cimx/sb700/Platform.h,
so we do some changes to remove such warnings.
Change-Id: I24979e08b83434f91a8fa37cd9f16303fa0b298d
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/1499
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Currently the C32 has some legacy boards which use the old C32 code. We need to seperate them.
CONFIG_CPU_AMD_SOCKET_C32 was used in legacy code before.
But it is not a good idea, so we change the code as follows:
So we use CONFIG_CPU_AMD_SOCKET_C32 to identify mainboard which uses agesa code,
and use CONFIG_CPU_AMD_SOCKET_C32_NON_AGESA to identify mainboard which uses legacy code.
Change-Id: If6114bf8912e78b7732f25a1adfb2e4d8eb10ee4
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/1497
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Command expr in some systems only take 32bit as integer, which
value is at 0x7FFFFFFF ~ -0x80000000. Use awk as alternate way to
calculate.
And some system doesnt take hex value in Makefile, even in awk instruction.
Change-Id: Ie35d6a5b96eea4192bd9cab857af4d4dcb37b9ed
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1527
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Stefan Tauner