Commit graph

6 commits

Author SHA1 Message Date
Kyösti Mälkki
a0b4a8d819 ACPI: Remove CBMEM TOC from GNVS
This existed for ChromeOS but was no longer used with DYNAMIC_CBMEM.

Change-Id: I558a7ae333e5874670206e20a147dd6598a3a5e7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6032
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-06-18 20:37:34 +02:00
Duncan Laurie
38109d558a SMM: Save the GNVS pointer when creating APCI tables
At boot time when the ACPI tables are created and the location
of GNVS is determined then save that address for resume time.

This also sets the values of USB charging in S3/S5 to the expected
default values for Stout/Butterfly that were not set correctly.

Change-Id: I9b94b868aa6e81aced06c0262cc2697ad4faf1e6
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1768
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14 05:45:00 +01:00
Patrick Georgi
9aeb69447d hpet: common ACPI generation
HPET's min ticks (minimum time between events to avoid
losing interrupts) is chipset specific, so move it to
Kconfig.

Via also has a special base address, so move it as well.

Apart from these (and the base address was already #defined),
the table is very uniform.

Change-Id: I848a2e2b0b16021c7ee5ba99097fa6a5886c3286
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1562
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2012-10-08 21:23:08 +02:00
Stefan Reinauer
a306ad701e ChromeOS: Remove board specific acpi_get_vdat_info()
The function acpi_get_vdat_info() was moved to the ChromeOS
vendor code, and is no longer required to be present for each
board. Hence, remove it.

Change-Id: I3dc8dbb6119ceffa057373bad7c0058ac0d40eb8
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1283
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-24 23:17:56 +02:00
Stefan Reinauer
e6063fee5c Fix Sandybridge/Ivybridge mainboards according to code review
This fixes a few cosmetics with the following three boards:

 - Intel Emerald Lake 2
 - Samsung ChromeBook
 - Samsung ChromeBox

The following issues were fixed:

 - rely on include path in ASL code instead of specifying relative
   paths
 - use updated ALIGN_CURRENT in acpi_tables.c
 - use preprocessor defines instead of hard coded values where possible

Change-Id: Ia5941be3873aa84c30c13ff2f0428d1c52daa563
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/963
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
2012-05-01 19:27:34 +02:00
Stefan Reinauer
e1ae4b212f Add support for Sandybridge base Samsung ChromeBox
Change-Id: Ic93ad2749834c8f7a2ca1651d343561f2a496312
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/953
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-30 23:09:26 +02:00