Commit Graph

35228 Commits

Author SHA1 Message Date
Angel Pons 26766fd85d nb/intel/pineview: Use PCI bitwise ops
Tested with BUILD_TIMELESS=1, Foxconn D41S does not change.

Change-Id: Idd6a11e95669f0a8fe9bd52359a9822b524c878c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42192
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10 01:52:51 +00:00
Zheng Bao a4098c759d amd/common: Add the macro definition for patch level MSR
This MSR is used for detecting if the micro code is applied
successfully.

Change-Id: I060eb1a31f3358341ac0d5b9105e710c351f2ce8
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42212
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10 01:49:42 +00:00
Kyösti Mälkki 56da63c3dc sb,soc/amd, ACPI: Do not override FADT preferred_pm_profile
Setting preferred_pm_profile under sb/ or soc/ overrides the
default determined from SYSTEM_TYPE_xx (or possibly
SMBIOS_ENCLOSURE_TYPE with followup work). This is not desireable.

With the overrides removed, AMD platforms will switch from
PM_UNSPECIFIED to PM_DESKTOP as their preferred profile.

Boards need to either select a pre-defined SYSTEM_TYPE_xx or provide
board-specific mainboard_fill_fadt() should they need to change this.

As they already select SYSTEM_TYPE_LAPTOP, following boards
will change to PM_MOBILE:

  google/kahlee
  hp/pavilion_m6_1035dx
  lenovo/g505s

Change-Id: I45c4a495a4bf3422adae9e22a6e436adef252e77
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-06-10 01:20:13 +00:00
Kyösti Mälkki ab516294a5 sb/amd/agesa,cimx,pi: Select COMMON_FADT
Change-Id: Ib6a0f8a3beb3d02dfd90234b1af6eccd3cde21bb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41924
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10 01:17:49 +00:00
Kyösti Mälkki 61ef71bcb2 soc/amd/stoneyridge,picasso: Select COMMON_FADT
Change-Id: I0c98bf7f88c33691401ebc6b174d959dd515dd11
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41921
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10 01:14:53 +00:00
Kyösti Mälkki 55c0c4bc86 mb,sb/amd/cimx/sb800: Remove FADT_PM_PROFILE
The platform_cfg.h files under mainboard/ are a legacy configuration
mechanism used with AGESA family14 boards.

With this change following boards will have FADT preferred_pm_profile
changed from PM_UNSPECIFIED to PM_DESKTOP:

  amd/inaqua
  amd/south_station
  amd/union_station
  asrock/e350m1

Change-Id: Ic28761eb238dbbaf3e8f820a29ec64b89f12bf53
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-06-10 01:08:24 +00:00
Kyösti Mälkki 4a09b97cad sb,soc/amd: Remove FADT_PM_PROFILE
This was copy-paste from fam14 configuration mechanism
using platform_cfg.h files.

Change-Id: I7fdd89a8b1fe9c7e558841e24fb832d0cffd3454
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42030
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10 01:06:53 +00:00
Kyösti Mälkki ba17829de4 sb/intel, ACPI: Do not override FADT preferred_pm_profile
Setting preferred_pm_profile under sb/ overrides the
default determined from SYSTEM_TYPE_xx (or possibly
SMBIOS_ENCLOSURE_TYPE with followup work). This is not desireable.

Boards need to either select a pre-defined SYSTEM_TYPE_xx or provide
board-specific mainboard_fill_fadt() should they need to change this.

As they already select SYSTEM_TYPE_LAPTOP, following boards
will maintain PM_MOBILE:

  lenovo/t400
  lenovo/x200
  roda/rk9

Following will change to PM_DESKTOP:

  aopen/dxplplusu
  asus/p2b
  emulation/qemu-i440fx
  emulation/qemu-q35

Change-Id: I2986eb0a8abc94507e9797cc8b64611ae4bd888a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-06-10 01:03:05 +00:00
Kyösti Mälkki 64e07ebde2 sb/intel/i82801ix: Select COMMON_FADT
Change-Id: Iffdce450b1d4c9984ec5efe11eff62bf9184e314
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41922
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10 01:01:32 +00:00
Kyösti Mälkki 8ad52fff64 sb/intel/i82371eb: Select COMMON_FADT
Change-Id: I0b1f3e16b2a801e5fcf5f96d59922f6231d73636
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41925
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10 01:00:54 +00:00
Kyösti Mälkki df63ff8b55 aopen/dxplplusu,intel/i82801dx: Select COMMON_FADT
Move existing fadt.c file under southbridge.

Change-Id: Ie2fdc715e4d1af347d25b51e83189f28cd9af014
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41923
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-10 01:00:11 +00:00
Felix Held e5f4b2f39d soc/amd/picasso/acpi/sb_fch: use local variable in _CRS methods
Use a local variable for the ResourceTemplate in the _CRS methods
instead of the RBUF object. When using RBUF, iasl complained that the
_CRS methods need to be serialized, since objects were created in there.
Since those are only used as local variables, just use local variables
for this.

TEST=iasl stops complaining about those methods not being serialized and
Linux still boots and there aren't any related ACPI errors or warnings.

Change-Id: Ic43fcaed5a8b19dbd5634c17f34a159803ba8577
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-09 22:23:16 +00:00
Nick Vaccaro 2bcf4565c7 mb/google/volteer: move volteer-specific GPIOs to variant gpio.c
- Move the GPIOs that are likely to be volteer-specific (mostly
peripherals) to reside in variants/volteer/gpio.c so that
variants don't have to override too many GPIO settings.

- Modify malefor's gpio.c to adjust for the changes to baseboard's
gpio.c.

- Remove unused GPP_C3 (USB4_SMB_SCL) and GPP_C4 (USB4_SMB_SCA)
settings.

- Remove unused GPP_D9, GPP_D10, GPP_D11, and GPP_D12 settings.

- Remove unused GPP_E8 (SLP_S0IX), COEX, WWAN, and SNDW related
  settings for malefor.

- Remove unused GPP_R4 (HDA_RST_L) setting.

BUG=b:157597158
TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot
volteer SKU4 to kernel.

Change-Id: Ib2f384f539d55a3a8d4a7608336ef22aca3d8c4f
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-06-09 21:30:34 +00:00
John Zhao 92a3a304af soc/intel/tigerlake: Set FSPS UPD ITbtConnectTopologyTimeoutInMs
The Connect Topology Command(CNTP) is sent with default timeout value
(0x1388) along with FW CM. The CNTP is supposed to be skipped while
using SW CM. While transition from FW CM to SW CM, the default timeout
value could cause boot time delay up to ~10 seconds. Set this FSPS UPD
ITbtConnectTopologyTimeoutInMs to be 0 in order to avoid the 10 seconds
delay. Future FSP release will evaluate this ITbtConnectTopologyTimeoutInMs
value. While FSP finds this UPD value being 0, FSP will skip sending CNTP.

BUG=b:155893566
TEST=Built image with SW CM Thunderbolt firmware and verified no
outstanding delay time while using FSP v3197 during boot to kernel.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I47e3519fd818cb56e6abd16464d8370ffddabc5b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42056
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-09 18:43:57 +00:00
Srinidhi N Kaushik 6d81eceb74 vendorcode/intel/fsp: Update Tiger Lake FSP Headers for v3197
Update FSP headers for Tiger Lake platform generated based FSP
version 3197 to include below additional UPD:

FSPS:
ITbtConnectTopologyTimeoutInMs

Signed-off-by: John Zhao <john.zhao@intel.com>
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I06d605b156c1e6f90921c20e0b8fbbe4d64916ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42046
Reviewed-by: Divya Sasidharan <divya.s.sasidharan@intel.corp-partner.google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-09 18:43:26 +00:00
Kyösti Mälkki d4acee887e ACPI: Move redundant FADT reserved entry
Change-Id: I35f66cdad6b8bedf4337aa8e5af7b0f1b53fe674
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42033
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-09 17:53:50 +00:00
Angel Pons 4a9569a123 nb/intel/x4x: Use PCI bitwise ops
Tested with BUILD_TIMELESS=1, Intel DG43GT does not change.

Change-Id: I1bb7a7fd808cbbb45efbbfb9581c6a948323a48f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42155
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-09 17:52:29 +00:00
Angel Pons 26886076f4 nb/intel/haswell: Use PCI bitwise ops
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change.

Change-Id: I99379299f7e744a3e906bdbc46d55060d9c75d6a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42153
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-09 17:50:55 +00:00
Duncan Laurie aab226cc83 soc/intel/tigerlake: Increase heap size
With SoundWire and USB4 enabled some boards are running out of
memory with all of the ACPI devices and properties.  Increase
the heap size to accommodate.

BUG=b:147462631
TEST=Successfully boot on volteer SKU5 board with SoundWire enabled,
before boot was failing with "Error! memalign: Out of memory"

Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I0245bdfad93b381871514578e66640e7fe6fa5c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-06-09 16:29:23 +00:00
Gaggery Tsai 342a8c3b2b mb/google/hatch/vr/puff: Set up PL2 and PsysPL2
This patch adds correct PL2 baseline setting and PsysPL2 for different
SKUs. There is no way to identify the barral jack power rating, the
assumption is following that ships with the product:
1. i3/i5/i7: 90W BJ
2. Celeron/Pentium: 65W BJ

For Type-C adapter, we don't have Pcritcial (10ms) data, keeps the
original settings as 90% of adapter rating for PsyspL2/PL4 and PL2
as min(PL2, 0.9n) where n is adapter rating power.

BUG=b:143246320
TEST=Run with U62 and Celeron CPU and ensure the PL2 settings are correct

Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Change-Id: If7de614d58366158a566563990ee1ecc8c0110bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-06-09 06:30:40 +00:00
Kyösti Mälkki be242788c2 SMBIOS: Remove Kconfig SYSTEM_ENCLOSURE_TYPE
This gets rid of the magic numbers in Kconfig.

Change-Id: Ibee033b6c99e3131bb323f0d86d306dcd82f9b45
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-06-09 06:29:59 +00:00
Kyösti Mälkki 8770954b99 mb/scaleway/tagada: Move override of SMBIOS_ENCLOSURE_TYPE
Change-Id: Iaefeccadb82106667a5108a2c77e538474ae18c2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-06-09 06:29:31 +00:00
Nico Huber e9e13d41e9 Revert "sb/amd/cimx/sb800: Fix 16-bit read/write PCI_COMMAND register"
This reverts commit 04506e2987.

Turned out that `dev->command` is only a `u8` and the way it's used
here is wrong: It is not supposed to reflect the state of the register
but only gathers (lower) bits to be enabled during allocation.

Change-Id: Iacd2b753939e8adcf5aedd4b9cf101638a324aa6
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42163
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-09 06:28:47 +00:00
Angel Pons 45aea0b1d0 mb/google/poppy: Add retail names
Taken from Chrome OS update information. Looks like nami encompasses
many different devices, which would not fit in one line, so skip it.

Change-Id: I53405cba269cbfc25bd4618777b946500f173e7e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-06-09 06:26:21 +00:00
Angel Pons 8a50827bea MAINTAINERS: Add myself as some northbridges' maintainer
I've got hardware to test things on these northbridges, and I am quite
familiar with their code.

Change-Id: Ied5adbb8bad94291a1843531be8a0923464d6212
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-06-09 06:24:46 +00:00
Angel Pons 32b9ef35b5 MAINTAINERS: Add myself to x4x and pineview northbridges
Change-Id: I42b1e8670f4e2ddfea7d473421e86649211eae86
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-06-09 06:24:30 +00:00
Angel Pons f2aaddc1eb MAINTAINERS: Add myself as some mainboards' maintainer
I've ported some more mainboards, but forgot to update MAINTAINERS.

Change-Id: I46d2cd3737d584156e8bf49a0d7ab6b0327e0063
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-09 06:24:18 +00:00
Angel Pons 71892b4bec nb/intel/sandybridge: Use MCHBAR bitwise ops
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.

Change-Id: If16d8c4aef3dfd1dbeaf48d6855dd4c0ef328168
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-09 00:33:53 +00:00
Angel Pons 9733f6a336 nb/intel/sandybridge: Use PCI bitwise ops
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.

Change-Id: If7f3f06cd3524790b0ec96121ed0353c89eac595
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-09 00:32:28 +00:00
Angel Pons 8ad0a4c0b8 nb/intel/gm45/iommu.c: Fix regression when updating PCI command
Commit 5ac723e (nb/intel: Fix 16-bit read/write PCI_COMMAND register)
uses `pci_read_config8` to read the PCI command register, which does not
correspond with what has been stated in the commit message. Moreover, it
potentially breaks things, as the upper byte of the PCI command register
is now being cleared.

So, restore the original behaviour of the code, using 16-bit accesses.

Fixes: 5ac723e (nb/intel: Fix 16-bit read/write PCI_COMMAND register)
Change-Id: Id2c42ea8551a2fa2fa5c64e8fff8940d8304fbe0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-09 00:31:54 +00:00
Angel Pons 2f3456a873 pci_ops.h: Turn and/or ops into update wrappers
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.

Change-Id: I2d3779967f357dd380928869c630a1996fdd60ec
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-09 00:26:12 +00:00
Angel Pons af36b29735 include/device/pci_ops.h: Add bitwise AND ops
For the sake of completeness, we should provide these operations.

Change-Id: Ia28af94ec86319c7380d8377f7e24e5cdf55dd9c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42145
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-09 00:23:19 +00:00
Usha P 3e241f54d2 mb/google/dedede: Default spk_en gpio to low
The max98357a_platform_driver will turn on/off the speaker enable gpio
based on use, so configure it low to save power.

BUG=None
TEST=Built dedede and tested speaker playback working.
We are seeing a power saving of ~10mW.

Change-Id: I070679457b06cb82633c1197b893a5d89c8b2cf0
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2020-06-08 21:41:00 +00:00
Aaron Durbin a2c045bd40 soc/amd/picasso: solve MTRRs only from 4GiB and below
Use x86_setup_mtrrs_with_detect_no_above_4gb() to only
solve the MTRR solution for memory up to 4GiB. This assumes
4GiB to TOM2 is marked as writeback in sys_cfg MSR.

BUG=b:155426691

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ib8358b614682f6a97278f3a60b5ada5e607965af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41898
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-08 19:08:11 +00:00
Aaron Durbin e80a1b1690 soc/amd/picasso: remove save/restore MTRRs around FSP-M
AGESA FSP-M implementation is now not updating MTRRs out from
under the caller. As such, remove the save/restore of MTRRs
from the FSP-M call.

BUG=b:155426691

Change-Id: I14f3b18dd373ce17957ef3857920e1c4e2901bbe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-08 19:08:03 +00:00
Aaron Durbin d6161d46ff soc/amd/picasso: establish full early caching memory map
The PSP does the memory training and setting up of MSRs for
TOP_MEM and TOM2. Set caching up for all the DRAM areas:

Enable WB caching for 1MiB->TOP_MEM, 4GiB->TOM2.
Enable WC caching fro 0->1MiB except 0xa0000->0xc0000.

BUG=b:155426691

Change-Id: I83916a220ea4016d4438dd4fb5be82dec5506f80
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-08 19:07:53 +00:00
Martin Roth 9455474f1b util/amdfwtool: Add option for setting PSP/FW shared memory location
This tells the PSP where in main memory to copy the vboot workbuf.

BUG=b:152576063
TEST=Build sharedmem destination into AMDFW, verify shared memory
gets placed at that location.

Signed-off-by: Martin Roth <martin@coreboot.org>
Original-Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Change-Id: Ie1e955e22632ca5cf146ac6eec0407091e81f519
Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2148830
Original-Reviewed-by: Simon Glass <sjg@chromium.org>
Change-Id: Id324403afa6d5a5a65ce4709be31e7f16e038da0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42044
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-08 14:19:24 +00:00
Martin Roth 37305e78fc util/amdfwtool: update to allow building in any location
For the verstage-on-PSP implementation, we need 2 additional copies
of the AMD firmware tables at non-standard locations.  These are
for RW-A & RW-B fmap regions.  This change allows us to build the
AMD firmware tables into those regions.

BUG=b:148767300
TEST=boot with psp_verstage, verify boot location

Signed-off-by: Martin Roth <martin@coreboot.org>
Original-Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Change-Id: I2b591b50e9b179fdfaead46ff93722fa2a155e9c
Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2144534
Original-Reviewed-by: Simon Glass <sjg@chromium.org>
Change-Id: I7f841db8617b953dc671a9c12576145f85263581
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-08 14:08:20 +00:00
Angel Pons e9b27e5527 superio/nuvoton/nct6776: Reflow `pnp_dev_info` array
Each PnP device now fits in a single 96-character line.

With BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: Ice65ce2504877c40962de7c26e01529d53d75c8e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-06-08 12:05:02 +00:00
Daniel Gröber 0d0b2f45f6 spi: Remove non_volatile flag from block protection interface
Only Winbond parts seem to support making status register writes
volatile. So this flag should not be exposed in the generic interface.

Change-Id: Idadb65ffaff0dd7809b18c53086a466122b37c12
Signed-off-by: Daniel Gröber <dxld@darkboxed.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41746
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-08 07:51:18 +00:00
Furquan Shaikh bcb4a77fb1 spd/lp4x: Set manufacturer part name to blank (0x20)
As per JEDEC spec, manufacturer part name should be set to
blank (0x20). This change updates gen_spd.go to set bytes 329-348 as
0x20 and regenerates SPDs for TGL and JSL.

Change-Id: I6af18d89afd7264cec7e54b38e95df83d55aa058
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42023
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-08 06:42:19 +00:00
Tim Wawrzynczak 16ef59e81e ec/google/chromeec: Append connector device to *-switch properties
The orientation, etc. -switch properties are supposed to use the
connector device (underneath the MUX device) that belongs to the port
number in question. This patch finds the CONx device and uses that
to pass to the acpigen API.

BUG=b:154620502
TEST=on Volteer, dump SSDT and verify the *-switch properties point to
\_SB.PCI0.PNC.MUX.CON0 and CON1

Change-Id: Ie65c2d750f3d9f83285e0e4cc9642110c804bbad
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-06-08 06:41:11 +00:00
John Zhao 95b4ece0fe device: Add a disabling PCIe device bus master function
A function pci_dev_disable_bus_master() is created. This function
can be used to disable Thunderbolt PCIe root ports, bridges and
devices for Vt-d based security platform at end of boot service.

BUG=None
TEST=Verified PCIe device bus master enable bit is cleared.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ie92a15bf2c66fdc311098acb81019d4fb7f68313
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-08 06:39:01 +00:00
Maulik V Vaghela aaebfa800c mb/google/dedede: source soc_common_config from variants overridetree
All variants are overriding soc_common_config, so source it from
overridetree and remove entry from baseboard devicetree.
Only keeping chipset lockdown config in baseboard which will be
common across all the variants.

BUG=None
BRANCH=None
TEST=Checked code compilation and lockdown config is applied to all variants

Change-Id: I23714b721a6bb0bac785f046586790a98dc5b646
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2020-06-08 03:43:35 +00:00
Patrick Georgi 4dbe84e432 vendorcode/amd: Remove duplicate assignment
Change-Id: I8a39e862176cd1c8a14424eb6d2bf7edabd36adb
Found-by: Silvio Cesare, https://twitter.com/silviocesare/status/1268784333029965824
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-07 21:56:03 +00:00
Kyösti Mälkki 02fd15dbcf acpi: Rename motherboard_fill_fadt() to mainboard_fill_fadt()
The prefix mainboard_ was used everywhere else.

Change-Id: Ie576fd47301aa484cb1396e0c6f7260b7698af4d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-07 21:53:33 +00:00
Kyösti Mälkki 1edf8b77e0 mb/*: Remove some fadt.c files
Change-Id: I13ed3b6e8608c37c1ebe51838e4052f89a638d83
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41947
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-07 21:53:04 +00:00
Kyösti Mälkki 315710af7b soc/intel/baytrail,braswell,broadwell,quark: Select COMMON_FADT
Some of the boards do not select SYSTEM_TYPE_LAPTOP or _CONVERTIBLE
so their FADT preffered_pm_profile would change from PM_MOBILE without
the added overrides here.

Change-Id: I04b602b2c23fbd163fcd110a44ad25c6be07ab66
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41920
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-07 21:52:37 +00:00
Jonathan Zhang 4b6b2609e5 drivers/mrc_cache: generate debug messages for MRC cache update
When MRC cached data update is performed, messages are written to
event log, which is flash based. For system that does not have flash
based event log, the messages are lost.

Added corresponding BIOS_DEBUG messages.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I1ef4794151fea7213c8317ddc898b0e37da280b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41981
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-07 21:51:32 +00:00
Venkata Krishna Nimmagadda a3e228ce15 soc/intel/tigerlake/acpi: Update gpio_op.asl to ASL2.0 syntax
This change updates gpio_op.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.

BUG=none
BRANCH=none
TEST="BUILD for Volteer"

Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>
Change-Id: Ib54b3f7da828ce8d232fcea0639077970638f610
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-06-07 21:51:01 +00:00