Commit Graph

26759 Commits

Author SHA1 Message Date
Caveh Jalali 41979d862a mb/google/poppy/variants/atlas: enable NVMe
This adds support for a x2 NVMe device on PCIe bus PCIe lines 5+6 and
clock#4.

BUG=b:113369699
TEST=booted on atlas

Change-Id: I08e7c4d65662ddbb7d936915c896eb1fcb240ba8
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/28535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-09-07 23:40:08 +00:00
Patrick Georgi dce4d465a6 util/crossgcc: Tell gcc that it'll use gnu as and ld
Otherwise it reduces its expectations on what as and ld take in terms
of arguments, which breaks some edk2 related builds because tons of
-I$path_to_stuff arguments aren't passed along.

Change-Id: I53f87442de03d5ead8a6632d3102d5502065b828
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-07 19:17:15 +00:00
Richard Spiegel 7160766ebf lib/gpio.c: Fix _gpio_base3_value invalid shift
Coverity CID 1395334: (BAD_SHIFT) - In function _gpio_base3_value(), if
gpio_num is 32 and gpio[31] is floating, the end result is 1 << 32, which
does not fit into a int. To avoid a possible error, make it an error to have
num_gpio > 31. Function _gpio_base2_value also have the same issue, but the
limit would be 32. As in practice it'll never be used with more than 20 GPIO,
create a helper function to limit it to 31 and call it everywhere needed.

BUG=b:113788440
TEST=Add a fake code to southbridge_final calling the function and printing
the result. Build and boot grunt, check result.

Change-Id: I0b79725bcbaf120587c7440e176643aaa7a1d5bb
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28445
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-07 14:53:54 +00:00
Marshall Dawson 653f760b13 amd/stoneyridge: Construct ACPI BERT table
Add a Boot Error Record Table to the ACPI information.  Avoid a driver
error message by skipping the table altogether when no errors are found,
or support isn't built in.

BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack.  Use test
     data plus a failing Grunt system.

Change-Id: I6fe38eefacaad0bc73d0cb4ae44a339a45857128
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28478
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-07 14:52:53 +00:00
Marshall Dawson 64e1fcaaf9 amd/stoneyridge: Construct BERT region from machine check
Add functions to build a Boot Error Record Table region based on
settings found in the MCA registers.

Two entries are reported for each error due to the nature of the ACPI
driver.  The first is a Generic Processor Error, which the OS recognizes
and parses.  Generic errors cannot convey much error description or
processor context.  Therefore an IA32/X64 Processor Error is also added,
which allows reporting the values found in the MCA MSR registers.

Follow-on work could decode the MC errors more precisely, and better
completing the Generic Error and the Check structure.  The current
level of support is sufficient to identify a (i.e., human readable)
problem in dmesg, and provides adequate context information for
analysis.

BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack.  Use test
     data plus a failing Grunt system.

Change-Id: I4d4ce29ddefa22aa29e6d3184f1adeaea1d5f837
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28477
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-07 14:52:32 +00:00
Marshall Dawson e1bd38bec5 amd/stoneyridge: Create an MCA structure
Convert the Machine Check reporting to use a newly defined structure.
This will facilitate later patches that will pass pointers to the MSR
values.

BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack.  Use test
     data plus a failing Grunt system.

Change-Id: I0a98aecc83a0fa1c5ca7926849a89145a595d9ff
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28476
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-07 14:52:03 +00:00
Marshall Dawson 0b4a1e220a amd/stoneyridge: Relocate MCA error identification
Move the process of interrogating the Machine Check registers into
its own file.  This rearranges source code in preparation of supporting
a Boot Error Record Table, which stoneyridge will use to report latent
MC errors to the OS.

BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack.  Use test
     data plus a failing Grunt system.

Change-Id: Ia3275e9135dc96ba4a717c9371f38843fa1e3e64
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-07 14:51:42 +00:00
Marshall Dawson 4b0f6fa156 amd/stoneyridge: Adjust memory map for reserved
Carve out memory to be reported to the OS as reserved.  This makes
room for a region usable for Boot Error Record Table information.
The BERT region reserved size is larger than likely requried, however
the SMM region's base must be on a boundary matching the granularity
of its size.

BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack.  Use test
     data plus a failing Grunt system.

Change-Id: I0958f6b6bab3fe9dae36c83e1fd9ae6ed0290a18
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28474
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-07 14:51:31 +00:00
Marshall Dawson bb7f1b41e7 amd/fam15: Add more MCA information
Add more definitions to be used for Machine Check Architecture
support, mainly for determining the type of error that is being
interpreted.  MCA is described in detail in the BKDG.

BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack.  Use test
     data plus a failing Grunt system.

Change-Id: I0682288aa58c69aee323fb43f74027f7a1905b68
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-07 14:51:03 +00:00
Marshall Dawson 1d8d369dad x86/acpi: Add BERT table
Create a structure for the Boot Error Record Table, and a generic
table generator function.

BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack.  Use test
     data plus a failing Grunt system.

Change-Id: Ibeef4347678598f9f967797202a4ae6b25ee5538
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-07 14:50:34 +00:00
Marshall Dawson 44705c6e5e x86/acpi: Add BERT to the revision table
Add the proper table revision level for the Boot Error Record Table.

BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack.  Use test
    data plus a failing Grunt system.

Change-Id: Ib4596fe8c0dd2a4e2e98df3a1bb60803c48d0256
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28471
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-07 14:50:16 +00:00
Marshall Dawson 991467da4d arch/x86: Add BERT region support functions
Add code for generating the region pointed to in an ACPI Boot Error
Record Table.

The BERT region must be reported as Reserved to the OSPM, so this
code calls out to a system-specific region locator.  cbmem is
reported as type 16 and is not usable for the BERT region.

Events reported via BERT are Generic Error Data, and are constructed
as follows (see ACPI and UEFI specs for reference):
 * Each event begins with a Generic Error Status Block, which may
   contain zero or more Generic Data Entries
 * Each Generic Data Entry is identifiable by its Section Type field,
   and the data structures associated are also in the UEFI spec.
     * The GUIDs are listed in the Section Type field of the CPER
       Section Descriptor structure.  BERT doesn't use this structure
       but simply uses its GUIDs.
     * Data structures used in the Generic Data Entry are named as
       Error Sections in the UEFI spec.
         * Some sections may optionally include a variable number of
           additional structures, e.g. an IA32/X64 processor error
           can report error information as well as machine contexts.

It is worth noting that the Linux kernel (as of v4.4) does not attempt
to parse IA32/X64 sections, and opts to hexdump them instead.

BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack.  Use test
     data plus a failing Grunt system.

Change-Id: I54826981639b5647a8ca33b8b55ff097681402b9
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28470
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-07 14:50:02 +00:00
Marshall Dawson 03b99772f7 include/cper.h: Add max of enum
Define the maximum value of the cper_x86_check_type enum, for use later
in determining a legal function argument.

Change-Id: I73df4c6daa5d232c2d38b0896442b5bcab5aa15f
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28533
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-07 14:49:51 +00:00
Mikolaj Walczak fad5395879 wedge100s: Add TPM support
Change-Id: Id7e8ad63de2a6094c66cbd47ae9b7707a9af4e81
Signed-off-by: Mikolaj Walczak <mwalczak@fb.com>
Reviewed-on: https://review.coreboot.org/28529
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-07 10:59:58 +00:00
Okash Khawaja dd5411a8b1 fsp_broadwell_de: enable spi console
this enables spi console for wedge100s with broadwell_de. the console
size is 64kb. enabling spi console in `board.fmd` enables code which
calls into `timer_monotonic_get` (from `spi_flash_cmd_poll_bit`) and
`udelay` (from `ich_status_poll`). this patch selects `TSC_CONSTANT_RATE`
in fsp_broadwell_de's Kconfig to satisfy that.

Change-Id: Ib925c5aee88b65c46a81534405c364dd5649f8e8
Signed-off-by: Okash Khawaja <okash.khawaja@gmail.com>
Reviewed-on: https://review.coreboot.org/28528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-09-07 10:25:52 +00:00
Furquan Shaikh 2d602098f9 mb/google/octopus: Configure H1 interrupt pad using Rx level config
This change configures GPIO_63 (which is used for H1 interrupts) as Rx
Level. This ensures that the signal gets passed on to the next logic
state as is and the APIC entry can be configured to trigger interrupt
on level or edge as per the kernel driver expectation.

TEST=Verified that no H1 interrupt timeouts are seen with 100
iterations of warm and 100 iterations of cold reboot.

Change-Id: I7aac30300a4251d9b40276dcca7ebc6a6d814c40
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-06 22:45:23 +00:00
Michael van der Westhuizen 401f8c59bd qemu-q35: Use the TSC for udelay
Use the TSC for delays on q35, ensuring that the TSC delay code is
included in the correct stages when selected.

Tested on qemu-35 and wedge-100s (for no regressions).

Change-Id: I3f8368509807974bfcf2a0fcff7a4aa21adf47ed
Signed-off-by: Michael van der Westhuizen <rmikey@fb.com>
Reviewed-on: https://review.coreboot.org/28526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-09-06 16:31:10 +00:00
Okash Khawaja 1c8f699758 wedge100s: enable mrc cache in fmap
this enables mrc cache in fmap for wedge100s and always enable it in
Kconfig.

Change-Id: I27cd236f67a6500b40fc3eb731397d408402f041
Signed-off-by: Okash Khawaja <okash.khawaja@gmail.com>
Reviewed-on: https://review.coreboot.org/28527
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-06 16:30:13 +00:00
kane_chen e781856af1 mainboard/google/poppy/variants/rammus: Enable GSPI clock for bus 0.
On rammus, system halt was observed because of gspi clk value being set to 0.

Log info from serial coreboot:
FMAP: area RW_NVRAM found @ 9fa000 (24576 bytes)
SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000
VBNV: Restore from flash failed
ASSERTION ERROR: file 'src/soc/intel/common/block/gspi/gspi.c', line 443

gspi.c
442
443     assert(gspi_clk_mhz != 0);
444     assert(ref_clk_mhz != 0);
445     return (DIV_ROUND_UP(ref_clk_mhz, gspi_clk_mhz) - 1) & SSCR0_SCR_MASK;

BUG=none
BRANCH=master
TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage
Flash FW to DUT, and make sure system boots up.

Change-Id: Ibe3937902901b2cdc1a196415c08fabb0f3155f2
Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28405
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-06 10:30:39 +00:00
Lijian Zhao 013ebbfa58 soc/intel/cannonlake: Fix Coverity Scan report
Fix uninitialized variable OnModuleSpd, init bool with false first.

BUG=CID 1395330, 1395331
TEST=N/A

Change-Id: I050287370f7321ff9905937304bb3cc7f20d8c6a
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-06 10:30:04 +00:00
Tristan Shieh 79b990d965 mediatek: Refactor memory test code among similar SoCs
Refactor memory test code which will be reused among similar SoCs.

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Elm

Change-Id: I800aa9a73f0b4588f46a98c964e2794bdf04f09d
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/28436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
Reviewed-by: Julius Werner <jwerner@google.com>
2018-09-06 10:29:39 +00:00
Sathyanarayana Nujella 6f70d51fac mb/google/poppy/variants/nocturne: Enable DMIC CLK0/DATA0
DMIC's are now connected to DMIC_CLK0/DMIC_DATA0.
So, enable the pins accordingly.

BUG=b:113744731,b:111106010
BRANCH=none
TEST='emerge-nocturne coreboot chromeos-bootimage' builds the image

Change-Id: I48cace3c6099a2853fcb377c695a5e325094baf6
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/28433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-06 10:28:59 +00:00
Rizwan Qureshi 55597ff279 soc/intel/common: Add function to set BILD bit in RTC
Add a function to set the Bios Interface Lock Down bit (bit 31)
in RTC Configuration register (0x3400). This bit when set prevents
the top swap enable bit (bit 0) in the RTC BUC register (0x3414)
from being changed.

Change-Id: Iacaeeb0d6cabcf0c2c46a58948457ab832351476
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/28057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-06 10:28:19 +00:00
Joel Kitching adfaea5400 acpi/gnvs: delay setting chromeos_apci_t.vdat until depthcharge
Standardize on using vboot_handoff data structure for transferring
data between coreboot and depthcharge.  chromeos_acpi_t.vdat is
undefined until set in depthcharge.

BUG=b:112288216
TEST=compile and run on eve
CQ-DEPEND=CL:1198814

Change-Id: Iccc021334d3c6f0145dffd5ca05beb9e430378a9
Signed-off-by: Joel Kitching <kitching@gmail.com>
Reviewed-on: https://review.coreboot.org/28407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-06 10:27:53 +00:00
Joel Kitching 6fbd874391 chromeos/gnvs: remove function and naming cleanup
- Remove unused acpi_get_chromeos_acpi_info (see CB:28190)
- Make function naming in gnvs.h consistent (start with "chromeos_")

BUG=b:112288216
TEST=compile and run on eve

Change-Id: I5b0066bc311b0ea995fa30bca1cd9235dc9b7d1b
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/28406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-06 10:26:50 +00:00
Marshall Dawson 8e5e9cf1a8 x86/acpi: Add APEI definitions
Add ACPI Platform Error Interfaces definitions that will be used
for building a BERT table region in a subsequent patch.  Two tables
are defined:  the Generic Error Status Block, Generic Error Data
Entry.

For reference, see the ACPI specification 6.2-A tables 381 and 382.

BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack.  Use test
     data plus a failing Grunt system.

Change-Id: Ib9f4e506080285a7c3de6a223632c6f70933e66c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-06 10:24:44 +00:00
Marshall Dawson fd39f915f5 src/include: Add CPER definitions
Add definitions from the UEFI appendix on Common Platform Error
Record (appx. N in revision 2.7-A).  The structures and fields
defined are the minimum required for generating ACPI Boot Error
Record data in a subsequent patch.

BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack.  Use test
     data plus a failing Grunt system.

Change-Id: I74d8ec8311de749e891827747b84dce0e737aceb
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-06 10:24:26 +00:00
Marshall Dawson 05b1bac072 src/include: Introduce guid_t type
Duplicate the guid_t and GUID_INIT framework from the Linux
driver.  Adapt it for coreboot, and create supporting copy
and compare functions.

Change-Id: Ia1cd7a1f0e0f900858830e1a6a7e2bbbe272fa30
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-06 10:24:09 +00:00
Seunghwan Kim c76e53ce30 mb/google/poppy/variants/nautilus: Bump VCC_SA voltage offset 75mV
Nautilus-Wifi with m3 AP got a halt issue during CTS test.

Nautilus-Wifi was FCS with Celeron AP first and also its PCB/BOM was
validated only with Celeron. Since Celeron deos not support turbo
boost mode, its steady power demend and lower CPU frequency may not
reflect the potential noise hidden inside the board.

Bumping VCC_SA voltage offset 75mV confirmed works to mitigate the
potential noise coupling to VCC_GT/SA, and we verified this change
makes this issue go away on Nautilus-Wifi board.

Nautilus-LTE doesn't show this issue, since it has 10L PCB, will have
better grounding and less noise/ripple than 8L PCB.

BUG=b:111417632
BRANCH=poppy
TEST=Verified CTS test pass without an issue.

Change-Id: Id13fcc36a5b6ed42620c66f57a7303f30bff1a50
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/28439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-06 05:07:08 +00:00
Aamir Bohra 6d569e0c6b intel/fsp2_0: Add fsp2.1 shared stack feature support
FSP 2.1 implementation is adding features on top of fsp2_0.
One such feature is a shared stack implementation that requires
coreboot to allocate stack for fspm and then fsp uses the same
stack as coreboot. This implementation adds support for shared
stack feature.

Change-Id: I6581111dbaddfa403eca14100577ccc8a05c4ec7
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/28358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-06 04:33:00 +00:00
Amanda Huang c36e8bf24f mb/google/octopus: Enable TBMC device
This change enables tablet mode ACPI device for all octopus boards.

BUG=b:113348027

Change-Id: I69a5dd41cd0958b93f8eed338fed4b6ee77a178f
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-06 03:54:51 +00:00
Martin Roth 11f7298249 mainboard/google/kahlee: Enable the BCLK buffer
Set GPIO135 high to enable audio through the BCLK buffer.

BUG=b:113559558
TEST=None
BRANCH=grunt

Change-Id: I1dcecf5960d3c91e0c2165e7f8856ff423c06e8c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/28482
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-05 20:35:43 +00:00
Stefan Tauner 3e3bae03cf nb/intel/x4x/gma.c: fix skipping of native graphics init
CB:27984 (e6c8f7e) is supposed to skip over NGI if bit #1 in
register GCC is set. However the check for x4x was wrongly
checking if any bit of the whole register is set.

Change-Id: I5000f5e771abb98f046e2ad19c1bee7dbc0743fc
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/28447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-09-05 13:08:21 +00:00
Nico Huber 4ba7b26019 arch/x86/Makefile: include dependencies for romcc bootblock
We already explicitly generated a dependencies file for the romcc
bootblock. Though, as it has its own rule and isn't registered
to any of our object-file classes, the dependencies file wasn't
included automatically.

Change-Id: I441cf229312dff82f377dcb594939fb85c441eed
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/28442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-05 10:06:36 +00:00
Stefan Tauner 0fc76910d6 mb/intel/dg43gt/dsdt.asl: fix globalnvs.asl include path
Use ICH10's file instead of ICH7's.

Change-Id: I02678179e8f1dbd9b9f7d6407383a7a6cad15011
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/28450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-09-05 10:05:50 +00:00
Xiang Wang 21ed107958 riscv: add entry assembly file for RAMSTAGE
RAMSTAGE will revoke CAR/scratchpad, so stack and exception handling
needs to be moved to ddr memory. So add a assembly file to do this.

Change-Id: I58aa6ff911f385180bad6e026d3c3eace846e37d
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/28384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-05 10:04:57 +00:00
Evgeny Zinoviev 384e9aed8c mb/lenovo: Support dual graphics for xx20/xx30 ThinkPads
Add CMOS option that allows to use both integrated and discrete GPU.

Tested on ThinkPad W530.

Change-Id: I8842fef0fa1235eb91abf6b7e655ed4d8598adc7
Signed-off-by: Evgeny Zinoviev <me@ch1p.com>
Reviewed-on: https://review.coreboot.org/28393
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-05 10:04:20 +00:00
Xiang Wang ce1af8b0bf riscv: add support to check machine length at runtime
Highest two bits of misa can be used to check machine length. Add code
to support this.

Change-Id: I3bab301d38ea8aabf2c70437e179287814298b25
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/27770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-05 10:03:40 +00:00
Martin Roth ee0f225e3a util/lint: update whitespace checking rules
- Check payloads, the root Makefiles and toolchain.inc
- 3rdparty is already not checked, so remove
- The marks around COPYING, LICENSE, and README were not needed
- Skip checking .ico files

Change-Id: Ic4a1709224604b36362d82e249c2916fca0336a2
Signed-off-by: Martin Roth <martinr@coreboot.org>
Reviewed-on: https://review.coreboot.org/28431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-09-04 12:38:56 +00:00
Martin Roth 87282737a8 payloads: Remove/fix trailing whitespace
Change-Id: Idfc54ca0ed53f52ddad61114ec6b05d94dd746c1
Signed-off-by: Martin Roth <martinr@coreboot.org>
Reviewed-on: https://review.coreboot.org/28430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-09-04 12:38:40 +00:00
Martin Roth 8600893017 util/lint: Update whitespace linter for FreeBSD
On FreeBSD, this test was failing with the error:
"grep: Argument list too long"

I found that changing this to other forms takes MUCH longer, so I left
the original method mostly unchanged except for moving the include &
exclude lists into variables.

Currently, I'm setting all non-linux operating systems to use the second
version. I'll update that if I find other that other OSes support the
first.

Change-Id: I1c9281440d051dea8a8b3a3ddc04676ccea77c7a
Signed-off-by: Martin Roth <martinr@coreboot.org>
Reviewed-on: https://review.coreboot.org/28429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-09-04 12:38:18 +00:00
Zhuohao Lee fe68ab9fd1 mb/google/poppy/variants/rammus: add sku info into smbios table
This patch adds the mainboard.c in order to support the sku id in smbios
table where the sku id is queried from the eeprom via EC.

BUG=b:113714761
BRANCH=master
TEST=check the result of 'dmidecode'

Change-Id: I3413784cca1ac10a2468d84f2d06c0e1d701fdcb
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/28426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-04 12:37:16 +00:00
Philipp Deppenwiese 9569ebeab8 payloads/LinuxBoot: Fix remaining issues
* Update kernel versions
* Fix initrd path handling

Change-Id: Ia0641fd0c0db1e47ee4829b73871af662d4a6370
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/28401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-09-04 12:36:43 +00:00
Xiang Wang 3b5351d044 riscv: add spin lock support
Add spin lock support for riscv.

Change-Id: I7e93fb8b35c4452f0fe3f7f4bcc6f7aa4e042451
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/27356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-04 12:35:47 +00:00
Xiang Wang 33354ddaa8 riscv: Add DEFINE_MPRV_READ_MXR to read execution-only page
Must to set MXR, when needs to read the page which is execution-only.
So make this change.

Change-Id: I19519782fe791982a8fbd48ef33b5a92a3c48bfc
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/28394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2018-09-04 12:35:29 +00:00
Wim fb758d420b drivers/intel/fsp1_1: Fix typo
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Change-Id: I9c6b063970fa328650de3f4402fe203305b5b760
Reviewed-on: https://review.coreboot.org/28373
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Wim Vervoorn
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-02 03:11:49 +00:00
Xiang Wang a5b265bb0c riscv: separately define stack locations at different stages
BOOTBLOCK/ROMSTAGE run in CAR/scratchpad. When RAMSTAGE begins
execution will enable cache, then CAR will disappear. So the
Stack will be separated.

Change-Id: I37a0c1928052cabf61ba5c25b440363b75726782
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/28383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-09-02 03:10:58 +00:00
Evgeny Zinoviev 0186912f9e mb/lenovo: dGPU power handling on T430, T530
Enable dGPU power handling on Lenovo ThinkPad T430, T530 via PMH7
register 0x50.

Although there's no Thinker-1 chip on these models according to
schematics, dGPU power control via PMH7 works the same as on T420/T520,
so they can be considered Thinker-1-compatible.

It can be tested from linux userspace using util/pmh7tool.

To turn dGPU power off:
  pmh7tool -c 0x50 7
  pmh7tool -c 0x50 3

To turn it on:
  pmh7tool -s 0x50 3
  pmh7tool -s 0x50 7

To check whether it is on (bash):
  reg=0x$(pmh7tool -r 0x50)
  echo "$(( (( reg & 0x08 )) >> 3 ))"
or just `pmh7tool -b 0x50 3` with
https://review.coreboot.org/#/c/coreboot/+/28388/

Tested on ThinkPad W530.

Change-Id: Ieab1a33b3c680c757cc0999660b5cb7e122474cc
Signed-off-by: Evgeny Zinoviev <me@ch1p.com>
Reviewed-on: https://review.coreboot.org/28392
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-02 03:10:39 +00:00
Martin Roth b7c0b8c8ee util/crossgcc: Add GCC 8.1 patch for missing backslash
When building the toolchain under BSDs, this missing backslash is
needed.

Change-Id: I40b0adaa73b241713493fd74f24c93f85e7aabbe
Signed-off-by: Martin Roth <martinr@coreboot.org>
Reviewed-on: https://review.coreboot.org/28362
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-02 03:09:46 +00:00
Elyes HAOUAS 6688f466a8 src/drivers/spi/tpm: Fix typo & capitalize TPM and IRQ
Change-Id: Ifb1e024821153865dd4a27a100f8a9c61151e0e1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-09-02 03:09:30 +00:00