Commit Graph

26759 Commits

Author SHA1 Message Date
Arthur Heymans e155e78a47 superio/ite/it8721f: Add SuperIO ACPI declarations
Change-Id: I074d57fa5b140b6946ae81beb210fefac48a66eb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-21 14:45:36 +00:00
Arthur Heymans 7200638b6d superio/ite/it8721f: Add resources
There is no public datasheet available for this SuperIO so the resources are
guessed by looking at other ITE SuperIO's and the register dumps while running
vendor firmware.

The only board with this SuperIO in the tree is the asus m5a88-v. Most of the
devicetree entries would have been invalid here so one should not worry too much
about regressions.

Tested with Foxconn d41s.

Change-Id: I6715c68b3aa9aebf6e292975cbf64ce905b30e8b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-21 14:45:32 +00:00
Arthur Heymans eb6f2f55ff nb/intel/pineview: Use a common MMCONF_BASE_ADDRESS
This should not be board specific.

Change-Id: Ifa617e84af767f33a94f1ddfa7d4883c1a45198f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-21 13:13:38 +00:00
Arthur Heymans 015339fbf0 nb/intel/pineview: Use the correct address for the RCVEN strobe
When doing the receive enable training, the final mapping of the ranks is
already done, so we can be sure that that address 0x00000000 there will always
be a rank.

Change-Id: I7ac017a8816fc9a47cef0695826a1c32f699f6f8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-21 11:55:02 +00:00
Arthur Heymans 1f6369e333 nb/intel/pineview: Use i2c block read to fetch SPD
With this the time spend during the raminit decreases from ~480ms to ~126ms.

Change-Id: Ic23f39f1017010c89795e626f6a6f918f8bda17a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-21 11:54:51 +00:00
Lucas Chen 38eb0ecca5 soc/intel/skylake: Remove unsupported sleepstates in ACPI table
Some OS certification test (for example Windows) will fail if there
are unsupported sleep states. Since these states are not really used
today, we can remove them from ACPI table.

BRANCH=eve
BUG=b:72197653
TEST=certification system sleep test pass.

Change-Id: I5f5122cac1bf61f7c580afb18cc66b5ff07286fb
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/1065401
Commit-Queue: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://review.coreboot.org/28080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-08-21 10:36:58 +00:00
Richard Spiegel 3388fdecf2 vendorcode/amd/pi/00670F00/Lib: Remove unused functions
The only code still used are LibAmdPciRead() and LibAmdPciWrite(). These
functions are used by PspBaseLib. Remove all functions that are not used,
directly or indirectly, by LibAmdPciRead() and LibAmdPciWrite().

BUG=b:112688270
TEST=Build grunt

Change-Id: Iba5cfbeee8e83ca78279a1bc2a333370c04f55ed
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28194
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-20 17:29:48 +00:00
Mike Banon 0e596ae760 vendorcode/amd/agesa/f15tn: add Richland RL-A1 to the equivalence table
This small change is required for the successful loading of microcode
from F15TnMicrocodePatch0600110F_Enc.c for the Richland RL-A1 CPUs,
such as A10-5750M found at coreboot-supported Lenovo G505S laptop.

Richland RL-A1 and Trinity TN-A1 CPUs are using the same microcode,
so the Richland RL-A1 IDs should be added to this equivalence table.

Function `GetPatchEquivalentId()` in
`src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuMicrocodePatch.c`
goes through the equivalence table like below.

  for (i = 0; i < (EquivalencyEntries * 2); i += 2) {
    // check for equivalence
    if (ProcessorRevisionId == MicrocodeEquivalenceTable[i]) {
      *ProcessorEquivalentId = MicrocodeEquivalenceTable[i + 1];
      return (TRUE);
    }
  }

Change-Id: I7a68f2fef74fb4c578c47645f727a9ed45526f69
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-on: https://review.coreboot.org/28204
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: <awokd@danwin1210.me>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-20 17:24:14 +00:00
Lucas Chen cc11c97b70 eve: Add PL1 override to 7W
Change PL1 from 4.5W to 7W, based on thermal test results.

BRANCH=eve
BUG=b:73133864
TEST=Verify the MSR PL1 limitation is set to 7W.

Change-Id: Ic3629f9c3b7eb6eef1a1b5a3051c9a11448bc9ad
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28078
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-20 15:59:15 +00:00
Wei Shun Chang b54d15487a soc/intel/skylake: Support PL1 override option
In legacy mode, DPTF on some systems may rely on MMIO to control PL1
settings. However, MSR PL1 also contributes to the decision of max
PL1 power; and in the current design, the lower value takes effect.
In order to align MMIO and MSR settings, a tdp_pl1_override option is
added to override the MSR PL1 limitation.

BRANCH=eve
BUG=b:73133864
TEST=1. Write PL1 override setting in devicetree.cb
     2. Verify the MSR PL1 limitation is set correctly.

Change-Id: I35b8747ad3ee4c68c30d49a9436aa319360bab9b
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-20 15:58:52 +00:00
Nico Huber 5d790e3f52 Makefile.inc: Ensure update of build.h
There were so many pitfalls that I wrote my own version of this even-
tually. This version is inspired by the procedure of Alex Thiessen[1].
Instead of generating a `build.h` on demand, we always generate a tem-
porary version that, if it differs from the current one, is added as
a dependency.

As we use .SECONDEXPANSION on the prerequisites, special care is taken
that we won't generate the file twice. As it would be too late to add
the dependency if we'd run `genbuild_h.sh` inside a recipe, we have
to run it through the `$(shell)` function. But that brings us to the
next issue: The make variables used by `genbuild_h.sh` are not expor-
ted to this shell like they would be in a recipe. So we export them
manually. We could also make these variables explicit parameters of
`genbuild_h.sh` instead.

An alternative to always creating the temporary `build.h` would be
to add a phony target as dependency instead, and finally calling
`genbuild_h.sh` again in case we need an update. But, um, we create
so many files anyway...

[1] https://review.coreboot.org/25685

Change-Id: I311cf610eabae873c70f2985fc7a09acec8061f0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-08-20 15:56:29 +00:00
Caveh Jalali 20df17cc65 atlas: enable keyboard backlight support
This adds support for controlling the keyboard backlight over ACPI.

BUG=b:112619894
BRANCH=none
TEST=verified keyboard backlight can be adjusted using keyboard
	shortcuts

Change-Id: I25713f341e8b5a4e50903ac109bfa717f20969d8
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/28205
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-20 15:55:38 +00:00
Matt Delco c1cb6da816 mb/google/poppy/variants/nocturne: enable eist
Enable Enhanced Intel SpeedStep (EIST) on nocturne.

Change-Id: Ie9b832f5bc3a5ef300783bd9bcd7cf5d186b98fa
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/28103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-20 15:54:28 +00:00
Matt Delco 1950ed9ee3 mb/google/eve: enable eist
Enable Enhanced Intel SpeedStep (EIST) on eve.

Change-Id: I49b18b817cda570f5c3c4d048c4e03329ac10b87
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/28102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-20 15:54:13 +00:00
Matt Delco 9084c3c31b soc/intel/skylake: add CPPC support
ACPI 5.0 defines a method _CPC for "Continuous Performance Control" (CPPC).
Linux has a driver that enables features like speed shift without
consulting ACPI.  Other OSes instead rely on this information and need a
_CPC present. Prior to this change performance in Win10 never exceeds
80% and MSR 0x770 is 0, while with this change (and enabling eist) higher
speeds can be achieved and the MSR value is now 1.

Change-Id: Ib7e0ae13f4b664b51e42f963e53c71f8832be062
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/27673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-08-20 15:53:54 +00:00
Matt Delco 9557a34abe cpu/intel/common: add function to init cppc_config
This change adds a method to init a cppc_config structure in a way that
should ideally work across Intel processors that support EIST.

Change-Id: Ib767df63d796bd1f21e36bcf575cf912e09090a1
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/28068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-08-20 15:53:28 +00:00
Subrata Banik afa07f7ae4 soc/intel/common/block: Move common uart function to block/uart
This patch moves uart functions which are common across multiple soc to
block/uart. This will remove redundant code copy from soc
{skylake/apollolake/cannonlake}.

BUG=b:78109109
BRANCH=none
TEST=Build and boot on KBL/APL/CNL platform.

Change-Id: I109d0e5c942e499cb763bde47cb7d53dfbf5cef6
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-20 15:51:48 +00:00
Enrico Granata 55a8d8a772 nocturne: Enable debouncing of SX9310 CLOSE / FAR IRQs
This is meant to solve an issue where the proximity sensor may fluctuate
between CLOSE / FAR in rapid succession upon the user removing their hand
from the unit, before settling on the correct output.

Using the hardware debouncing filter solves this issue and removes the
spurious fluctuations.

BRANCH=None
BUG=None
TEST=manual on Nocturne, observing events come in

Change-Id: I78cc4852d42fcda6209fedce1ce91236b5814571
Signed-off-by: Enrico Granata <egranata@chromium.org>
Reviewed-on: https://review.coreboot.org/28112
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-20 15:51:27 +00:00
Krzysztof Sywula bb0cf01911 soc/intel/common/block: Add WHL 2-core SKU
There are two SKUs of Whiskey Lake W0, 2-core and 4-core.

Change-Id: Ia9b2707568702a5fbae3e9495ca53df34613a542
Signed-off-by: Krzysztof Sywula <krzysztof.m.sywula@intel.com>
Reviewed-on: https://review.coreboot.org/28111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-20 15:50:57 +00:00
John Zhao 7dff726b78 soc/intel/apollolake: Force USB-C into host mode
When USB OTG is set, GLK FSP enables xHCI SW ID pin and configures
USB-C as device mode. Force USB-C into host mode.

BUG=b:111623911
TEST=Verified that USB-C being host mode once USB OTG is set.

Change-Id: Iaca3d25a1159f922b743963cbc508d8defa7b6ff
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/27746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-20 15:50:27 +00:00
Crystal Lin 5251ff7204 mb/google/octopus/variants/fleex: Increase weida touchscreen reset delay
Weida touchscreen controller needs 130 ms delay after reset

BUG=b:111102092
BRANCH=master
TEST=Verify touchscreen on fleex works with this change

Change-Id: Ia86c3acf3c0e09ca05cc1681113672b546f830a0
Signed-off-by: Crystal Lin <crystal_lin@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-20 15:49:45 +00:00
Nico Huber bfae9a861a util/lint: Exclude util/superiotool from checkpatch
`superiotool` follows its own style (e.g. lot's of missing spaces
and odd placement of braces in the register descriptions).

Change-Id: Ifa33938a0fbac10577cbda10537f856f6f100233
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28214
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-20 15:21:50 +00:00
Patrick Rudolph 64efbe20bf configs: Build test verbose BDK and FIT payload support
Change-Id: I2075142a0b241222839899e707a1e3d264746432
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/28228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-08-20 14:34:33 +00:00
Stefan Tauner 3a9d222c1e drivers/pc80/rtc: do not warn if CMOS options are unavailable
Callers should have a default ready and get noticed by the return
value of get_option(). No need to scare log readers at this location.

Change-Id: Ied373d8a02afdc8d1017c9f41d9004e3797dfbb3
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/28215
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-20 10:57:41 +00:00
Patrick Rudolph 2de750b141 nb/intel/raminit: Remove unused headers
Change-Id: Ic6e7341b53bcabc415089ccfab121d3694ccb071
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/28212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-08-20 09:52:08 +00:00
Patrick Rudolph 08c9a7ce1f nb/intel/sandybridge/raminit: Fix DIMM type mapping
The DIMM type read from SPD needs to be converted to make sure SMBIOS fills
in the correct formfactor.

Tested on Lenovo T430: The Form Factor no longer reads as unknown.

Change-Id: Ia0211fa133f4ba9d60dfbd5f0dd45a43df68c030
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/28192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-20 09:51:46 +00:00
Patrick Rudolph 15e6469ef9 nb/intel/sandybridge: Fill in DIMM serial number
Fill in SMBIOS type 17 DIMM serial number, read from SPD.

Fixes FWTS SMBIOS type 17 test.

Change-Id: Id6e818bfdf4af0fd34af56dc23df052a3f8c348d
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/28191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-20 09:51:22 +00:00
John Zhao eac84ca35c intel/common/block: Fix issues found by klockwork
src/soc/intel/common/block/cpu/mp_init.c
  Function init_cpus: Pointer dev checked for NULL may be
  dereferenced.

src/soc/intel/common/block/graphics/graphics.c
  Function graphics_get_bar: Pointer dev returned from
  call may be NULL and will be dereferenced.

BRANCH=None
TEST=Built & booted Yorp board.

Change-Id: I5e7caa15a3911e05ff346d338493673af5318a51
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-20 07:04:12 +00:00
Elyes HAOUAS ddcf5a05e3 mb/asus/kfsn4-dre: Use common pnp_{enter,exit} functions
Change-Id: I4b0577bf3c00307733a1096749c1835d86764f29
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-20 06:58:02 +00:00
Elyes HAOUAS e051dc07f5 mb/kontron/ktqm77: Use common pnp_{enter,exit} functions
Change-Id: Ib5799cceacefa89385a7615ef1c4b4d06157044f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-20 06:57:51 +00:00
Alexander Couzens 74ab031ba1 ec/lenovo/pmh7: use read/write function in clear_bit/set_bit
Make the code simpler and improve readability.

Change-Id: Ifa9308c32e4646c122254931b55fb83541a10a3c
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/28195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-20 06:57:18 +00:00
Stefan Tauner b0622de878 src/drivers/usb/Kconfig: increase warning signs for BBB owners
The help text is already very clear but some users (first and
foremost the author of this patch ;) are still selecting
USBDEBUG_DONGLE_BEAGLEBONE when using a BeagleBone Black and
waste hours on analyzing the debug output of EHCI debug driver.

Change-Id: Ibf002db7d81ed44878f3ce0324170e4b99e780a5
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/28184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-20 06:55:50 +00:00
Matt DeVillier 6e89d3bc52 google/cyan: Fix ACPI resource scope for Melfas touchscreen
Fix scope of ResourceSource, which should match the scope of the
device itself.

Change-Id: I9d0ff0ecc2721ec55b1ed12dddb495cd55966daf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/28114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-19 16:58:24 +00:00
Alexander Couzens 532e8a9bf5 mb/lenovo/x1_carbon_gen1: add support for hynix memory
All different memory configuration should be supported by now.
Thanks to Igor Lee.

Change-Id: Ib93c0e3cbdc29cbf6cff26292df4fbbb8208082f
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: Igor Lee <getrun@gmail.com>
Reviewed-on: https://review.coreboot.org/27781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-19 00:19:54 +00:00
Julius Werner 5d6593a43c arm64: Factor out common parts of romstage execution flow
The romstage main() entry point on arm64 boards is usually in mainboard
code, but there are a handful of lines that are always needed in there
and not really mainboard specific (or chipset specific). We keep arguing
every once in a while that this isn't ideal, so rather than arguing any
longer let's just fix it. This patch moves the main() function into arch
code with callbacks that the platform can hook into. (This approach can
probably be expanded onto other architectures, so when that happens this
file should move into src/lib.)

Tested on Cheza and Kevin. I think the approach is straight-forward
enough that we can take this without testing every board. (Note that in
a few cases, this delays some platform-specific calls until after
console_init() and exception_init()... since these functions don't
really take that long, especially if there is no serial console
configured, I don't expect this to cause any issues.)

Change-Id: I7503acafebabed00dfeedb00b1354a26c536f0fe
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/28199
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-17 21:29:46 +00:00
Patrick Rudolph 2d22cda32c configs: Add various common non-default mainboards
Build tests:
* Option table
* Static option table
* Verbose debugging code
* Sandy Bridge optional Kconfigs
* TPM debugging code
* Lenovo Bluetooth on Wifi
* Libgfxinit on Sandy Bridge

Change-Id: Ib463f578c97a212d0729aa6f54b7b6fba33e0478
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/28118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-17 21:18:41 +00:00
Iru Cai 89af71c7dd sandybridge/raminit_common.c: fix printram statement
Change-Id: Iddea8cc71dc1fb33d46b22dd19e39bf1c1257555
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/28117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-17 21:18:17 +00:00
Richard Spiegel 9010140c6d soc/amd/common/block/pi/agesawarapper.c: Use find_image()
In preparation to removing AmdLib, replace function LibAmdLocateImage()
with its ported version find_image().

BUG=b:112625809
TEST=Build and boot grunt.

Change-Id: I75ddd55f7e3e7f2cd7914f97c99b62690ae70660
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28164
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-17 21:11:07 +00:00
Richard Spiegel 84978674e3 soc/amd/common/block: Port vendorcode's LibAmdLocateImage
In preparation to removing AmdLib, function LibAmdLocateImage() has to be
ported to be used by agesawrapper. The most important aspect of this porting
is that it has to obey coreboot format, specifically 8 character tab and 80
characters max. This required breaking the function in 2 (to solve
indentation) and rename some variables to shorter names.

One important aspect was breaking
(AMD_MODULE_HEADER*)(((AMD_IMAGE_HEADER *) CurrentPtr)->ModuleInfoOffset)

into:
image_ptr = (AMD_IMAGE_HEADER *) current_ptr;
if (validate_image((void *)image_ptr->ModuleInfoOffset,

and, within validate_image completed by:
AMD_MODULE_HEADER *mod_ptr = (AMD_MODULE_HEADER *)module_chain;

BUG=b:112625809
TEST=Build grunt, functionality tested in next commit.

Change-Id: I0d1e8b966cf7606fdb15a95de5771f835f07b2bc
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-17 21:10:53 +00:00
Kevin Chiu 108bf29516 google/grunt: Update TP/TS/H1 i2c timings
After adjustment on Careena EVT
TP: 400.0 KHz
TS: 396.8 KHz
H1: 396.8 KHz

BUG=b:112663934,b:112664258
BRANCH=master
TEST=emerge-grunt coreboot
     measure by scope
Change-Id: I9eeaf9290d95969a283f14618878e28faf0ea46f
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/28119
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-17 21:10:34 +00:00
Marc Jones 24462e6507 x86/acpigen: Fix ACPI _ROM method
Fix the following Error:
FAILED [LOW] AMLAsmASL_MSG_SERIALIZED_REQUIRED: Test 1, Assembler remark in line
142
Line | AML source
--------------------------------------------------------------------------------
00139|
00140|     Scope (\_SB.PCI0.IGFX)
00141|     {
00142|         Method (_ROM, 2, NotSerialized)  // _ROM: Read-Only Memory
     |                   ^
     | Remark 2120: Control Method should be made Serialized    (due to creation of named objects within)
00143|         {
00144|             OperationRegion (ROMS, SystemMemory, 0xCD520000, 0xFE00)
00145|             Field (ROMS, AnyAcc, NoLock, Preserve)
================================================================================

ADVICE: (for Remark #2120, ASL_MSG_SERIALIZED_REQUIRED): A named object is
created inside a non-serialized method - this method should be serialized. It is
possible that one thread enters the method and blocks and then a second thread
also executes the method, ending up in two attempts to create the object and
causing a failure.

Use the acpigen_write_method_serialized() to correct the error.

BUG=b:112476331
TEST=Run FWTS.

Change-Id: I145c3c3103efb4a02b4e02dd177f4bf50a2c7b3e
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/28124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-08-17 21:10:04 +00:00
Marc Jones e17ec3e2e8 ec/google/chromeec: Fix ACPI FWTS error
Fix the following FWTS error:
FAILED [MEDIUM] AMLAsmASL_MSG_RETURN_TYPES: Test 1, Assembler warning in line
3038
Line | AML source
--------------------------------------------------------------------------------
03035|                 Return (One)
03036|             }
03037|
03038|             Method (_Q09, 0, NotSerialized)  // _Qxx: EC Query
     |                       ^
     | Warning 3115: Not all control paths return a value    (_Q09)
03039|             {
03040|                 If (Acquire (PATM, 0x03E8))
03041|                 {
================================================================================

ADVICE: (for Warning #3115, ASL_MSG_RETURN_TYPES): Some of the execution paths
do not return a value. All control paths that return must return a value
otherwise unexpected behaviour may occur. This error occurs because a branch on
an conditional op-code returns a value and another does not, which is
inconsistent behaviour.

_Q09 is a reserved method and can't return a value. Change the logic
so that no return is used and avoid this test error.

BUG=b:112476331
TEST=Run FWTS.

Change-Id: Ibbda1649ec2eb9cdf9966d4ec92bfd203bb78d07
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/28123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-08-17 21:09:45 +00:00
Marc Jones 4ae02818fc mainboard/google/kahlee: Fix ACPI method Not Serialized error
Fix the following failure from FWTS:

FAILED [LOW] AMLAsmASL_MSG_SERIALIZED_REQUIRED: Test 1, Assembler remark in line
131
Line | AML source
--------------------------------------------------------------------------------
00128|                 }
00129|             }
00130|         })
00131|         Method (_CRS, 0, NotSerialized)  // _CRS: Current Resource Settings
     |                   ^
     | Remark 2120: Control Method should be made Serialized    (due to creation of named objects within)
00132|         {
00133|             Name (RBUF, ResourceTemplate ()
00134|             {
================================================================================

ADVICE: (for Remark #2120, ASL_MSG_SERIALIZED_REQUIRED): A named object is
created inside a non-serialized method - this method should be serialized. It is
possible that one thread enters the method and blocks and then a second thread
also executes the method, ending up in two attempts to create the object and
causing a failure.

BUG=b:112476331
TEST= Run FWTS.

Change-Id: I6f4f6e7e94b01f673afc97d9415481ee63e406e3
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/28122
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-17 21:09:30 +00:00
Marc Jones 1faa11ed39 Fix PCI ACPI _OSC methods
Fix the IASL build warnings:
Object is not referenced (Name [CDW2] is within a method [_OSC])
Object is not referenced (Name [CDW3] is within a method [_OSC])

Remove the not referenced objects. They are not needed.

BUG=b:112476331
TEST=IASL doesn't give the warning.

Change-Id: I5b38d4de3f9875c5b013a49eb5146bf5916b96a6
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/28121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-17 21:09:17 +00:00
Matt Delco 4988fe2986 src/include: add more msr defines
This change adds some MSRs that are needed in a subsequent change to add
support for Continuous Performance Control.

Change-Id: Id4ecff1bc5eedaa90b41de526b9a2e61992ac296
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/28067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-17 20:13:21 +00:00
Matt Delco b425bc8cd0 arch/x86/acpigen: add methods for cppc
This change adds 2 methods for Conginuous Performance Control that was
added in ACPI 5.0 and expanded twice in later versions.  One function
will create a global table based on a provided struct, while the other
function is used to add a _CPC method in each processor object.

Change-Id: I8798a4c72c681b960087ed65668f01b2ca77d2ce
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/28066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-17 20:13:11 +00:00
Felix Held e37d771001 superio/ite/it8720f: fix power control init
The existing code for modifying the power state after power loss of the system
only implemented the transitions from power off to either power on or power keep
properly.

Since I don't have a board with this chip, I couldn't test the patch on real
hardware. The two cases described above were tested before the original patch
was merged, so I'd expect this to work.

Change-Id: I3c26a2837e451dbfd3cee82e9beedc0f4a90af03
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-17 18:27:00 +00:00
Maulik V Vaghela b6f2e7bd4c mb/intel/coffeelake_rvp: Update spd details as per Coffeelake board
Update SPD details to match with Coffeelake U RVP board

BUG=none
BRANCH=none
TEST=Boot on coffelake U rvp board and check if memory training is
passing and board boots till payload.

Change-Id: I953354cf5c6045731262f4f4e9da230187c2d246
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/27906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-08-17 12:28:32 +00:00
Maulik V Vaghela bad8fbb22c mb/intel/coffeelake_rvp: Update GPIO table for Coffeelake U RVP
Update GPIO table as per board schematics.
GPIO table for other variants will be added later.

Change-Id: Ieb55d160ae2d6bff940840b1fba9411979332d4d
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/27907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2018-08-17 12:28:17 +00:00
Daisuke Nojiri 9b56ef05cc Nami: Disable powering off EC on cr50 update
Nami doesn't support wakeup from hibernation by CR50. This causes the
device to remain turned off after CR50 update.

This patch disables turning off EC on cr50 update. CR50 resets the
whole system. So, EC reset is not required.

Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>

BUG=b:112604277
BRANCH=none
TEST=gsctool -a -u /media/removable/cr50.bin && reboot
Verify EC reboots. AP prints 'Waiting for CR50 reset to pick up update'
then reboots.

Change-Id: I06f5eb6100e8af6ffec45d4de2b40eff44f89709
Reviewed-on: https://review.coreboot.org/28113
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-17 12:27:40 +00:00