Commit Graph

1244 Commits

Author SHA1 Message Date
Patrick Georgi c430ecec9e libpayload/arm64: Drop unused static array
Fixes build with gcc8.1

Change-Id: I042f79ddfb4c249e00b5b259280289b8534f6854
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/27546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-20 11:06:36 +00:00
Raul E Rangel 1b43ad7149 libpayload/generic_hub: Detect port disconnect after reset
If a port disconnects after a reset we should abort any initialization
on the port. This might mean the device has re-enumerated as a 3.0 device
so the hub should be scanned again.

BUG=b:76831439
TEST=Verified USB-C devices that get detected correctly in depthcharge.

Change-Id: Iad899544684312df1bef08d69b5c7f41eac3a21c
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-17 20:38:46 +00:00
Raul E Rangel d29c81d513 libpayload/xhci: Check noop return code when debugging
Make it obvious that the command has failed.

BUG=b:76831439
TEST=Verified on grunt

Change-Id: Ifa0b2fb087f5f0a36ba017a774fc98b33ab035a4
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-17 15:30:10 +00:00
Raul E Rangel c534a066d8 libpayload: Add UNKNOWN_SPEED to usb_speed enum
xhci_rh_port_speed return -1 if the port is disabled. The usb_speed enum
is unsigned so this results in a positive value which implies success.

Adding a -1 to the enum will make it signed so the >= 0 check will work
correctly.

BUG=b:76831439
TEST=verified on grunt that -1 is returned when port is disabled.

Change-Id: I98a373717d52dfb6ca4dcc53a00dc1b4c240a919
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-17 15:23:36 +00:00
Raul E Rangel 50a2a86832 libpayload: Make libpayload compile using gnu11
This matches coreboot.

BUG=b:76831439
TEST=emerge-grunt libpayload deptcharge chromeos-bootimage
then booted image

Change-Id: I3a3baa03e03a31e9e75b201ac4fa642505fc1d3a
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-16 07:44:03 +00:00
Raul E Rangel 8fdc9162d9 libpayload/xhci: Document struct offsets on xhci_t
This makes it easier to know what offset each register references.

BUG=b:76831439
TEST=none

Change-Id: I92dcbd463ceb4dd8edbbd97b51a4e9aa32a983a6
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-16 07:43:50 +00:00
Furquan Shaikh 6756c16e82 payloads/libpayload/drivers/i8042: Disable scanning on disconnect
This change ensures that keyboard scanning is disabled and keyboard is
set to default state while disconnecting the keyboard. This is
required to ensure that the controller doesn't keep scanning and
buffering keystrokes which could lead to OS drivers reading stale
data.

BUG=b:110024487
TEST=Verified that kernel driver is able to probe correctly even if
multiple keys are pressed during handoff from payload to OS.

Change-Id: I1ffb8904d545284454c1825ee2e7c0087fc13762
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-02 07:33:38 +00:00
Furquan Shaikh 1299dc107d payloads/libpayload/drivers/i8042: Add macros for i8042 commands
This change adds macros for commands (written to 0x64) and keyboard
commands (written to 0x60) for 8042 controller.

BUG=b:110024487

Change-Id: I74b2388d048e35b5bdf5bd862d0975e88f1bd6af
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-02 07:32:33 +00:00
T Michael Turney be073dacb0 libpayload: cheza - fix config for chromium chroot build
Add CONFIG_LP_CHROMEOS to configuration file

Change-Id: I528dee96cf5052b99b8f7573010d98fd80680688
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/26711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-22 13:11:06 +00:00
Patrick Rudolph 7ee05eddf1 util/cbfstool: Support FIT payloads
In order to support booting a GNU/Linux payload on non x86, the FIT format
should be used, as it is the defacto standard on ARM.
Due to greater complexity of FIT it is not converted to simple ELF format.

Add support for autodecting FIT payloads and add them as new CBFS_TYPE 'fit'.
The payload is included as is, with no special header.
The code can determine the type at runtime using the CBFS_TYPE field.
Support for parsing FIT payloads in coreboot is added in a follow on
commit.
Compression of FIT payloads is not supported, as the FIT sections might be
compressed itself.

Starting at this point a CBFS payload/ can be either of type FIT or SELF.

Tested on Cavium SoC.

Change-Id: Ic5fc30cd5419eb76c4eb50cca3449caea60270de
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-06-15 09:13:24 +00:00
Elyes HAOUAS 012e7a4ebd libpayload/curses/{form,menu}: Fix uncountable "information"
Change-Id: I28c79d0262a54b58d353802e0d572e5b8be5fbc5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-04 09:14:48 +00:00
Patrick Rudolph ae2cb2d3bf libpayload-x86: Export keyboard modifiers
Add function to get active keyboard modifiers.

Change-Id: Ifc7bd4aa86f20d67c5b542d0458b966e605c5499
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18601
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-31 15:31:47 +00:00
Patrick Rudolph 1f5ebf7c8b libpayload: Export usbhid_getmodifiers
Add a new method to retrieve active usb keyboard modifiers.

Change-Id: Ief6679ce782b58b9ced207f4f27504fb2a517b76
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18602
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-31 15:28:24 +00:00
Hannah Williams b81362a82e libpayload-x86: i8042: fix i8042_data_ready_ps2 and i8042_data_ready_aux
keyboard_disconnect was called without keyboard_init being called and in this
case keyboard_havechar returns true because i8042_data_ready_ps2 is
dereferencing uninitialized variable ps2_fifo from within fifo_is_empty causing
keyboard_disconnect to be stuck in this while loop.
while (keyboard_havechar())
    keyboard_getchar();

BUG=b:80299098
TEST=Check if the normal mode path in depthcharge is not causing a hang

Change-Id: I944b4836005c887a2715717dff2df1b5a220818e
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/26590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-30 01:10:44 +00:00
Kyösti Mälkki 185202c469 libpayload: Fix payload .bss corruption
Third call to newwin() corrupted payload context.
Fix array indexing and check for boundary.

Sample payload coreinfo was affected, loader_eax
variable got corrupted on my particular build.

Change-Id: Iee98901cf57f0689f65ac43aa7e60e8aea092500
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-05-21 04:48:28 +00:00
Patrick Georgi e8604b8da6 libpayload: disable mouse on CHROMEOS
We already have that Kconfig flag, so I guess we should use it for
consistency.

Change-Id: I61ee6a97e369ccfe5c55d4414a5fa91c8d80ecf7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/26351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-05-18 16:00:18 +00:00
Patrick Rudolph 5afc2936b8 libpayload-x86: Add PS2 mouse driver
Make use of i8042 driver to add PS2 mouse driver support.

Tested on Lenovot T500.
The touchpad can be used to drive the mouse cursor.

Change-Id: I4be9c74467596b94d64dfa510824d8722108fe9c
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-05-15 12:02:31 +00:00
Patrick Rudolph 52165966f3 libpayload-x86: keyboard: Use i8042 driver
Make use of i8042 driver in keyboard.c.

Required to add PS/2 mouse support.

Tested on Lenovo T500.

Change-Id: If60b5ed922b8fc4b552d0bfd9fe20c0fd6c776bf
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18596
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-15 11:21:55 +00:00
Patrick Rudolph 9d22172558 libpayload-x86: Move keyboard.c
Move keyboard.c into i8042 folder.

Change-Id: Idd30a9082e48a451d9fe5ead3f3dda4e6396b50c
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18595
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-15 11:20:30 +00:00
Patrick Rudolph e6a3821b97 libpayload-x86: Add common i8042 driver
Add a common i8042 driver that uses multiple overflowing
fifos to seperate PS/2 port and PS/2 aux port.

Required to support PC keyboard and PC mouse at the same time.

Tested on Lenovo T500.

Change-Id: I4ca803bfa3ed45111776eef1f4dccd3fab02ea39
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18594
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-15 11:20:06 +00:00
Patrick Rudolph 4f5bed5210 cbfs: Rename CBFS_TYPE_PAYLOAD to CBFS_TYPE_SELF
In preparation of having FIT payloads, which aren't converted to simple ELF,
rename the CBFS type payload to actually show the format the payload is
encoded in.

Another type CBFS_TYPE_FIT will be added to have two different payload
formats. For now this is only a cosmetic change.

Change-Id: I39ee590d063b3e90f6153fe655aa50e58d45e8b0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-05-04 10:30:24 +00:00
Elyes HAOUAS 00877386ee payloads/libpayload: Add spaces around '=='
Change-Id: Ie1da925aceb01c2d21b472bf171000803004578f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/25856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-05-02 07:59:14 +00:00
T Michael Turney 9b5c28af18 libpayload: Add Timer for sdm845
Uses ARCH64 Timer

TEST=build

Change-Id: Ic312bcf3bc7e80482b7f038e2dbc4abaaffd5956
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/25214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-05-01 23:35:25 +00:00
T Michael Turney 1e3e02a1d2 libpayload: Add raw_read_ functions
Add: raw_read_cntfrq_el0() and raw_read_cntpct_el0()

Required to support Arch64 Timer

Change-Id: I86aa97039304b9e9336d0146febfe1811c9e075a
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/25649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-05-01 23:34:03 +00:00
Elyes HAOUAS 03f2536f9d libpayload/drivers/usb/ohci_private.h: Add parentheses around macro
Change-Id: Ib90564e32f5ff204aa5d856024b7eed2624a77b7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-04-29 18:13:08 +00:00
Elyes HAOUAS 99fe7d243d libpayload/include/queue.h: Remove trailing whitespace
Change-Id: I7ff676f51958e12c40a82f56e68a776ddf429228
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/25825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-04-27 09:11:16 +00:00
Elyes HAOUAS 4713b5cd9e libpayload/curses/form: Remove trailing whitespace
Change-Id: I231ea26e8d8bfc53da22a440451802b425c996b0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/25830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-04-27 09:09:17 +00:00
Elyes HAOUAS f2be550d3d payloads/libpayload/curses/menu: Remove trailing whitespace
Change-Id: Ia4bd5224a77914e0561fa35a18aec8db16bff320
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/25829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-04-27 09:09:07 +00:00
Julius Werner 39c4bb0211 libpayload: Move GDB functions to stdlib.h
When GDB support is compiled in, halt() in libpayload will call
gdb_enter(). halt() is defined in <stdlib.h> and gdb_enter() in
<libpayload.h>. Usually files just include <libpayload.h> so this is not
a problem, but in some situatons a payload may just include <stdlib.h>
(or a file including it like <assert.h>), leading to an undeclared
identifier here. Move the GDB functions to <stdlib.h> to solve this.

Change-Id: I7b23b8ac9cd302aa6ef96f24565130490ac40071
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/25730
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-19 20:39:29 +00:00
Paul Menzel 0cdaad36eb Use git HTTP URLs without `/p` in it
Change-Id: I9972b138c6dd2a289880c4ec8b3fe64fc3baa66b
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/25545
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-17 10:38:06 +00:00
Patrick Rudolph 57afc5e0f2 arch/arm64/armv8/mmu: Add support for 48bit VA
The VA space needs to be extended to support 48bit, as on Cavium SoCs
the MMIO starts at 1 << 47.

The following changes were done to coreboot and libpayload:
 * Use page table lvl 0
 * Increase VA bits to 48
 * Enable 256TB in MMU controller
 * Add additional asserts

Tested on Cavium SoC and two ARM64 Chromebooks.

Change-Id: I89e6a4809b6b725c3945bad7fce82b0dfee7c262
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/24970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-03-23 04:09:50 +00:00
Julius Werner 3faa2c802e libpayload: usbhid: Zero-initialize all parts of usbhid instance struct
The USBHID driver zero-initializes some but not all of the fields in its
usbhid_inst_t structure. This is a problem because under some
circumstances, some of the uninitialized fields may be read and lead to
incorrect behavior. Some (broken) USB keyboards keep sending reports
that contain all zeroes even when they have no new keys... these usually
get silently ignored, but if the usbhid_inst_t structure is in an
inconsistent state where 'previous' is zeroed out but 'lastkeypress'
is non-zero because it wasn't properly initialized, these reports will
be interpreted as keyrepeats of the bogus 'lastkeypress'. This patch
changes the code to just xzalloc() the whole structure so we won't have
to worry about initialization issues anymore.

Change-Id: Ic987de2daaceaad2ae401a1e12b1bee397f802ee
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/23766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-02-16 00:08:26 +00:00
Aaron Durbin 610e2e6faf libpayload: allow x86 devices to provide non-tsc implementation
Make is so that a different timer source can be provided instead
of TSC on x86 platforms.

BUG=b:72378235,b:72170796

Change-Id: I6faeecf7624a5aa4e1af8862036f1fbd2f54eb51
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-01-26 00:23:28 +00:00
Nico Huber 4792689f67 libpayload: Add pci_free_dev() and some boilerplate
Add just enough code and boilerplate to keep it compatible with future
libflashrom.

Change-Id: If0d46fab141da525f8f115d3f6045a8c417569eb
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-12-07 21:51:24 +00:00
Julius Werner f38a10f8d2 libpayload: Add SKU ID coreboot table support
This patch adds support to read the SKU ID entry from the coreboot table
that was recently added in coreboot.

Change-Id: I1c3b375da6119a4f8e8e7e25a11644becb90f927
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22743
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-07 01:19:38 +00:00
Julius Werner 2e029ac6a6 libpayload: Minor board ID / RAM code cleanups
This patch mirrors recent cleanups in coreboot regarding the strapping
ID entries in the coreboot table.

Change-Id: Ia5c3728daf2cb317f8e2bc72c6f1714d6cb4d080
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07 01:18:30 +00:00
Julius Werner 59e9080dcb endian: Fix bebitenc() to actually encode big-endian
bebitenc() just runs a downward loop over the same body as lebitenc().
That doesn't give you a byte-swapped result, it gives you the same final
value, just starting from the other side to fill it in. (Also, it
confused i++ and i--, so it really gives you a compiler error.)

The correct code needs to have the array index inverted relative to the
bit shift index to produce a big endian result.

Change-Id: I5c2da3a196334844ce23468bd0124bbe2f378c46
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-06 20:46:37 +00:00
Ronald G. Minnich 8db7f8bad7 LB_TAGS: change the value of CB_TAG_MAC_ADDRS to 0x33
When building the Go version of cbmem I found that
LB_TAG_MAC_ADDRS has the same value as LB_TAG_VERSION_TIMESTAMP.

I am guessing that this tag was little used. In any event, move it
forward to 0x33.

Change-Id: I038ad68e787e56903a2ed9cb530809a55821c313
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/22218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-29 18:07:51 +00:00
Nico Huber 3f43edc351 libpayload/storage: Add Sunrise Point AHCI PCI id
Change-Id: I9645d76d05014722e4ae0c398d82f7f8e34d6f1c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/21289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-09-02 15:33:50 +00:00
Nicola Corna b016f144cc libpayload: add time()
Change-Id: I97e393537ccc71ea454bb0d6cdbbb7ed32485f1e
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/21011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-21 16:53:20 +00:00
Caveh Jalali 673e014fab libpayload: add *SECS_PER_SEC macros to stddef.h
this adds convenience definitions for MSECS_PER_SEC, USECS_PER_MSEC,
and USECS_PER_SEC along the lines of the time units in coreboot's
<timer.h>.

Change-Id: I489dc2d1ff55d137936acec74ac875dc7fbc1713
Signed-off-by: Caveh Jalali <caveh@google.com>
Reviewed-on: https://review.coreboot.org/20882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-08-14 18:06:33 +00:00
Martin Roth 6c9c196f1c copy & update test routines from what-jenkins-does
Currently the only testing we had was 'what-jenkins-does' and
'make lint'. While the lint testing is suitable for developers,
the 'what-jenkins-does' target really isn't, as it was designed
specifically for testing on jenkins.

This adds the infrastructure for basic tests that are more suitable
for the developer. Extended tests and improvements will follow.

Add the coreboot-builds directories to .gitignore.

TODO:
- Save/restore .config
- Update test-abuild to use existing COREBOOT_BUILD_DIR variable

Change-Id: I19e1256d79531112ff84e47a307f55791533806f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chris Ching <chingcodes@google.com>
2017-08-11 15:24:56 +00:00
Nico Huber abc69cd001 libpayload/libpci: Add a constant for PCI class memory other
Change-Id: I71e902c4ec843608c1518fe1e8b90fbcf98a13d1
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-10 16:41:16 +00:00
Paul Menzel 12a3fbdb7e libpayload: Use a static copy of `font_glyph_filled()`
libpayload needs a static copy of the out of line function
`font_glyph_filled()` in every TU that needs it. So make it static
inline.

This fixes a build error by gcc (Debian 7.1.0-12) 7.1.0 from Debian
Sid/unstable. This happens with any libpayload based payload like
coreinfo, nvramcui or tint.

```
[…]
    LPCC       build/coreinfo.elf (LINK)
/src/coreboot/payloads/coreinfo/build/libpayload/bin/../lib/libpayload.a(corebootfb.libc.o): In function `corebootfb_putchar':
/src/coreboot/payloads/libpayload/drivers/video/corebootfb.c:173: undefined reference to `font_glyph_filled'
[…]
```

Change-Id: I931f0f17b33abafdc49aa755a0dad65e28820750
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/20897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-08-10 12:07:13 +00:00
Caveh Jalali 0068a9f579 add __must_check to */compiler.h
the __must_check function attribute is pretty much straight from the
linux kernel - used to encourage callers to consume function return
values.

Change-Id: I1812d957b745d6bebe2a8d34a9c4862316aa8530
Signed-off-by: Caveh Jalali <caveh@google.com>
Reviewed-on: https://review.coreboot.org/20881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-08 18:18:03 +00:00
Paul Kocialkowski d85e485c58 libpayload: video: Add support for font scaling with a factor
This introduces support for font scaling with a factor provided via
Kconfig. In practice, the font itself is not scaled at any point in
memory and only the logic to determine whether a pixel should be filled
or not is changed.

Thus, it should not significantly impact either the access time or
memory use.

Change-Id: Idff210617c9ec08c6034aef107cfdb34c7cdf029
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/20709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-08-03 20:37:07 +00:00
Paul Kocialkowski 1c0b603673 libpayload: video: Introduce helpers for font access
This introduces helpers for accessing the included font, instead of
using hardcoded values provided by the font's header itself.

It will allow painlessly adding support for font scaling in a subsequent
change. It should not introduce any functionality change.

Change-Id: I0277984ec01f49dc51bfc8237ef806f13e3547e2
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/20708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-08-03 20:34:59 +00:00
Ricardo Ribalda Delgado ff1477911e libpayload: Double HEAP_SIZE in default config
Bettong board with the standard configuration is not capable of
running nvramui with the default size.

malloc error happens on PDC_makelines(). Resulting in:

Booting from CBFS...
Run img/nvramcui
Calling addr 0x00100000
initscr(): Unable to create stdscr.
exited with status 1

Change-Id: I56a0fb3319fe77599bf3dd6c328a0b70be60a348
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-on: https://review.coreboot.org/20681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-07-28 16:17:04 +00:00
Nico Huber 1a4add9e87 libpayload/storage: Replace 1s AHCI reset delay with a timeout
AHCI spec explicitly states that we may poll.

TEST=Ran FILO on kontron/bsl6 and observed that the controller
     always becomes ready during the first delay.

Change-Id: If34694abff14d719d10d89bc6771dbfa12065071
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-07-27 13:56:53 +00:00
Nico Huber a67dd9de77 libpayload/storage: Enable bus mastering for AHCI
This is (thankfully) not done by coreboot any more for recent chipsets.

Change-Id: If56e38037f7b1e53871ee63e6ff297028c59d493
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-07-27 13:56:45 +00:00
Nico Huber 50ab84fa37 libpayload: Clean up unaligned memset() support
Use a `for` instead of a `while` loop and use meaningful identifiers.
Also, don't use more than one variable for one and the same purpose,
don't use more (non-const) variables than necessary, don't alter more
than one variable per statement, don't compare pointers of different
types and don't do pointer arithmetic on `void *`.

This was meant as a fix up to a regression but that has already been
fixed.

Change-Id: I0c8fd118d127a26cfcf68bfb0bf681495821e80a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-07-26 19:34:02 +00:00
Marshall Dawson 148a7a60d8 libpayload: Fix unaligned buffer logic in default_memset
Fix an issue when setting an unaligned buffer where n is less
than the difference of the rounded up pointer and the pointer.
This was identified where n=1 was passed.  n was decremented
once, as expected, then decremented again after the while()
evaluated to false.  This resulted in a new n of 4GB.

Change-Id: I862671bbe7efa8d370d0148e22ea55407e260053
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-07-20 21:38:14 +00:00
Stefan Reinauer 6a00113de8 Rename __attribute__((packed)) --> __packed
Also unify __attribute__ ((..)) to __attribute__((..)) and
handle ((__packed__)) like ((packed))

Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/15921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-13 19:45:59 +00:00
Jeremy Compostella 5b8987ae46 libpayload: Support unaligned pointer for memcpy, memmove and memcmp
The memcpy(), memmove() and memcmp() functions use word by word
operations regardless of the pointer alignment.  Depending on the
platform, this could lead to a crash.

This patch makes the memcpy(), memmove() or memcmp() operate byte per
byte if they are supplied with unaligned pointers.

Change-Id: I0b668739b7b58d47266f10f2dff2dc9cbf38577e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/20535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-07-13 18:16:15 +00:00
Jeremy Compostella 54db255529 libpayload: Support unaligned pointers for memset
The optimization of the memset() function introduced by commit
dbadb1dd63 (libpayload: Reorder default
memcpy, speed up memset and memcmp) is provoking an issue on x86
platform when compiling without the CONFIG_GPL option.

GCC is making use of the movdqa instruction to copy words.  This
instruction can raise a "General Protection Fault Exception" when it
is called on a non-aligned address argument.

Change-Id: I73382a76a4399d8e78244867f2ebb1dca176a6bf
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/20524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-12 10:58:55 +00:00
Patrick Rudolph 837da6ade7 libpayload: Add mouse cursor driver
Add a driver to handle multiple low level mouse drivers
and provide basic cursor acceleration support.

Tested on Lenovo T500.

Change-Id: Ib7cec736631b8acf81a14d28daa29ff720777b10
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-28 00:56:53 +00:00
Elyes HAOUAS 70083a1de9 payloads: Add whitespace around '<<'
Change-Id: I0659f6ec59fb808b4cedf57d60d737c13c250042
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20396
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-28 00:23:18 +00:00
Elyes HAOUAS 7c4a8e57dc libpayload/drivers/usb/ehci_private.h: Add brackets around macro
Change-Id: Iee8dc03d5a4ca7537c7da4fed2c67b169c9e2422
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-27 19:43:22 +00:00
Elyes HAOUAS 47916fbef2 libpayload/drivers/usb/xhci_private.h: Add parentheses around macro
Change-Id: I0347594e9480dedc4845b6863733a67fc5e47e1c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20371
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-27 19:43:15 +00:00
Elyes HAOUAS b09822cf82 libpayload/drivers/usb/ohci_private.h: Add brackets around macro
Change-Id: Id4892adba161cd08eecde71a011384b6c465b98f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-06-27 16:51:30 +00:00
Duncan Laurie 98409cff92 libpayload: corebootfb: Add null check for framebuffer address
If the framebuffer address is zero the corebootfb_init() function
should abort and not attempt to use it for video, otherwise it
will likely hang.

This was tested by booting on a board that does not have a display
attached and includes the previous patch to zero the framebuffer
structure in the coreboot tables.

Change-Id: I53ca2e947a7915cebb31b51e11ac6c310d9d6c55
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-27 02:16:10 +00:00
Lee Leahy 6796d787c5 libpayload: Enable building libpayload with march=i586
Add a Kconfig value to enable building libpayload with the 586 compiler.
Update the cross compiler script to add the Kconfig value name that is
used when libpayload builds.

The Quark SOC does not support some of the instructions generated with
the 686 compiler (e.g. CMOV).  Success occurs when
payloads/libpayload/build/config.h indicates that
CONFIG_LP_USE_MARCH_586=1.

TEST=Build and run on Galileo Gen2.

Change-Id: I04907e9a38ee139bae2e8b227821f54614707c25
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/20322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-26 23:14:05 +00:00
Lee Leahy 82890928d3 libpayload/configs: Add configuration for Galileo
Add the default configuration file for the Galileo board.  The Quark SOC
requires building libpayload with march=i586.

TEST=Build and run on Galileo Gen2

Change-Id: Ifd4b533feacbab6f0d357e13d8cebb64bc1c18c6
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/20323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-26 15:32:17 +00:00
Martin Roth e81ce0483d payloads: change coreboot to lowercase
The word 'coreboot' should always be written in lowercase, even at the
start of a sentence.

Change-Id: I2ec18ca55e0ea672343a951ab81a24a5630f45fd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2017-06-07 12:08:55 +02:00
Paul Menzel 59e2113670 Use www.coreboot.org over coreboot.org
<https://coreboot.org> is redirected to <https://www.coreboot.org>.

```
$ curl -I https://coreboot.org
HTTP/1.1 301 Moved Permanently
Server: nginx/1.8.1
Date: Mon, 05 Jun 2017 10:41:33 GMT
Content-Type: text/html
Content-Length: 184
Connection: keep-alive
Location: https://www.coreboot.org/

```

So use the command below to use the final location to save a redirect.

```
$ git grep -l https://coreboot.org \
| xargs sed -i 's,https://coreboot.org,https://www.coreboot.org,g'
```

Change-Id: I4176c20ef31399f0063b41e3a0029cca0c1b0ff3
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/20035
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-07 12:05:44 +02:00
Paul Menzel a8843dee58 Use more secure HTTPS URLs for coreboot sites
The coreboot sites support HTTPS, and requests over HTTP with SSL are
also redirected. So use the more secure URLs, which also saves a
request most of the times, as nothing needs to be redirected.

Run the command below to replace all occurences.

```
$ git grep -l -E 'http://(www.|review.|)coreboot.org'
| xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g'
```

Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/20034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-06-07 12:04:50 +02:00
Julius Werner baa3e70084 arm64: Align cache maintenance code with libpayload and ARM32
coreboot and libpayload currently use completely different code to
perform a full cache flush on ARM64, with even different function names.
The libpayload code is closely inspired by the ARM32 version, so for the
sake of overall consistency let's sync coreboot to that. Also align a
few other cache management details to work the same way as the
corresponding ARM32 parts (such as only flushing but not invalidating
the data cache after loading a new stage, which may have a small
performance benefit).

Change-Id: I9e05b425eeeaa27a447b37f98c0928fed3f74340
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-30 22:17:57 +02:00
Shelley Chen d635506fa7 detachables: Add invert parameter
Instead of storing inverted-colored bitmaps,
invert drawing of text bitmap on the fly by adding
an invert parameter down to libpayload.  Merging
pivot and invert fields into flags field.

BUG=b:35585623
BRANCH=None
TEST=Make sure compiles successfully
CQ-DEPEND=CL:506453

Change-Id: Ide6893a26f19eb2490377d4d53366ad145a9e6e3
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/19698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-05-25 18:23:56 +02:00
Nickey Yang d0e465456e cbgfx: Add portrait screen support
cbgfx currently does not support portrait screen which height >width.
so add it.

Change-Id: I66fee6d73654e736a2db4a3d191f030c52a23e0d
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Reviewed-on: https://review.coreboot.org/19474
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-05-01 17:52:12 +02:00
Patrick Georgi c854e943e0 libpayload/gdb: fix unused variable warning
input_underrun is defined but not used. A reasonably new compiler,
enabled warnings and warnings-as-error make the build break for no good
reason.

Change-Id: Ibeb7ba53aad5738938093ab7b34695c9c99c9afe
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/19482
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-04-29 07:34:08 +02:00
Julius Werner d67c6876b5 Turn CBMEM console into a ring buffer that can persist across reboots
This patch allows the CBMEM console to persist across reboots, which
should greatly help post factum debugging of issues involving multiple
reboots. In order to prevent the console from filling up, it will
instead operate as a ring buffer that continues to evict the oldest
lines once full. (This means that if even a single boot doesn't fit into
the buffer, we will now drop the oldest lines whereas previous code
would've dropped the newest lines instead.)

The console control structure is modified in a sorta
backwards-compatible way, so that new readers can continue to work with
old console buffers and vice versa. When an old reader reads a new
buffer that has already once overflowed (i.e. is operating in true ring
buffer mode) it will print lines out of order, but it will at least
still print out the whole console content and not do any illegal memory
accesses (assuming it correctly implemented cursor overflow as it was
already possible before this patch).

BUG=chromium:651966
TEST=Rebooted and confirmed output repeatedly on a Kevin and a Falco.
Also confirmed correct behavior across suspend/resume for the latter.

Change-Id: Ifcbf59d58e1ad20995b98d111c4647281fbb45ff
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18301
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-20 00:29:07 +02:00
Furquan Shaikh 342f5f836c libpayload/libc/console: Flush input driver buffer on init
When console input driver registers itself, perform flush of input
buffer to avoid interpreting any stale key presses before libpayload
is run.

keyboard.c: Remove the redundant buffer flush.
8250.c: Ensure that serial_hardware_is_present is set before call to
add input driver.

BUG=b:37273808
TEST=Verified that any key presses in serial console before payload is
up do not have any effect after the payload starts running.

Change-Id: I46f1b6715ccf6418f5b2c741bf90db2ece26a60d
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19345
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19 19:19:56 +02:00
Julius Werner 7b58319e9c libpayload: cbgfx: Show square images on portrait displays
CBGFX currently doesn't support portrait screens at all. This will have
to be fixed eventually but might take a bit of effort. As a first step
to make devices with a portrait panel somewhat usable, this patch will
just force a square canvas on these panels and keep the bottom part of
the screen black.

Also switch set_pixel to calculate framebuffer position via
bytes_per_line instead of x_resolution. This is supposed to be the
canonical way to do that and may differ in cases where the display
controller requires a certain alignment from framebuffer lines.

Change-Id: I47dd3bf95ab8a7d8b7e1913e0ddab346eedd46f1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19279
Tested-by: build bot (Jenkins)
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
2017-04-17 18:12:02 +02:00
Paul Kocialkowski 038818f00c libpayload: Add gru config
This adds a gru libpayload config, that should fit all gru-based
devices such as kevin.

As gru-based devices are CrOS devices, select the associated config
to enable CrOS-specific features.

Change-Id: I6e79b763fc497c126612b8786a669a33b57ea29f
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/19137
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-04-07 21:33:19 +02:00
Julius Werner 5fae829410 libpayload: usbhub: Force enumeration of all connected ports on init
We have found a non-compliant USB hub (RealTek RTS 5413) that does not
set a port's Connect Status Change bit on its USB 3.0 half if the port
had already been connected while the hub was being reset. To work around
this bug, this patch adds code to initially request the status of every
port after a hub was enumerated, clear the Connect Status Change bit if
set, and then enumerate the port iff it is currently connected,
regardless of whether the change bit was set. A similar behavior can
also be found in the Linux kernel.

BRANCH=oak
BUG=b:35929438
TEST=Booted Elm with this change, my USB 3.0 sticks enumerate now even
if they had been plugged in since boot.

Change-Id: I8a28252eb94f005f04866d06e4fc61ea265cee89
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18729
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-03-15 00:54:23 +01:00
Patrick Rudolph b854ae2649 libpayload-x86: Enable SSE and FPU when present
Allows to use SSE and floating point in payloads without digging to
much into x86 assembly code.

Tested on Lenovo T500 (Intel Core2Duo).
Both floating point operation and SSE is properly working.

Change-Id: I4a5fc633f158de421b70435a8bfdc0dcaa504c72
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18345
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-08 04:44:12 +01:00
Paul Kocialkowski 7a543d2ab9 libpayload: Add oak config
This adds an oak libpayload config, that should fit all oak-based
devices such as elm.

Change-Id: Iabb71404ff84029a5976371a353e8c92e781ca1f
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/18447
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-02-23 17:03:45 +01:00
Mathias Krause 898de6111a libpayload: multiboot - support meminfo flag
Some simple implementation of the MultiBoot protocol may not pass a
memory map (MULTIBOOT_FLAGS_MMAP missing in the flags) but just the two
values for low and high memory, indicated by the MULTIBOOT_FLAGS_MEMINFO
flag.

Support those kind of boot loaders too, instead of falling back to the
hard-coded values in lib_get_sysinfo().

Tested with a multiboot enhanced version of FILO.

Change-Id: I22cf9e3ec0075aff040390bd177c5cd22d439b81
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: https://review.coreboot.org/18350
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-02-17 18:20:38 +01:00
Mathias Krause d2f16cac74 libpayload: x86/head - implement argc/argv handling
Implement the argc/argv passing as described in coreboot’s payload API:
http://www.coreboot.org/Payload_API

While at it, give the code some love by not needlessly trashing register
values.

Change-Id: Ib830f2c67b631b7216843203cefd55d9bb780d83
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: https://review.coreboot.org/18336
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2017-02-17 17:29:40 +01:00
Mathias Krause 57dc93c967 libpayload: x86/exec - simplify and robustify the code
Simplify the code by directly using the arguments on the stack as base
pointer relative memory references, instead of loading them into
intermediate registers first.

Make it more robust by preserving all callee saved registers mandated by
the C calling convention (and only those), namely EBP, EBX, ESI and EDI.

Don't assume anything about the register state when the called function
returns -- beside the segment registers and the stack pointer to be
still the same as before the call.

Change-Id: I383d6ccefc5b3d5cca37a1c9b638c231bbc48aa8
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: https://review.coreboot.org/18335
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2017-02-17 17:27:55 +01:00
Mathias Krause 7b681c5926 libpayload: x86/main - propagate return value of main()
According to coreboot’s payload API [1], the called payload should be
able to return a value via %eax. Support this by changing the prototype
of start_main() and pass on the return value of main() to the caller
instead of discarding it.

[1] https://www.coreboot.org/Payload_API

Change-Id: I8442faea19cc8e04487092f8e61aa4e5cba3ba76
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: https://review.coreboot.org/18334
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-17 17:25:11 +01:00
Mathias Krause 9fa78c136d libpayload: x86/exec - fix argc/argv value passing
According to coreboot’s payload API [1] the argc value should be passed
at stack offset 0x10, so we need to push a dummy value to comply to the
API.

[1] https://www.coreboot.org/Payload_API

Change-Id: Id20424185a5bf7e4d94de1886a2cece3f3968371
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: https://review.coreboot.org/18333
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-17 17:24:08 +01:00
Mathias Krause 901efea8ab libpayload: x86/exec - fix return value passing
The pointer to write the return value to is in %ecx, not %eax. Writing
to (%eax) leads to memory corruptions as %eax holds the return value,
e.g. would write zero to address zero for a "successful" returning
payload.

Change-Id: I82df27ae89a9e3d25f479ebdda2b50ea57565459
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: https://review.coreboot.org/18332
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-15 21:56:14 +01:00
Mathias Krause d42c38b93c libpayload: x86/exec - fix libpayload API magic value
According to coreboot’s payload API [1] the magic value passed to the
payload should be 0x12345678, not 12345678. Fix that.

[1] https://www.coreboot.org/Payload_API

Change-Id: I10a7f7b1a4aec100416c5e7e4ba7f8add10ef5c5
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: https://review.coreboot.org/18331
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-15 21:55:21 +01:00
Patrick Georgi b144a34c60 libpayload: fix build
When .xcompile doesn't already exist, building libpayload fails because
the CC variable (et al) remain empty since .xcompile is only included
after the variables coming from there are evaluated.

Change-Id: I73f1cbced95afcff15839604fea5fd05d81bc3d3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/18228
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-25 17:58:48 +01:00
Patrick Georgi 0ffef882d8 build system: don't run xcompile or git for %clean/%config targets
It takes a long time for no gain: We don't need to update the
submodules, we don't need to fetch the revision, we don't need to find
the compilers, when all we want to do is to manipulate the .config file
or clean the build directory.

Change-Id: Ie1bd446a0d49a81e3cccdb56fe2c43ffd83b6c98
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/18182
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-24 23:22:56 +01:00
Shelley Chen 674e971dc4 libpayload: drivers/keyboard: report power button events
Power button events are usually dropped because the button is not in
the keyboard matrix range.  Add condition to forward it like other keys.

BUG=chrome-os-partner:61275
BRANCH=None
TEST=reboot and make sure power button selection
     in depthcharge's detachable menus is processed on reef.

Change-Id: I86897fa8d73a56533ef62bba05458ac3d339237e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 25654e214f0ab8685d445ced62612a02be851126
Original-Change-Id: I516a0043bd7730789728d5c5498d0a0f30a2acac
Original-Signed-off-by: Shelley Chen <shchen@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/428199
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://review.coreboot.org/18177
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-24 09:33:48 +01:00
Paul Kocialkowski 3e7f14bfae libpayload: Enable USB HID in veyron configuration
This enables USB HID support in the veyron config, since it seems to
work correctly and is needed for interaction with depthcharge on devices
without an embedded keyboard (such as veyron_mickey).

Change-Id: Icae829e3a132005df17bcb6f7e6f8a190912576d
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/17930
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-01-19 23:00:46 +01:00
Jeffy Chen 9a3f06d202 libpayload: usb: Reset ohci controller when trying to shutdown ohci
Currently we just disabled ohci interrupts when calling ohci_shutdown,
Which would not actually shutdown the ohci controller, for example it
may still written the increased HccaFrameNumber to Hcca buffer.

Perform a soft reset to ohci controller as the linux kernel ohci-hcd
driver does.

BUG=chrome-os-partner:60996
BRANCH=None
TEST=Checked on gru, no more "BUG: Bad page state" error in kernel.

Change-Id: I128ab6ba455ac5383a4d48be0bc12b8bb4533464
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4749fc82fdd1b74ca3f2ed3fdf0ef53a5e161087
Original-Change-Id: I3f192aea627ba2fa69533bc0a4270466ca18f2a7
Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/426338
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://review.coreboot.org/18125
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-13 17:40:25 +01:00
Kan Yan b6cadc6465 libpayload: Add VPD address into lib_sysinfo
BUG=chrome-os-partner:56947
TEST=Verifed country code can be parsed from VPD in depthcharge.
BRANCH=None

Change-Id: I2fbbd4a784c50538331747e1ef78c33c6b8a679b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: acea6e2a200e8bd78fd458255ac7fad307406989
Original-Change-Id: I4616fefc6a377d7830397cdadb493927358e25cc
Original-Signed-off-by: Kan Yan <kyan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/425819
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/18124
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-13 17:40:10 +01:00
Paul Kocialkowski 7a9ec36fd4 libpayload: Update ARM CrOS devices configuration
This updates the configuration for ARM CrOS devices (nyans and veyrons)
by using the CHROMEOS Kconfig option, thus reducing the number of
options to select. It also brings proper serial console support.

Change-Id: Iffc84c44a1d339c5bb575fbaffc40bc2d56bb6cf
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/17928
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-01-13 17:34:22 +01:00
Patrick Georgi b5623dede7 libpayload: usb: handle situation with no free device address
Change-Id: I1308bdca90f1a09d980f384ee85552198a39b965
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1260940
Reviewed-on: https://review.coreboot.org/18036
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-06 18:43:05 +01:00
Patrick Georgi a370ae8556 libpayload: xhci: plug leak
Change-Id: Ia163872846906c6c78144a984a405812f856f626
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1325835
Reviewed-on: https://review.coreboot.org/18035
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-06 18:42:18 +01:00
Patrick Georgi 61dac130b2 libpayload: timer: cast cpu_khz to make sure 64bit math is used
Change-Id: Iaf84de2330b433076a66c22fa72ffb45e957c0dc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1261177
Reviewed-on: https://review.coreboot.org/18034
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-06 18:40:44 +01:00
Paul Kocialkowski 35562d8b64 libpayload: Get current tick from high register in generic timer
This fixes the generic timer driver to get the current tick from the
high register, so that comparison with the high count value (obtained
previously from the same register) has a chance to succeed.

Change-Id: I5ce02bfa15a91ad34641b8e24813a5b7ca790ec3
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/17929
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-21 20:26:39 +01:00
Patrick Georgi 4134680d46 libpayload/drivers/video: Improve check in if condition
Coverity considers this a copy&paste error, and maybe it is. In any
case, it makes sense to check the variable that (if the condition is
true) is changed, and the values are the same before that test, so the
change is harmless.

Change-Id: I163c6a9f5baa05e715861dc19643b19a9c79c883
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1347376
Reviewed-on: https://review.coreboot.org/17837
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-14 18:03:13 +01:00
Patrick Georgi 5250852b0f libpayload/.../PDCurses: Improve compatibility with ncurses
Coverity erroneously complains that we call wmove with x or y == -1,
even though our copy of that function properly checks for that.

But: setsyx is documented to always return OK (even on errors), so let
it do that. (and make coverity happy in the process)

Change-Id: I1bc9ba2a075037f0e1a855b67a93883978564887
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1260797
Reviewed-on: https://review.coreboot.org/17836
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-14 18:02:51 +01:00
Patrick Georgi 83f75bfeb9 libpayload/.../PDCurses: avoid reading orig before NULL checking it
Coverity complains and that (unfortunately) means that some compiler
might take advantage of the same fact.

Change-Id: I59aff77820c524fa5a0fcb251c1268da475101fb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1261105
Reviewed-on: https://review.coreboot.org/17835
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-14 15:58:22 +01:00
Nico Huber d1e2edf708 libpayload: Add Cougar Point PCH's AHCI to whitelist
Change-Id: Ie8ca342a32323be4c26c236a5209052ec724317f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17353
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-12-08 01:36:01 +01:00
Jeremy Compostella bf618cb94e libpayload: increase MAX_ARGC_COUNT
MAX_ARGC_COUNT limits the payload to ten parameters which is not
enough when used with a proprietary first stage bootloader providing
hardware description using around 20 parameters.

This patch makes the libpayload able to get up to 32 parameters.

Change-Id: I49925040d951dffb9c11425334674d8d498821f2
Signed-off-by: Jeremy Compostella <jeremy.compostella@gmail.com>
Reviewed-on: https://review.coreboot.org/17467
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-25 13:39:01 +01:00
Julius Werner 58caa8ba8c libpayload: Reintroduce CONFIG_LP_CHROMEOS to set suitable defaults
Chrome OS builds always have some inherent differences to "standard"
libpayload configurations: they don't want to use curses or things like
storage drivers, they always use the coreboot framebuffer and USB, etc.
This patch reintroduces CONFIG_LP_CHROMEOS as an option that only
affects Kconfig defaults. This allows Chrome OS builds to select most of
what they need in one go and reduces board-specific .config files to
only the options that are really specific to that board.

Also restricts the 8250_SERIAL_CONSOLE Kconfig to only default to yes on
x86 boards, which probably makes sense for all of libpayload (some but
far from all ARM boards use 8250-compatible UARTs, and we should
probably not default a platform option unless it's going to be correct
with very high probability).

BRANCH=None
BUG=None
TEST=Built and booted Jerry and Oak.

Change-Id: Ie0c0593ffd399608d2cbfb83d20891f6f1864914
Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Id: e558f59
Original-Change-Id: I609637cd2ea7dfb4558aa3c04c90b64038c9ab57
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/347970
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17024
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-17 22:46:11 +02:00
Julius Werner 4fda9bd0ec libpayload: Replace majority of timer drivers with a generic one
Currently every non-x86 platform supported by libpayload needs to
provide its own timer driver. Most of the ones we have accumulated there
look almost identical: For the frequency, return a preset constant. For
the value, read a 32-bit register, possibly read another 32-bit register
and shift+OR it with the previous one, then return that.

Let's replace this with a single .c file that can easily handle all of
those cases. Menuconfig convenience can still be maintained by providing
several presets that select different defaults for the driver's
configuration options (register address(es) and frequency).

Removes an "enabled" check from Samsung MCT driver since coreboot always
unconditionally enables that timer anyway.

CQ-DEPEND=CL:344809
BRANCH=None
BUG=None
TEST=Booted Oak and Veyron, observed how dev-mode delay was still ~30s

Change-Id: I61cb7d2ffd4902aa841c57f9afa9cd991f770acd
Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Id: a036af6
Original-Change-Id: I9784e7c6aa5abd6d92478ea7ec1cf42c9a437546
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/347749
Reviewed-on: https://review.coreboot.org/17023
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-17 22:43:37 +02:00
Hakim Giydan 11302f38cd libpayload: mvmap2315: Introduce timer driver
Testing: booted successfully.

Change-Id: I4a50c9fb7aec929ea29a3cf2eec3e424e3629c92
Signed-off-by: Hakim Giydan <hgiydan@marvell.com>
Reviewed-on: https://review.coreboot.org/16692
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-09 21:31:46 +02:00
Jeremy Compostella 3ab8ce52f9 libpayload: Fix strtok_r
This patch makes strtok_r:
- handle the end of the string
- handle string that contains only delimiters
- do not set ptr outside of str

Change-Id: I49925040d951dffb9c11425334674d8d498821f1
Signed-off-by: Jeremy Compostella <jeremy.compostella@gmail.com>
Reviewed-on: https://review.coreboot.org/16524
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-08 21:11:34 +02:00
Martin Roth 26d484a237 Fix newlines at the end of files
All but ga-g41m-es2l/cmos.default had multiple final newlines.
ga-g41m-es2l/cmos.default had no final newline.

Change-Id: Id350b513d5833bb14a2564eb789ab23b6278dcb5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16361
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Antonello Dettori <dev@dettori.io>
2016-09-02 18:04:48 +02:00
Julius Werner f975e55dcd cbfs: Add "struct" file type and associated helpers
This patch adds functionality to compile a C data structure into a raw
binary file, add it to CBFS and allow coreboot to load it at runtime.
This is useful in all cases where we need to be able to have several
larger data sets available in an image, but will only require a small
subset of them at boot (a classic example would be DRAM parameters) or
only require it in certain boot modes. This allows us to load less data
from flash and increase boot speed compared to solutions that compile
all data sets into a stage.

Each structure has to be defined in a separate .c file which contains no
functions and only a single global variable. The data type must be
serialization safe (composed of only fixed-width types, paying attention
to padding). It must be added to CBFS in a Makefile with the 'struct'
file processor.

Change-Id: Iab65c0b6ebea235089f741eaa8098743e54d6ccc
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16272
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-27 01:16:22 +02:00
Julius Werner 1143d08f7e libpayload: head.S: Avoid clearing BSS (and heap) again
3 out of 4 architectures currently zero out the payload BSS in early
assembly code, which is pointless since the code loading the payload has
already done that (with a more efficient memset). ARM64 has never had
any code like this and can run just fine without it. This also defeats
the new optimization of moving the heap out of the BSS, since all three
implementations assume that everything between _edata and _end is BSS.
We should just take this out.

Change-Id: I45cd2dabd94da43ff0f77e990f11c877cee6cda1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16091
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-13 02:46:19 +02:00
Julius Werner 55ffccfbae libpayload: cbfs: Fix minor memory leak in some edge cases
cbfs_get_handle() allocates memory for a handle and doesn't free it if
it errors out later, leaving the memory permanently leaked. Fix.

Change-Id: Ide198105ce3ad6237672ff152b4490c768909564
Reported-by: Coverity
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16207
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-12 22:52:22 +02:00
Julius Werner e25d3ff9bd libpayload: lzma: Allocate scratchpad on the heap
Allocating a 15980-byte scratchpad on the stack when your default stack
size is set to 16KB is really not a great idea. We're regularly
overflowing into the end of our heap when using LZMA in libpayload, and
just happen not to notice it because the heap rarely gets filled up all
the way. Of course, since we always *have* a heap in libpayload, the
much saner solution is to just use it directly to allocate the
scratchpad rather than accidentally grow backwards into it anyway.

Change-Id: Ibe4f02057a32bd156a126302178fa6fcab637d2c
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16089
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-08 19:02:07 +02:00
Julius Werner 41ddd4fcc1 libpayload: arm64: Fix MMU range overlap check
The ARM64 MMU code maintains a list of used ranges, to avoid mapping the
DMA buffer over the coreboot tables and things like that. Unfortunately,
the overlap with ranges in that list is checked with

 (start1 >= start2 && start1 <= end2) || (end1 >= start2 && end1 <= end2)

which is not a full overlap check and misses the case where the second
region is completely contained within the first. This patch replaces
that code with a properly vetted primitive from Stack Overflow.

BRANCH=none
BUG=chrome-os-partner:54416
TEST=Observe how Kevin recovery screen now gets drawn at 10x the speed.

Change-Id: I7e2706426762794e160d743bbfc40da1e26eee12
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16075
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-08 17:35:31 +02:00
Antonello Dettori aded214e74 libpayload: split "Drivers" config section in Kconfig
Move the configuration of the timer, storage and USB drivers from the
main Kconfig to three separate ones stored in the respective
directories.

This reduces the LOC of Kconfig and makes it more manageable.

Change-Id: I0786dbc1d5d8317c8ccb600f5de9ef4a8243d035
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/15914
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-02 20:14:36 +02:00
Martin Roth bb9722bd77 Add newlines at the end of all coreboot files
Change-Id: I7930d5cded290f2605d0c92a9c465a3f0c1291a2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15974
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-08-01 21:43:56 +02:00
Patrick Georgi 33ab4fea23 libpayload: fix leak in libcbfs
stage wasn't freed on errors.

Change-Id: I10d2f42f3e484955619addbef2898981f6f90a35
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1347345
Reviewed-on: https://review.coreboot.org/15958
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-31 20:01:10 +02:00
Patrick Georgi e8c413318f libpayload: Drop superfluous "continue"
Change-Id: I5a1d1ce8ba268b08d1275f392f0b9e602860c6ab
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Found-by: Coverity Scan #1260729
Reviewed-on: https://review.coreboot.org/15957
Tested-by: build bot (Jenkins)
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Omar Pakker
2016-07-31 19:17:27 +02:00
Martin Roth 4c72d3612b Remove extra newlines from the end of all coreboot files.
This removes the newlines from all files found by the new
int-015-final-newlines script.

Change-Id: I65b6d5b403fe3fa30b7ac11958cc0f9880704ed7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15975
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-31 18:19:33 +02:00
Julius Werner e9808b145f cbgfx: Use memset() for faster screen clearing if possible
cbgfx currently makes a separate function call (recomputing some values)
for every single pixel it draws. While we mostly don't care that much
about display speed, this can become an issue if you're trying to paint
the whole screen white on a lowly-clocked Cortex-A53. As a simple
solution for these extreme cases, we can build a fast path into
clear_screen() that just memset()s the whole framebuffer if the color
and pixel format allow it.

BUG=chrome-os-partner:54416
TEST=Screen drawing speed on Kevin visibly improves (from 2.5s to 3ms).

Change-Id: I22f032afbb86b96fa5a0cbbdce8526a905c67b58
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15524
Tested-by: build bot (Jenkins)
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-02 03:22:51 +02:00
Furquan Shaikh 49f7dd9982 libpayload/pci: Correct MASK macro names
BUG=chrome-os-partner:54563

Change-Id: I8ef1c595205fe46dd64357051eeb232e2bbbebc1
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15270
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-21 20:41:06 +02:00
Liangfeng Wu 8c7e416309 libpayload: usb: xhci: Support rockchip xHCI controller
1. Make the xHCI driver to support xHCI controller v1.1
2. And a new function xhci_ring_doorbell(), it aims to
   add a memory barrier before ringing the doorbell, to ensure
   all TRB changes are written to memory.

BRANCH=none
BUG=chrome-os-partner:52684
TEST=boot from USB on Kevin rk3399 platform

Change-Id: Ife1070d1265476d0f5b88e2acf3299fc84af5832
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 0c21e92
Original-Change-Id: I4e38e04dc3c7d32ee4bb424a473c70956a3c3ea9
Original-Signed-off-by: Liangfeng Wu <wulf@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/346831
Original-Commit-Ready: Brian Norris <briannorris@chromium.org>
Original-Tested-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15111
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-06-12 12:09:55 +02:00
Julius Werner 2c51572435 arm64: Add stack dump to exception handler
Some exceptions (like from calling a NULL function pointer) are easier
to narrow down with a dump of the call stack. Let's take a page out of
ARM32's book and add that feature to ARM64 as well. Also change the
output format to two register columns, to make it easier to fit a whole
exception dump on one screen.

Applying to both coreboot and libpayload and syncing the output format
between both back up.

Change-Id: I19768d13d8fa8adb84f0edda2af12f20508eb2db
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14931
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-24 20:51:28 +02:00
Julius Werner 2296479dfd libpayload: cbfs: Add cbfs_handle API for more fine-grained accesses
The libpayload CBFS APIs are pretty old and clunky, primarily because of
the way the cbfs_media struct may or may not be passed in and may be
initialized inside the API calls in a way that cannot be passed back out
again. Due to this, the only real CBFS access function we have always
reads a whole file with all metadata, and everything else has to build
on top of that. This makes certain tasks like reading just a file
attribute very inefficient on non-memory-mapped platforms (because you
always have to map the whole file).

This patch isn't going to fix the world, but will allow a bit more
flexibility by bolting a new API on top which uses a struct cbfs_handle
to represent a found but not yet read file. A cbfs_handle contains a
copy of the cbfs_media needed to read the file, so it can be kept and
passed around to read individual parts of it after the initial lookup.
The existing (non-media) legacy API is retained for backwards
compatibility, as is cbfs_file_get_contents() (which is most likely what
more recent payloads would have used, and also a good convenience
wrapper for the most simple use case), but they are now implemented on
top of the new API.

TEST=Booted Oak, made sure that firmware screens and software sync
worked okay.

Change-Id: I269f3979e77ae691ee9d4e1ab564eff6d45b7cbe
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14810
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-17 22:48:28 +02:00
Lee Leahy f92a98c56e coreboot_tables: Extend serial port description
Extend the serial port description to include the input clock frequency
and a payload specific value.

Without the input frequency it is impossible for the payload to compute
the baud-rate divisor without making an assumption about the frequency.
This breaks down when the UART is able to support multiple input clock
frequencies.

Add the UART_PCI_ADDR Kconfig value to specify the unique PCI device
being used as the console UART.  Specify this value as zero when the
UART is not on the PCI bus.  Otherwise specify the device using bus,
device and function along with setting the valid bit.

Currently the only payload to consume these new fields is the EDK-II
CorebootPayloadPkg.

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file:
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
   CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
   UEFIPAYLOAD.fd
*  Testing is successful when CorebootPayloadPkg is able to properly
   initialize the serial port without using built-in values.

Change-Id: Id4b4455bbf9583f0d66c315d38c493a81fd852a8
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14609
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-05-09 17:21:22 +02:00
Varadarajan Narayanan c1ae7e9183 libpayload: ipq40xx: Introduce timer and uart driver
BUG=chrome-os-partner:49249
TEST=None. Initial code not sure if it will even compile
BRANCH=none

Change-Id: Ibf2c91be93e2567cc1262b6fb84461eef51ab3e0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b87157138302b017e64a28417a22421c880c1bcb
Original-Change-Id: I16a8324d3c8ef4ee729f4509fda5bfe703b24ce4
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333304
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/14656
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 08:53:24 +02:00
Patrick Georgi 5dc87fe470 libpayload/arm64: Mark existing framebuffer as DMAable
If a framebuffer is already configured by coreboot, libpayload's
MMU tables didn't mark its memory DMAable (unlike when libpayload
set up its own framebuffer memory).

BRANCH=none
BUG=chrome-os-partner:52826
TEST=depthcharge's recovery screen is not corrupted anymore on kevin

Change-Id: I228a861b3fdcf1298a3cfa0a054214c78ed55e70
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 889e8358a0f2f504abd9910549aa68f3992bb4e8
Original-Change-Id: I7ba79151ccc1eb605f82e1869a74b539a6be5e99
Original-Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/341092
Reviewed-on: https://review.coreboot.org/14685
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 08:30:56 +02:00
Varadarajan Narayanan 8e0ffe2088 libpayload: xhci: Set MPS based on speed
BUG=chrome-os-partner:49249
TEST=Compiles and boots and detect USB storage
BRANCH=none

Change-Id: I9007399e1f785e6f1d2258225e3f7cc602053aed
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1db43f53973d2124e41186777caa829aa346ace3
Original-Change-Id: I943d19a3a7d785bd075073b57ba6388662d7df90
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333311
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14659
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 08:29:57 +02:00
Paul Kocialkowski d2ea674635 libpayload: Add nyan config
This adds a nyan libpayload config, that should fit all nyan devices.

Change-Id: I6b86a03054a7625534fd38ee6a21d3b91fb43589
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/14473
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 07:49:57 +02:00
Stef van Os c012428291 libpayload: time: split time.h from libpayload.h
Move time functions and prototypes from libpayload.h to time.h.
In a similar manner to other c libary headers, this change makes
porting existing applications to libpayload easier.

Change-Id: I71e27c6dddde6e77e0e9b4d7be7cd5298e03a648
Signed-off-by: Stef van Os <stef.van.os@prodrive-technologies.com>
Reviewed-on: https://review.coreboot.org/14437
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-04-21 23:08:52 +02:00
Martin Roth 41f0e0fd4d libpayload: disable EHCI & XHCI in defconfig-mips
drivers/usb/xhci.c and drivers/usb/ehci.c both require arch/barrier.h.

barrier.h is present for x86, arm, and arm64, but not for mips. This
is generating a build error after enabling USB by default on libpayload.

I believe that this slipped through the buiders due to them not getting
cleaned fully.  It was caught in the coverity scan and when setting up
a new build server.

Change-Id: Idd89409a048009c087ce2a787d96a1efd089157f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14391
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-04-18 14:24:21 +02:00
Stefan Reinauer 777028fd8a libpayload: Split off generic serial API from 8250 driver
There is a lot of generic code in the 8250 driver that should
be available for non-8250 systems with serial ports as well.

Change-Id: I67fcb12b5fa99ae0047b3cbf1815043d3919437e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14371
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-16 01:08:23 +02:00
Marcel Meißner cb672a5857 libpayload: Enable USB support by default
Most people use USB keyboards.

Change-Id: Ia7cf513059565db7b86190c4aae62d7a35392408
Signed-off-by: Marcel Meißner <mm-meissner@gmx.de>
Reviewed-on: https://review.coreboot.org/7540
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-04-14 19:48:16 +02:00
Jonathan Neuschäfer a4fbc385e0 libpayload/libc: Fix memset/sizeof usage
Since r is a pointer, memset(r, 0, sizeof(r)) would only zero the first
4 (or 8) bytes of the newly allocated struct align_region_t.

An alternative to this patch would be to use calloc, or introduce a new
zalloc (zeroed allocation; a single-element calloc) and use that.

Change-Id: Ic3e3487ce749eeebf6c4836e62b8a305ad766e7e
Found-by: Coverity (ID 1291160)
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/14244
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-04-06 13:33:07 +02:00
huang lin 7b9bca0b2b libpayload: mmu: Initialize the base 4GiB as device memory
This allows to accommodate different platforms' default
configurations, memory configuration is fine tuned later during boot
process.

BUG=chrome-os-partner:51537
BRANCH=none
TEST=none yet, the full stack of patches boots fine on EVB

Change-Id: I39da4ce247422f67451711ac0ed5a5e1119ed836
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 97a9a71ade4df8a501043f9ae58463a3135e2a4f
Original-Change-Id: I39da4ce247422f67451711ac0ed5a5e1119ed836
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/332384
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/13914
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-04-05 13:34:47 +02:00
Martin Roth 6959f5c915 libpayload: update junit.xml target, clean up output
- Copy each config in configs/ to the junit_config, update each,
in turn, and clean up when done.  This avoids updating the saved
config files and creating dirty files in git.
- Use 'make olddefconfig' instead of 'yes "" | make oldconfig'
- Update clean target to remove junit_config file
- Update distclean target to remove junit.xml

Change-Id: Ib023eb3197f2d8806c73c9c18464157ce3de958f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14164
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-25 18:18:27 +01:00
Stefan Reinauer 94534b3132 libpayload: recreate config files
Add all the default options with:

  for i in configs/*
  do
    cp $i .config
    make savedefconfig
    mv defconfig $i
  done

This also switches to minimal config files instead of the full
configuration files that were previously checked in.

Change-Id: If18a32eca4df9e1dfeb0e212b652d972cea8e4b8
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14077
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
2016-03-16 17:56:32 +01:00
Stefan Reinauer 821844534c libpayload: Move base address, stack and heap size to Kconfig
This will allow more payloads to use the standard linker script
instead of implementing their own.

Change-Id: Ie60120769829f427ceb722109d85859b61dbde31
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14074
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15 20:53:38 +01:00
Stefan Reinauer 347a7529aa libpayload: Make comment into help text
Change-Id: I8c8669e73e335e12cb3785cf84b878c305dd5929
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14068
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15 20:53:27 +01:00
Stefan Reinauer 805d44f2c7 libpayload: Fix ARM workaround code
_LDFLAGS+="foo" did not work in my shell (bash on Ubuntu 15.10),
so change it to _LDFLAGS="$_LDFLAGS foo". I'm mildly surprised
that this ever worked.

Change-Id: I59c10f34992240c6df2ec7f24aebc6daafb76493
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14076
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15 18:24:41 +01:00
Stefan Reinauer f0acf47ae1 libpayload: Add comment about ARM64 exception stack
Change-Id: I8b74cbf6bdde32c90ad0510e14e899711269e57f
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14075
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15 18:24:30 +01:00
Stefan Reinauer 1e6b86b8b6 libpayload: Move MEMMAP_RAM_ONLY to generic options
MEMMAP_RAM_ONLY is not an architecture specific option,
hence move it out of the architecture specific menu.

Change-Id: Iaeef03ed8cbff930a580ad03b1e712087b48714e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14071
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15 18:23:11 +01:00
Stefan Reinauer 8fda04449f libpayload: Drop CONFIG_LP_CHROMEOS
This is adding complexity to the code more than it saves
space, plus some of the tables could potentially be interesting
outside of the ChromeOS context.

Change-Id: I4bf24608f3e26d3b7871a5031ae8f03bc2c8c21f
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14070
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15 18:22:58 +01:00
Stefan Reinauer 96d14ac1c9 libpayload: Unify defconfigs
Bring defconfig and defconfig-tinycurses in sync, so that
defconfig and defconfig-tinycurses only differ in the selection
of the curses implementation.

Change-Id: I739c5122b5aaaa2681055c845905721a0b2a11c1
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14069
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-15 18:22:44 +01:00
Martin Roth 6116f369e9 codebase: Change makefile $(shell pwd) commands to $(CURDIR)
- Change the makefile command $(shell pwd) to $(CURDIR) to find the
current directory without going out to the shell.

Change-Id: I4890eba6129630acd2883b92de77308d39949443
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13967
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-03-11 18:48:06 +01:00
Julius Werner 09f2921b5d cbfs: Add LZ4 in-place decompression support for pre-RAM stages
This patch ports the LZ4 decompression code that debuted in libpayload
last year to coreboot for use in CBFS stages (upgrading the base
algorithm to LZ4's dev branch to access the new in-place decompression
checks). This is especially useful for pre-RAM stages in constrained
SRAM-based systems, which previously could not be compressed due to
the size requirements of the LZMA scratchpad and bounce buffer. The
LZ4 algorithm offers a very lean decompressor function and in-place
decompression support to achieve roughly the same boot speed gains
(trading compression ratio for decompression time) with nearly no
memory overhead.

For now we only activate it for the stages that had previously not been
compressed at all on non-XIP (read: non-x86) boards. In the future we
may also consider replacing LZMA completely for certain boards, since
which algorithm wins out on boot speed depends on board-specific
parameters (architecture, processor speed, SPI transfer rate, etc.).

BRANCH=None
BUG=None
TEST=Built and booted Oak, Jerry, Nyan and Falco. Measured boot time on
Oak to be about ~20ms faster (cutting load times for affected stages
almost in half).

Change-Id: Iec256c0e6d585d1b69985461939884a54e3ab900
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13638
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-02-22 21:38:37 +01:00
Aaron Durbin 152e5a03a1 libpayload: honor TSC information under CONFIG_LP_TIMER_RDTSC
When CONFIG_LP_TIMER_RDTSC is enabled honor the TSC information
exported in the coreboot tables as the cpu_khz frequency. That
allows get_cpu_speed() not to be called which currently relies
on the 8254 PIT. As certain x86 platforms allow that device
to be optional or turned off for power saving reasons, allow
a path where get_cpu_speed() is no longer called. Additionally,
this approach also allows the libpayload to not duplicate logic
that already exists in coreboot.

BUG=chrome-os-partner:50214
BRANCH=glados
TEST=Confirmed in payload TSC frequency is honored instead of
     using get_cpu_speed().

Change-Id: Ib8993afdfb49065d43de705d6dbbdb9174b6f2c4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13671
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-02-19 19:50:25 +01:00
Patrick Georgi d4adf58e03 libpayload: use 32bit access when accessing 4byte wide uart registers
This fixes serial on rk3288.

Change-Id: I3dbf3cc165e516ed7b0132332624f882c0c9b27f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13636
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2016-02-09 21:53:42 +01:00
Ruilin Hao 5bcbd11b0d libpayload: Add timer driver for armada38x
Add timer driver for armada38x

BUG=chrome-os-partner:47462
TEST=emerge-cyclone libpayload
BRANCH=tot

Change-Id: Iefb6d1fcb907edb54d55ba8addfb66329af6c3c7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cd467160ecab050a541a445c2afab9e6bc625635
Original-Change-Id: Id42bafdbc34295b6f8afe5610fb3bab0e0e1b6e8
Original-Signed-off-by: Ruilin Hao <rlhao@marvell.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313343
Original-Commit-Ready: Kan Yan <kyan@google.com>
Original-Tested-by: Kan Yan <kyan@google.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Yuji Sasaki <sasakiy@chromium.org>
Reviewed-on: https://review.coreboot.org/13114
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-02-04 11:32:22 +01:00
Daisuke Nojiri d201e8c38a cbgfx: add error code to cbgfx_init
cbgfx_init can fail for multiple reasons. These codes help debugging
cbgfx_init.

BUG=chromium:502066
BRANCH=tot
TEST=Tested on Glados

Change-Id: Ifaa8d91b058bd838a53faf5d803c0337cb1e082c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4caf2496f3583e133f3f216ec401515c267e6e7b
Original-Change-Id: I84f60dd961db47fa426442172ab19676253b9495
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/315550
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12930
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-01-14 18:44:20 +01:00
Daisuke Nojiri 6d2c7226cb libpayload: add archive.h
archive.h is a header file for the programs which need to parse an archive
created by 'archive' tool. See archive.h for the format description.

BUG=chromium:502066
BRANCH=tot
TEST=Tested on Glados

Change-Id: I2bee9d7c12b0e1bce1529dfef360c5fa4ce0872d
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/311201
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://review.coreboot.org/12734
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-16 19:00:53 +01:00
Martin Roth 5a8d619a1c libpayload/configs/config.veyron: Use CONFIG_LP_8250_SERIAL_CONSOLE
- Update to use the CONFIG_LP_8250_SERIAL_CONSOLE instead of the removed
CONFIG_LP_8250_MMIO32_SERIAL_CONSOLE.
- CONFIG_LP_LZ4 and CONFIG_LP_PL011_SERIAL_CONSOLE are set to the
default values for these new config options.

CONFIG_LP_8250_MMIO32_SERIAL_CONSOLE was removed in
commit 4d5317e5 (libpayload: Remove redundant 8250 MMIO32 UART driver)

Change-Id: I97461c5e0c14075dcf8a35c96a0b0f1651e2e8e4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12654
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06 22:24:30 +01:00
Martin Roth 2a27a85809 libpayload/configs/config.purin: Use CONFIG_LP_8250_SERIAL_CONSOLE
- Update to use the CONFIG_LP_8250_SERIAL_CONSOLE instead of the removed
CONFIG_LP_8250_MMIO32_SERIAL_CONSOLE.
- CONFIG_LP_LZ4 and CONFIG_LP_PL011_SERIAL_CONSOLE are set to the
default values for these new config options.

CONFIG_LP_8250_MMIO32_SERIAL_CONSOLE was removed in
commit 4d5317e5 (libpayload: Remove redundant 8250 MMIO32 UART driver)

Change-Id: I2775c3676d5f458a4c31fe0c1d571bc2b9221a5c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12653
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-06 22:23:12 +01:00
Daisuke Nojiri 03688ec1da libpayload: get cbfs offset & size for default media from lib_sysinfo
This change revives the path which was made inert by CL:308520. When
media == CBFS_DEFAULT_MEDIA, cbfs_get_file replaces it with a pointer
to a default media. Thus, get_cbfs_range does not set cbfs offset &
size from lib_sysinfo.

BUG=chrome-os-partner:47772
BRANCH=tot
TEST=Tested on Jerry and Glados

Change-Id: I012f7871336dd24b8eada5c96c4d72117921b0d2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 279ba344788b4ba85f500e6cfcca8199af6d0a89
Original-Change-Id: I7f0798881519026a23d0801d0a790332ab878ff0
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/313205
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12583
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-03 14:16:34 +01:00
Alexandru Gagniuc 4d5317e5a4 libpayload: Remove redundant 8250 MMIO32 UART driver
The more generic 8250 driver can handle both port-mapped and memory-
mapped 8250-compatible UARTs, with different register sizes. Thus, a
separate driver for MMIO32 is not needed.
The generic 8250 driver was tested to work for both output and input,
on Apollolake SoC, which only presents an MMIO32 UART.

Change-Id: Idab766588ddd097649a37de92394b0078ecc660a
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: https://review.coreboot.org/12524
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-11-28 19:19:31 +01:00
Stefan Reinauer 5bbc5e5e0d libpayload: PDCurses: Remove trailing whitespace
find . -type f |xargs perl -pi -e 's, *$,,'
find . -type f |xargs perl -pi -e 's,	*$,,'

Change-Id: I62c2bc15b7c395a68b68422e701edf98b08e27c6
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12399
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-20 16:27:36 +01:00
Furquan Shaikh fe35623f20 libpayload: udc/dwc2: Ignore setup packet in check for queue empty
during shutdown

DWC2 UDC controller always requires an active packet to be present in
EP0-OUT to ensure proper operation of control plane. Thus, during
shutdown ignore EP0-OUT for queue empty check if only 1 packet is
present.

BUG=b:24676003
BRANCH=None
TEST=Compiles successfully. "fastboot reboot-bootloader" reboots
device without timeout in udc shutdown.

Change-Id: Iafe46c80f58c4cd57f8d58f060d805b603506bbd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4e7c27d849c0411aae58e60a24d8170a27ab8485
Original-Change-Id: Ifa493ce0e41964ee7ca8bb3a1f4bb8726fa11173
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311257
Original-Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12413
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2015-11-13 00:53:02 +01:00
Furquan Shaikh 1dcb10eeb6 libpayload: queue: Add a helper macro for checking singleton queue
Check if the simple queue consists of only 1 element.

BUG=b:24676003
BRANCH=None
TEST=Compiles successfully.

Change-Id: Ib257a5e6b9042b42c549f8ad8b943e3b75fd8c9c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5435d6fec1c4fbb4c04ba5b8c15caff9ee4e50f0
Original-Change-Id: I7a8cb9c4e7e71956e85e65b3e7b8e0af4d354110
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311256
Original-Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12412
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2015-11-13 00:52:58 +01:00
Stefan Reinauer 4f85a1eb76 libpayload: Rename PDCurses-3.4 to PDCurses
Change-Id: If881ec130833c7e7e62caa3d31e350a531f5bc8e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12398
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-11 21:38:48 +01:00
Stefan Reinauer 2ea24dabd6 PDCurses: Don't hard code version number
Don't hard code the PDCurses version number in every file
added to the object list.

Change-Id: Ic2e9230b7e3089c60dd7f442e3ea7baffb4aa400
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12397
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-11-11 21:38:34 +01:00
Furquan Shaikh bf54c2cc5c libpayload/udc: dwc2: Add handler for add_strings
BUG=b:24676003
BRANCH=None
TEST=Compiles successfully. fastboot devices shows serial number for
shark.

Change-Id: I61d6c168fa458d1f880bc566db997aa5d6398361
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 45b286b318281aea9a4b0362c9259d748b66fd28
Original-Change-Id: Ib9cc22de9daa6c5ec9cde1e62c6f5f768e946069
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/310984
Original-Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12348
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-10 14:10:39 +01:00
Furquan Shaikh 3d6c95c1cd libpayload/udc: dwc2: Add timeout for shutdown operation
BUG=b:24676003
BRANCH=None
TEST=Verified that udc shutdown returns after the timeout.

Change-Id: I5df598c4eddecbecb353343ef5a4e44eae4fc20b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 268913f21adea9969c9f88e3cb759341a60719f0
Original-Change-Id: I3ee059791d6e821f83f9ac41fd7c5385bd60e21e
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/310983
Original-Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12347
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2015-11-10 14:10:02 +01:00
Rajmohan Mani 1528ffa57c libpayload: xhci: Add delay to get reset working more reliably
Existing Intel xHCI controllers require a delay of 1 ms,
after setting the CMD_RESET bit in command register, before
accessing any HC registers. This allows the HC to complete
the reset operation and be ready for HC register access.
Without this delay, the subsequent HC register access,
may result in a system hang, very rarely.

Verified CherryView / Braswell platforms go through over
1000 warm reboot cycles (which was not possible without
this patch), without any xHCI reset hang in depthcharge.

BRANCH=None
BUG=None
TEST=Verified CherryView / Braswell platforms go through
over 1000 warm reboot cycles, without any xHCI reset hang
in depthcharge.

Change-Id: I8eff5115ca52738bdcf8bc65fbfb2a5f60a0abe1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3e7ea70df36e3bf35a6ee1297640900ee76bfdac
Original-Change-Id: Id681a19d0eedb0e2c29e259c5467bcde577e3460
Original-Signed-off-by: Rajmohan Mani <rajmohan.mani@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/310022
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/12325
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-11-05 17:40:30 +01:00
Patrick Georgi 102245fbed libpayload: Avoid confusing usb debug output in dwc2 driver
enqueue_packet already runs start_ep_transfer, which enqueues the next
job. It's pretty much guaranteed that the port will look busy.

BUG=none
BRANCH=none
TEST=no spurious ep 0-0 busy messages

Change-Id: I9cbfa7b51dd37564262295ddbcdd0755da40c05b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8997dbd78dc363334f4e22eaa61f25de1449ffba
Original-Change-Id: I8a39713fc1d6f16b80284e0f21dc95685716a9b7
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/308763
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: yunzhi li <lyz@rock-chips.com>
Reviewed-on: http://review.coreboot.org/12259
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-05 17:39:58 +01:00
Patrick Georgi b791799d9a libpayload: Fix building dwc2 UDC driver with debug enabled
hexdump() now takes a pointer instead of an int-containing-an-address.

BUG=none
BRANCH=none
TEST=building with USB_DEBUG works

Change-Id: Idd0c43031a212c8f3b6489f533c488805d98d6a9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8660f6091bb124eeabe73302e8c7f1a8e46324f1
Original-Change-Id: I266efcb8b939d6da104ad05a3e79a78065c60beb
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/308762
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: yunzhi li <lyz@rock-chips.com>
Reviewed-on: http://review.coreboot.org/12258
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-05 17:39:52 +01:00
Patrick Georgi f86d035105 libpayload: Allow non-default CBFS media
CBFS requests were always fulfilled using the CBFS specified in
cbtables. That's a great policy when default requests are sought, but
not so great when the user deliberately asked for something else.

So check if they want default CBFS media information, otherwise ignore
cbtables data.

BUG=chromium:445938
BRANCH=none
TEST=none

Change-Id: I01b63049eebfba6f467808ac84ef77385840c204
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 621c916ab14c0de4bae3dde09c05060c4f3c63c5
Original-Change-Id: Ia4a8848fd7db9d9a2bf9f5c226566fe3936ff543
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/308520
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12232
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-05 17:39:42 +01:00
Patrick Georgi a73b93157f tree: drop last paragraph of GPL copyright header
It encourages users from writing to the FSF without giving an address.
Linux also prefers to drop that and their checkpatch.pl (that we
imported) looks out for that.

This is the result of util/scripts/no-fsf-addresses.sh with no further
editing.

Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11888
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-10-31 21:37:39 +01:00
Julius Werner 8db7e6702b libpayload: usbmsc: Add small delay during initialization to fix CZ60
We found that some SanDisk Cruizer Glide CZ60 sticks (confirmed on 16GB
and 64GB versions) have a problem responding to our first GET_MAX_LUNS
request right after they received their SET_CONFIGURATION. They will
continually return a NAK until the host gives up (which is 2
user-noticable seconds for us). Adding a small delay of about 15us seems
to be enough to fix the issue, but let's do 50 to be save.

Confirmed with both MT8173 and Intel LynxPoint XHCI controllers.

BRANCH=None
BUG=chrome-os-partner:45473
TEST=No notable delay before detecting stick on Oak and Falco.

Change-Id: Ib03944d6484de0ccecbb9922d22666f54c9d53dd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 589f19a901275fb8b00de4595763a7d577bed524
Original-Change-Id: I95c79fe40d3ad79f37ce2eb586836e5de55be454
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/308980
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/12229
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-29 21:06:45 +01:00
Patrick Georgi 564fbbeac9 libpayload: Fix building dwc2 UDC driver
Change Ie54699162 changed a structure's name and field names and we
didn't notice. Adapt.

BUG=none
BRANCH=none
TEST=building with UDC_DWC2 works

Change-Id: I592ebc29b2a08a23e6dbc9d2186807cbbbbca330
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3dda8ad5ffc36593d8b8fd6664a7f9b4816f0f93
Original-Change-Id: I4a065de0f4045a01bef1dc9fbb2e0578b5508518
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/308791
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/12228
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-10-29 21:06:38 +01:00
Daisuke Nojiri 2ccb280f51 cbfs: read cbfs offset and size from sysinfo
This change allows libpayload to read cbfs offset and size from sysinfo.
Legacy way of locating cbfs reagion is still supported in case sysinfo
doesn't store the offset and the size.

BUG=none
BRANCH=master
TEST=tested on samus and smaug

Change-Id: I86434fd249467e7c90d59d6b82f0e6c514bc2d05
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 548a74b7a0758c3f9ba6809425d0fb9c6a5e9d7c
Original-Change-Id: I190d5545a65228483204bf1aa1cbf5a80db31ae0
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/296993
Original-Commit-Ready: Daisuke Nojiri <dnojiri@google.com>
Original-Tested-by: Daisuke Nojiri <dnojiri@google.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11557
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-28 22:26:17 +01:00
Jason A. Donenfeld a5c5db37ee cbgfx: Fix spelling of calculate_position()
Change-Id: Ib0dc14b197091450596ad01a924539b0e69acd68
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Reviewed-on: http://review.coreboot.org/12216
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-28 17:09:59 +01:00
Patrick Georgi 990ae70698 libpayload/libcbgfx: Add license headers
Change-Id: I09a9d9eef9d8fe45cdd4d68d29b8d662fe5956e1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/12164
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-27 16:49:10 +01:00
Daisuke Nojiri dcc63b6cb7 cbgfx: remove load_bitmap
load_bitmap is no longer needed.

BUG=none
BRANCH=master
TEST=Tested on Samus
CQ-DEPEND=CL:305589

Change-Id: I4e598ade20a5d49850f9ad0f13681ea5d16cd8c7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 125bbc98195cbb8378ba0e4c7fece85ffca4cdfa
Original-Change-Id: I64d685f7a6367b03455ae2a206b9936613614a24
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/305517
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11930
Tested-by: build bot (Jenkins)
2015-10-27 15:22:53 +01:00
Daisuke Nojiri 20b7907041 cbgfx: add get_image_dimension
get_image_dimension returns the width or height of the image projected on
canvas.

This is necessary for example when two images of different lengths have to
be placed side by side in the center of the canvas and the widths of the
images must be adjusted according to the height.

BUG=chromium:502066
BRANCH=tot
TEST=Tested on Samus

Change-Id: I119c83891f48046e888b6b526e63348e74f8b77c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: d1a97f0492eb02f906feb5b879b7b43518dfa4d7
Original-Change-Id: Ie13f7994d639ea1556f73690b6b6b413ae64223c
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/304113
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11929
Tested-by: build bot (Jenkins)
2015-10-27 15:22:41 +01:00
Daisuke Nojiri 9aed1465d7 cbgfx: make the code more descriptive
This change makes the code in graphics.c more descriptive and readable.
Especially, it makes expressions for scale calculation look what they
are meant to do. It also includes:

- Rename variables (struct fraction, dim_org, etc.) for more consistency
- Add more input validation (div-by-zero, etc.)

BUG=chromium:502066
BRANCH=master
TEST=Tested on Samus
CQ-DEPEND=CL:304860

Change-Id: I2694912bb7b6017d5655de2fd655b95432addb22
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 0863dc3ee925d3a05c83c66397b19a57f5478ef3
Original-Change-Id: Id8e349b8e09082fb84c3e1a984617f916e16c518
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/304861
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11928
Tested-by: build bot (Jenkins)
2015-10-27 15:22:33 +01:00
Daisuke Nojiri a11e3ff160 cbgfx: add pivot option to draw_bitmap
This change adds 'pivot' option to draw_bitmap. It controls the point of the
image based on which the image is positioned. For example, if a pivot is set
to the center of the image horizontally and vertically, the image is
positioned using pos_rel as the center of the image.

This feature is necessary, for example, to place a text image in the center
of the screen because each image has a different width depending on the
language.

This change also makes draw_bitmap accept both horizontal and vertical size.
If either of them is zero, the other non-zero value is used to derive the
size to keep the aspect ratio.

Specifying the height is necessary to keep font sizes the same when drawing
text images of different lengths.

draw_bitmap_direct is a variant of draw_bitmap and it draws an image using
a native coordinate and the original size (as opposed to the location and
the size relative to the canvas).

CL:303074 has real use cases.

BUG=none
BRANCH=tot
TEST=Tested on Samus

Change-Id: I5fde69fcb5cc9dc53e827dd9fcf001a0a32748d4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 82a0a8b60808410652552ed3a888937724111584
Original-Change-Id: I0b0d9113ebecf14e8c70de7a3562b215f69f2d4c
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/302855
Reviewed-on: http://review.coreboot.org/11927
Tested-by: build bot (Jenkins)
2015-10-27 15:22:24 +01:00
Daisuke Nojiri f86515244a cbgfx: use bilinear interpolation to scale bitmap
This change replaces the current scaling algorithm (nearest neighbor) used
for bitmap rendering with the bilinear interpolation, which has much better
reproduction.

BUG=none
BRANCH=tot
TEST=Tested on Samus

Change-Id: I02520883debb7db40ffc19d4480244e0acabc818
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 764b383c1763a022728f2b2d9fb90e27c9e32e94
Original-Change-Id: I0ddd184343428904d04d8a76fe18a885529c7d3d
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/302195
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: http://review.coreboot.org/11926
Tested-by: build bot (Jenkins)
2015-10-27 15:22:16 +01:00
Daisuke Nojiri bed16d9706 cbgfx: add load_bitmap
This change adds load_bitmap API, which loads a bitmap file from cbfs
and returns a pointer to the image data.

BUG=none
BRANCH=tot
TEST=Tested on Samus

Change-Id: I7d7874f6f68c414dc877a012ad96c393e42dc35e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 9d33e713a0cf6bd1365418dad989e47e86db01e4
Original-Change-Id: Idbf9682c2fa9df3f0bd296ca47edd02cd09cfd01
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/302194
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: http://review.coreboot.org/11925
Tested-by: build bot (Jenkins)
2015-10-27 15:22:10 +01:00
Daisuke Nojiri fed269b1c4 cbgfx: add clear_screen
clear_screen clears the screen with the specified color.

BUG=none
BRANCH=tot
TEST=Tested on Samus

Change-Id: I45e61c67485dbdbe15e2b602718232bc6382ad00
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 1ab04e2cc8d3c3e36e4eb41d9e7b0fdc25595200
Original-Change-Id: I1b3890b9e8ca52e796f417b5f41d4fa02a97a255
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/301451
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: http://review.coreboot.org/11924
Tested-by: build bot (Jenkins)
2015-10-27 15:22:00 +01:00
Daisuke Nojiri dd49eccb50 cbgfx: allow draw_bitmap to render outside canvas
This change allows draw_bitmap to draw an image outside the canvas
with the original size if the scale parameter is zero. This is used
for example when drawing a splash screen which has to be positioned
at a pixel perfect location.

BUG=none
BRANCH=master
TEST=Draw pictures and boxes on Samus and Ryu

Change-Id: Ia2d8799184d1aa192e2c50850e248bee8f234006
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 45d4717fe5c3e3554bd79b63ade490d88cf00bbe
Original-Change-Id: I48aa21122cfc2ee43bcb1b8f87b00c66abdc230e
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295961
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11923
Tested-by: build bot (Jenkins)
2015-10-27 15:21:53 +01:00
Daisuke Nojiri 09ad206cda cbgfx: add draw_bitmap
draw_bitmap renders a bitmap image on screen with position and sizes
scaled relative to the screen. images are scaled up or down by nearest
neighbor interpolation.

BUG=chrome-os-partner:43444
BRANCH=tot
TEST=drew bitmap images on Samus

Change-Id: Ib599acc85b25626a6aed1fa9884ecd8e169bb860
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c910c9cdb7efc53aace067bd081aeefc07556811
Original-Reviewed-on: https://chromium-review.googlesource.com/290302
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Change-Id: Ib599acc85b25626a6aed1fa9884ecd8e169bb860
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295532
Reviewed-on: http://review.coreboot.org/11584
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-27 15:21:42 +01:00
Daisuke Nojiri 3f66398ef8 cbgfx: coreboot graphics library
This change introduces cbgfx, a graphics library, which provides APIs for
drawing basic shapes, texts, graphic data, etc. on a screen.

BUG=chrome-os-partner:43444
BRANCH=tot
TEST=Drew boxes by draw command of depthcharge cli on Samus

Change-Id: I6019e5998e65dca3ab4785a90669b5db02463d2e
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 5b3ebce8eae91be742e4f977d3407d24e1537580
Original-Reviewed-on: https://chromium-review.googlesource.com/290301
Original-Reviewed-by: Stefan Reinauer <reinauer@google.com>
Original-Change-Id: I10db27715cb907bdc451a33ed99d257e3af241b7
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/291065
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11408
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-27 15:21:31 +01:00
Shawn Nematbakhsh ff5d0b2518 libpayload: usb: Retry get_descriptor() on failure
Certain Lexar USB disks may fail during the first calls to
get_descriptor(..., DT_CFG, ...) for unknown reasons. Therefore, make
several attempts before giving up.

BUG=chromium:466758
TEST=Manual on Samus. Go to recovery mode, verify that Lexar LJDS70 USB
stick is bootable.
BRANCH=None

Change-Id: I476ac22f9c4f844c60ebc6e53af8c144d70bb9d4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 93a0570b343479dd22506ad4d7961f0ea4251f8c
Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Change-Id: Ie581c7c71c53816065c7f59202581888a79e445e
Original-Reviewed-on: https://chromium-review.googlesource.com/302403
Original-Commit-Ready: Shawn N <shawnn@chromium.org>
Original-Tested-by: Shawn N <shawnn@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/12133
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-27 15:00:16 +01:00
Patrick Georgi 744729a4f0 libpayload: Add ptrdiff_t typedef
vboot2 in payloads (eg depthcharge) needs it.

Change-Id: I4e79ae29cc282c8680f21686befd35c4ff461b3a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/11922
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-10-20 16:50:25 +02:00
Paul Menzel dc1b3c162e libpayload/Kconfig: Use official spelling for TinyCurses
TinyCursess is officially spelled in CamelCase [1].

[1] https://github.com/tommyettinger/TinyCurses

Change-Id: I7e0aa5af54140796a981c0f4c58950b25fdd67ba
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11727
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-17 06:53:52 +00:00
Paul Menzel aa98eec316 libpayload/configs: Add default configuration with TinyCurses enabled
Change-Id: Ib057e2b5f15b8d5bcdf45666f8761614317d25ee
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/11726
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-17 06:53:37 +00:00
Patrick Georgi 78517f3a45 libpayload: Add data structures for hashes in file attributes
Taken from cbfstool.

Change-Id: I4387900517dbfb1aa51ae6f679e26d0cf5b2acf8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/11808
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-11 12:36:24 +00:00
Nico Huber bda38eece8 libpayload: Check for CBFS_DEFAULT_MEDIA in cbfs_get_file_content()
The error-prone interface of cbfs_get_file_content() led to another
possible NULL dereferencing. So check for CBFS_DEFAULT_MEDIA here
like the other functions do.

Change-Id: Ib8732160d389e9ecceb44f28be0e7de9a1d66e04
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/11796
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-05 15:23:54 +00:00
Nico Huber ac1f4b86f4 libpayload: Fix possible NULL deref in cbfs_get_file_content()
Change-Id: I2e10ccac3248717d90838ca721cc691de792b507
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/11780
Tested-by: build bot (Jenkins)
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
2015-10-02 19:19:32 +00:00
Jimmy Huang c159a0ec4a arm64: mmu: Prevent CPU prefetch instructions from device memory
Set XN bit of block upper attribute to device memory in mmu. CPU may
speculatively prefetch instructions from device memory, but the IO
subsystem of some implementation may not support this operation. Set
this attribute to device memory mmu entries can prevent CPU from
prefetching device memory.

BRANCH=none
BUG=none
TEST=build and booted to kernel on oak-rev3 with dcm enabled.

Change-Id: I52ac7d7c84220624aaf6a48d64b9110d7afeb293
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7b01a4157cb046a5e75ea7625060a602e7a63c3c
Original-Change-Id: Id535e990a23b6c89123b5a4e64d7ed21eebed607
Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/302301
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/11722
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-28 09:36:32 +00:00
Daisuke Nojiri 9dcf457707 cbfs: fix debug message
BUG=none
BRANCH=tot
TEST=built for Samus with debugging enabled

Change-Id: I0b555d018f8c2eb1b51519a6227298c8d5d58a42
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5908e4b8ffc66e6ecc7cae78cf10055fbd727c81
Original-Change-Id: Ifd049111fee540789dabb1d7653568b80405b77d
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/302131
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11713
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-28 09:33:20 +00:00
Patrick Georgi eb33b3f80e libpayload: provide cbfs_file_find_attr()
cbfs_file_find_attr(file, tag) finds the first attribute of file with
the given tag.

Change-Id: I78ee3b996b4b086605244c5d7d57ef7e3fc1db47
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11678
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2015-09-17 20:13:47 +00:00
Daisuke Nojiri d66f1da846 libpayload: allow compression at file header level
Decompression is handled transparently within cbfs_get_file_content:

	const char *name = "foo.bmp";
	void *dst = cbfs_get_file_content(media, name, type, NULL);

To keep things consistent, a couple of API changes were necessary:
- cbfs_get_file_content always returns a copy of the data, even for
  uncompressed files. It's the callers responsibility to free the
  memory.
- same for cbfs_load_payload and cbfs_find_file.
- cbfs_load_optionrom doesn't take a "dest" argument anymore but always
  returns a copy of the data, for compressed and uncompressed files.
  Like with cbfs_get_file_content, the caller is responsible to free it.
  It also decompresses based on extended file attributes instead of the
  cbfs_optionrom subheader that libpayload specified but that (AFAIK)
  nobody ever used, given that there's not even tooling for that.

Change-Id: If959e3dff9b93c6ae45ec7358afcc7840bc17218
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10938
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2015-09-17 18:52:56 +00:00
Daisuke Nojiri 5c6dc72501 libpayload: rename cbfs variable from name to vardata
The dynamically sized region after struct cbfs_file doesn't contain only
the file name anymore.

Change-Id: I3241cb2f0cbec3fcf4d3c27d638e2847e43f4761
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11676
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17 18:52:41 +00:00
Patrick Georgi 377d1db57d libpayload: bring in file attribute support from cbfstool
This comes from cbfstool (GPL) into libpayload (BSD-l), but I could have
just as well written it in libpayload first.

Change-Id: I86baefe5c299125a4733fa20523efd5d06de7182
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11675
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-17 18:48:10 +00:00
Yunzhi Li 87c9f0eaa9 libpayload: usb: dwc2: check device connect state before enable channel
If the device has already been disconnected then we shouldn't enable
host channel to start any transfer, otherwise this channel goes into
an odd state the channel is enabled but can not be disabled by set
hcchar.chdis=1. So we need check the device connect status before
enable channel.

BRANCH=None
BUG=chrome-os-partner:44534
TEST=None

Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ae3e690b2cd4a9ea8b5766ac873b0e00bf3a23de
Original-Change-Id: Ib3ecf486649ca11b302144f9c00a5e88424e90fa
Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/298402
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Lin Huang <hl@rock-chips.com>
Original-Tested-by: Lin Huang <hl@rock-chips.com>
Original-(cherry picked from commit ea96f947b5304fdde2e0991d23febaeba209dde1)
Original-Reviewed-on: https://chromium-review.googlesource.com/299398
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>

Change-Id: Idf48ffbc4c2794900e09dec6b2e34e33b21f87b4
Reviewed-on: http://review.coreboot.org/11662
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17 14:18:30 +00:00
Yunzhi Li a881000cd1 libpayload: usb: dwc2: fix hub hot-plug bug
When disconnect is detected in dwc2_split_transfer() the split
configuration registers should be cleared before return.

BRANCH=None
BUG=chrome-os-partner:44534
TEST=On Jerry, usb hot plug works with devices behind hubs

Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 37594d8b4490b6d393d19d17d8e497db7de8817d
Original-Change-Id: Ie1eecec067305874513c6ceb95df4240dc393cd6
Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/295625
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Lin Huang <hl@rock-chips.com>
Original-Tested-by: Lin Huang <hl@rock-chips.com>
Original-(cherry picked from commit d543e14cdc73bd549dd553c8d1d07672a1307981)
Original-Reviewed-on: https://chromium-review.googlesource.com/299700
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>

Change-Id: Ib4604097743f2f9d763b29ee27f3bc1788a85a62
Reviewed-on: http://review.coreboot.org/11661
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17 14:18:08 +00:00
Nico Huber 66cc843f3d libpayload: Revive ffs()
Revive ffs() in a more fancy way (that is more likely to be accepted).
We dropped it in
  7a8a4ab lib: Unify log2() and related functions
but there is at least one user: flashrom.

Change-Id: I4e3fc15816b778e640bceea0d89cd9624d271c2e
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/11591
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-09-10 20:11:33 +00:00
Nico Huber a7c609c262 libpayload: Fix merge of PL011 UART support
Wished I hadn't seen that. Git saw the conflict (file was gone), both
committer and reviewer thought it would be a good idea to re-add it as
dead code (see 558e9b5: libpayload: Add minimal support for PL011 UART).

Change-Id: Ifea8113fbc59e0463eaedb86b976f54ec11113a9
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/11604
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-09-10 09:19:11 +00:00
Nico Huber 602a82af7c libpayload: Add missing autoconf dependency
With new version of kconfig we have to trigger [silent]oldconfig each
time .config changed. We missed that, because config.h had no dependen-
cies.

Change-Id: I9f0dd8adbc3aa434a18cb4815b1ccbd1f6e7847b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/11603
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-09-10 09:18:12 +00:00
Daisuke Nojiri ccda446e52 video_printf: align text
This change allows video_printf to left/center/right-align text depending on
the enum value provided by the caller. This is useful especially because usually
the length of formatted string is unknown before calling video_printf.

BUG=none
BRANCH=smaug
TEST=drew fastboot screens on Smaug
CQ-DEPEND=CL:296460

Reviewed-on: https://chromium-review.googlesource.com/292929
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 436f05f60c1b88626740a35913e3ad37b5c777a3)
Change-Id: If1d50b7d8ddaa86eddc1618946756184cb87bfe1
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/295413
Reviewed-on: http://review.coreboot.org/11583
Tested-by: build bot (Jenkins)
2015-09-08 11:51:55 +00:00
Daisuke Nojiri abe03d25e2 video: add video_printf
video_printf prints strings on the screen with specified foreground and
background color.

BUG=none
BRANCH=smaug
TEST=verified messages printed on Smaug

Change-Id: I619625f7d4c5bc19cd9de64a0ba07899cf9ba289
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: e0ac4cb4c0d43b40f5c8f8f5a90eac45b0263b77
Original-Reviewed-on: https://chromium-review.googlesource.com/290130
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-(cherry picked from commit 75ea2c025d629c8fabc0cb859c4e8ab8ba6ce6e3)
Original-Change-Id: Ief6d1fc820330b54f37ad9260cf3119853460b70
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290373
Reviewed-on: http://review.coreboot.org/11407
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08 11:51:26 +00:00
Stefan Reinauer 4460703f59 Drop "See file CREDITS..." comment
coreboot has no CREDITS file.

Change-Id: Iaa4686979ba1385b00ad1dbb6ea91e58f5014384
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11514
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-07 15:54:50 +00:00
Duncan Laurie 5c25d0e8cc libpayload: x86: Add read/write{8,16,32} variants that match coreboot
Add the now coreboot standard MMIO read/write accessors that were
already defined for other architectures but not x86.

This leaves the old read/write{b,w,l} variants in place as was done
on the other architectures, presumably to support old payloads that
have not been updated.

BUG=chrome-os-partner:43072
BRANCH=none
TEST=emerge-glados libpayload
CQ-DEPEND=CL:294711

Change-Id: I5ae3d755adcef0f6ff27aaa7c35a5b12ddc32e22
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: c09dd557050e3002fa5b8504980d72d4cb79a56c
Original-Change-Id: I58d928338335d3fe4bb7fe2bdc9c2967d8689118
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294565
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11405
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2015-08-28 06:46:28 +00:00
Julius Werner e8a8a00342 libpayload: usb: dwc2: Always return 'size' transferred bytes for OUT
Seems like our transferred bytes calculation for OUT transfers that span
more than one packet had been wrong, and we just got lucky that we never
noticed it before. The HCTSIZ.xfersize register field we're reading only
counts bytes transferred by the last packet we sent.

OUT endpoints cannot have short transfers -- every transfer should
either finish all bytes we wanted to send or end in a proper error
condition. Therefore, in the absence of an error we can just conclude
that all input bytes have been transferred.

BRANCH=veyron
BUG=chrome-os-partner:35525
TEST=SMSC95xx netboot on Jerry now works.

Change-Id: I57349e697c428df6b56e2f6f62e87652ef1e7a94
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 0abee13b6d89dec12c6fff581ece1836393c7703
Original-Change-Id: Id0a127e6919f5786ba05218277705dda1067b8c3
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/293956
Original-Reviewed-by: yunzhi li <lyz@rock-chips.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/11404
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-28 06:46:19 +00:00
Julius Werner 4bfa29e947 arm64: xcompile: Add support for A53 erratum 843419
This patch adds support to enable a linker workaround to a hardware
erratum on some early Cortex-A53 revisions. Since the linker option was
added very recently, we use xcompile to test whether the toolchain
supports it first. It is also guarded by a Kconfig since only a few
ARM64 SoCs will need this and it incurs a performance penalty.

BRANCH=none
BUG=none
TEST=Turned it on or off for Smaug and confirmed that it (dis)appeared
in verbose make output accordingly.

Change-Id: I01c9642d3cf489134645f0db6f79f1c788ddb00d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 57128785760c4dfa32d6e6d764756443a9323cb7
Original-Change-Id: Ia5dd124f484e38460d75fb864304e7e8b18d16b7
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294745
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11403
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-08-28 06:46:09 +00:00
Nico Huber f58746bd33 libpayload: Fix default_memmove() implementation
If I wanted to fill the whole memory address space with one byte, I
wouldn't try it that subtle.

With size_t beeing unsigned the loop condition >= 0 was always true.

Change-Id: Idee6a4901f6697093c88bda354b5e43066c0d948
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/11286
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2015-08-19 16:35:08 +00:00
Yunzhi Li 4938426783 libpayload: usb: dwc2: fix usb plug/unplug bug
Check device connect status while waiting for usb transfer complete
Avoid coreboot get stuck when usb device unplugged

BUG=chrome-os-partner:35525
TEST=None
BRANCH=None

Original-Change-Id: Id103501aa0d8b31b0b81bef773679c0fad79f689
Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292630
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Lin Huang <hl@rock-chips.com>
Original-Tested-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292966
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>

Change-Id: I49396b74131dbfda505d9d3de5adbdc87eb92ce1
Signed-off-by: Yunzhi Li <lyz@rock-chips.com>
Reviewed-on: http://review.coreboot.org/11236
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-19 14:04:15 +00:00
Julius Werner 6f4c7a6fde libpayload: usb: xhci: Fix list of cleared port change bits
The xhci_rh_port_status_changed() function tries to always clear all
port status bits, even though most of them don't interest us. This is
generally a smart thing to do since not clearing a status bit may cause
the controller to not generate any more Port Status Change Events.
However, the bitmask we currently use doesn't cover bit 23 (Port Config
Error Change) and instead covers bit 16 (Port Link State Write Strobe)
which is not really related to this and not a W1C bit. Probably a typo,
so let's fix that.

BRANCH=None
BUG=None
TEST=Plugged/unplugged a bunch of USB devices on an XHCI Falco.

Original-Change-Id: Ia83f5b72cce094859c0f0e730752d7b5cfa6e1c6
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/291842
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I11f5fe38cb70055daf6e866a8ee84ca80488e3bf
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/11194
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14 15:18:16 +02:00
David Hendricks 75daee5ee9 libpayload: Do not gate USB_DWC2 on USB_HID
This forward-ports the change from CL:277155 since the Kconfig file
was renamed from Config.in.

BUG=chrome-os-partner:41416
BRANCH=none
TEST=built and booted on Mickey, keyboard works at dev screen
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>

Original-Change-Id: Ibffa5188df51ecd7b8bdd631d4b767ec64130819
Original-Reviewed-on: https://chromium-review.googlesource.com/291138
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>

Change-Id: Iebb1da6ec8c7886a6eb9ebcc67b59d617496c555
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/11188
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@google.com>
2015-08-14 15:17:36 +02:00
Julius Werner 57ddd9abc7 libpayload: usb: xhci: Count new Max Scratchpad Bufs bits from XHCI 1.1
The 1.1 revision of the XHCI specification added an extra 5 bits to the
Max Scratchpad Bufs field of HCSPARAMS2 that newer controllers make use
of. Not honoring these bits means we're not allocating as many
scratchpad buffers as the controller expects, which means it will
interpret some uninitialized values from the end of the pointer array as
scratchpad buffer pointers, which obviously doesn't end well. Let's fix
that.

BRANCH=none
BUG=chrome-os-partner:42279
TEST=Makes a USB-related memory corruption issue disappear.

Original-Change-Id: I7c907492339262bda31cdd2b5c0b588de7df8544
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/291681
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Iba1007bfebffe1f564f78bb875fff9ba0fe11a38
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/11189
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14 15:17:30 +02:00
Yunzhi Li 8b4988933c libpayload: usb: dwc2: fix short packet transfer
If short packet detected, stop this transfer and return the actual
transferred size

BUG=chrome-os-partner:42817
TEST=Netboot could run well
BRANCH=None

Original-Change-Id: Icb4317f48aa04ac15bb1886b81d2e3c472d123d0
Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/288215
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Lin Huang <hl@rock-chips.com>
Original-Tested-by: Lin Huang <hl@rock-chips.com>
Original-(cherry picked from commit d372343b4e3d664ce2d76dbf55a5061b5d496bba)
Original-Reviewed-on: https://chromium-review.googlesource.com/291064
Original-Commit-Queue: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Julius Werner <jwerner@chromium.org>

Change-Id: I43d9edffe2074c037f2df203621863e54d2597fa
Signed-off-by: Yunzhi Li <lyz@rock-chips.com>
Reviewed-on: http://review.coreboot.org/11187
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14 15:17:18 +02:00
Chunfeng Yun b4a24995c9 libpayload: usb: Fixup wrong use of config
replace CONFIG_LP_XHCI_MTK_QUIRK by CONFIG_LP_USB_XHCI_MTK_QUIRK

BRANCH=none
BUG=none
TEST=Rev0-oak

Original-Change-Id: I68f58ed3b02caa7cef8f0f60a4a8f5e9755c97a7
Original-Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/290522
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>

Change-Id: I316712e99e0b44d292dab27cf66e26837dc2e957
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Reviewed-on: http://review.coreboot.org/11179
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14 15:14:18 +02:00
Julius Werner 5f9a3f7fae libpayload: xhci: Carry over fixes from Chromium tree
This patch re-adds a few fixes that originally went into the
chromeos-2013.04 tree. I kinda seem to have slipped them into the
backport of Nico's original XHCI patch (crosreview.com/168097) instead
of making a new change, which was not very clever and caused them to be
forgotten in the later upstreaming wave.

Changing internal XHCI error numbers is just a cosmetic change to make
them uniquely identifyable in debug output. Bumping the timeout to 3
seconds is an actually important fix since we have seen mass storage
devices needing that much in the past.

BRANCH=None
BUG=None
TEST=Diffed payloads/libpayload/drivers/usb between chromeos-2013.04 and
chromeos-2015.07, confirmed that no serious differences remain.

Original-Change-Id: I03d865dbe536072d23374a49a0136e9f28568f8e
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290423
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I5d773d3a23683fb2164916cc046f4a711b8d259e
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/11178
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14 15:14:09 +02:00
Daisuke Nojiri 03e8188a3f cbfs: fix printf for 64bit architectures
BUG=none
BRANCH=smaug
TEST=Built for Smaug

Original-Change-Id: I7ff577f97252265ca6c96963ca44a6fbd0de9f7a
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290049
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-(cherry picked from commit 9cff308653766ea81978214e99a3d740aff4dbbe)
Original-Reviewed-on: https://chromium-review.googlesource.com/290116
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>

Change-Id: I5dcc17e0a42b46350fe6c398767f8155bdd0fd9d
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: http://review.coreboot.org/11177
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-14 15:13:39 +02:00
Aaron Durbin e3260ec29a libpayload: usb: don't prematurely free the usb device
Before the controller's destroy_device() could interrogate
the usbdev_t object usb_detach_device() was freeing and
NULLing out the pointer. That results in all callers who
needed that object to start accessing random bits of memory.

This eventually led into free()ing memory it shouldn't which
corrupted the allocator's state. Eventually, all forward
progress was lost by way of a single ended linked list
turning into a circular list.

The culprit seems to be a bad merge in commit e00ba21.

BUG=chrome-os-partner:43419
BRANCH=None
TEST=Can boot into OS now w/o "hanging" on glados.

Original-Change-Id: I86dcaa1dbaf112ac6782e90dad40f0932f273a1f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290048
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>

Change-Id: I9135eb0f798bf7dbeccc7a033c3f8471720a0de5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11173
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-13 16:34:09 +02:00
Paul Kocialkowski f1b7afb4a4 libpayload: Kconfig include in lpgcc
Payloads will include headers from libpayload, which depend on kconfig.h, so it
has to be included in the command line produced by lpgcc.

Change-Id: I3b55928babba2896a112f8c5fae46365cf71d308
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: http://review.coreboot.org/11114
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-10 20:29:07 +02:00
Patrick Georgi 7db6cef7fd libpayload: Fix compile error in time.c if nvram support is disabled
rdtsc() is only used for nvram access.

Change-Id: I896116d6a5782e5e50aa3acfbe1831b080f55d34
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11137
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-10 18:10:00 +02:00
Stefan Reinauer 2c6fe441a7 libpayload: Use CONFIG_LP_CCACHE instead of CONFIG_CCACHE
CONFIG_CCACHE was obsoleted a long time ago for libpayload.

Change-Id: Ib0a418d97f368439476e524b753160a6229bb9f6
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10710
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-09 21:02:37 +02:00
Patrick Georgi d7eb0cbf9a license headers: Drop FSF addresses again
Some FSF addresses found their way back into our tree.

Change-Id: I34b465fc78734d818eca1d6962a1e62bf9d6e7f3
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11145
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-09 17:49:13 +02:00
Paul Kocialkowski 7572e66bc7 libpayload: lpgcc: CFLAGS and CMDLINE order inversion
When building an external payload with lpgcc, the provided cmdline needs to be
included before libpayload-specific CFLAGS so that the include priority is the
payload first. This way, a payload using e.g. Kconfig that declares a config.h
will have its config.h included first, instead of libpayload's config.h.

Change-Id: I19b8012623e04c92a427d74904aed7f3bf5f0996
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: http://review.coreboot.org/11113
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-09 13:07:04 +02:00
Paul Kocialkowski 5d5fcdd82b libpayload: .xcompile target is an actual file
Marking .xcompile as PHONY implies triggering the xcompile script each time make
is invoked. This is particularly problematic, especially when the script cannot
find the crossgcc toolchains on its own and has to be fed XGCCPATH.

Change-Id: Icb5ae82b210bca1ee9cf56d76130eefde481f81e
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: http://review.coreboot.org/11118
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-08-04 08:06:55 +02:00
Paul Kocialkowski 8d829bf2cd libpayload: Veyron configs unification
All the currently-provided configs for veyron boards are the same, so we might
as well have a common one that can be used on all boards.

Change-Id: I2e24f2d7a5206878381467b97f01d3e752a93289
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: http://review.coreboot.org/11115
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-04 08:06:45 +02:00
Paul Kocialkowski db0c0c4a60 libpayload: Allow for KBUILD_DEFCONFIG override
In order to specify a defconfig to libpayload, one might want to declare
KBUILD_DEFCONFIG in the make command line and run the defconfig target.

Change-Id: I2ade6f4ff2f0b6478a0831158028ebc79b5daa81
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: http://review.coreboot.org/11112
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-03 17:24:32 +02:00
Julius Werner bf697566da libpayload: lz4: Add output overrun check to incompressible case
The LZ4 decompressor currently doesn't check for output overruns before
writing data in the case where a block had been incompressible (and
included verbatim in the compression stream). This is extremely unlikely
with the default 4MB blocks, but still a nice thing to fix. We'll still
output as much data as we can before returning an error to support
partial decompression use cases.

This matches the behavior already in place for normal, LZ4-compressed
blocks where the decompression function is already (supposed to be)
doing complete bounds checking (although it is not guaranteed to output
all valid bytes before aborting on an output overrun, and you should try
to provide a few dozen bytes of extra buffer space beyond the parts
you're interested in on partial decompression).

BRANCH=None
BUG=chrome-os-partner:32184
TEST=None

Change-Id: I5e40c8cec8947ec0ec8f6d8c8fa2574cfb4dc958
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 636985334c9b3b93a12d4066d2829f1f999c9315
Original-Change-Id: Iecf44650aade60b9fa1b13e57da752fb482a3f3f
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/286240
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11016
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-21 21:27:42 +02:00
Julius Werner 752fba7846 libpayload: usb: Add support for SuperSpeed hubs
This patch adds support for the SuperSpeed half of USB 3.0 hubs, which
previously prevented SuperSpeed devices behind those hubs from working.

BRANCH=None
BUG=chrome-os-partner:39877
TEST=Played around with multiple hubs and devices on Oak and Falco, can
no longer find a combination that doesn't work.

Change-Id: I20815be95769e33d399b7ad91c3020687234e059
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3db96ece20d2304e7f6f6aa333cf114037c48a3e
Original-Change-Id: I2dd6c9c3607a24a7d78c308911e3d254d5f8d91d
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/284577
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: chunfeng yun <chunfeng.yun@mediatek.com>
Reviewed-on: http://review.coreboot.org/10958
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-18 09:40:48 +02:00
Julius Werner e44a4e8787 libpayload: usb: xhci: Prevent address reuse
We have been trying to avoid reassigning previously used USB addresses
to different devices since CL:197420, because some devices seem to take
issue with that. Unfortunately, that patch doesn't affect XHCI: those
controllers insist on chosing addresses on their own. The only way to
prevent them from reusing a previously assigned address is to not
disable that slot at all.

This patch implements address reuse avoidance on XHCI by not disabling
slots when a device is detatched (which may occur both on physical
detachment or if we simply couldn't find a driver for that device).
Instead, we just release as many resources as we can for detached
devices (by dropping all endpoint contexts) and defer the final cleanup
until the point where the controller actually runs out of resources (a
point that we probably don't often reach in most firmware scenarios).

BRANCH=none
BUG=chrome-os-partner:42181
TEST=Booted an Oak plugged into a Servo without having a driver for the
SMSC network chip, observed that it could still enumerate the next
device afterwards. Kept unplugging/replugging stuff until the cleanup
triggered and made sure the controller still worked after that. Also
played around a bit on a Falco without issues.

Change-Id: Idfbab39abbc5bc5eff822bedf9c8d5bd4cad8cd2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 88c6bcbc41156729c3c38937c8a4adebc66f1ccb
Original-Change-Id: I0653a4f6a02c02498210a70ffdda9d986592813b
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/284175
Original-Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10957
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-18 09:40:32 +02:00
Yunzhi Li ebd3da7dba libpayload: usb: dwc2: support split transaction
With split transaction, dwc2 host controller can handle full- and
low-speed devices on hub in high-speed mode. This commit adds support
for split control and interrupt transfers

BUG=None
TEST=Connect usb keyboard through hub, usb keyboard can work
BRANCH=None

Change-Id: If7a00db21c8ad4c635f39581382b877603075d1a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4fb514b7f7f7e414fa94bfce05420957b1c57019
Original-Change-Id: I07e64064c6182d33905ae4efb13712645de7cf93
Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/283282
Original-Tested-by: Lin Huang <hl@rock-chips.com>
Original-Commit-Queue: Lin Huang <hl@rock-chips.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10956
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16 22:39:59 +02:00
Patrick Georgi 2272b80a1d libpayload: assume cbfs file alignment is 64 byte
Change-Id: I8dfd8fbd452ce92fbca2cf095bc5e43e4a26969d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10920
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-15 16:34:50 +02:00
Patrick Georgi f61b35d5b0 libpayload: store boot media information in sysinfo
Write boot media information in sysinfo, if it exists. This allows picking the
right CBFS for further files in case there are several.

Change-Id: I75a8ee6b93f349b9f2fab1e82826aba675949c0a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10869
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2015-07-14 22:37:10 +02:00
Patrick Georgi 89f73dccdb libpayload: Add support for handling fmaps
They will become more common soon, so better support them now.

Change-Id: I2b16e1bb7707fe8410365877524ff359aeefc161
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10868
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-14 18:12:06 +02:00
Julius Werner 6df355da87 libpayload: Fix arithmetic precedence in div_round_up()
Well, this is just embarrassing...

BRANCH=None
BUG=None
TEST=None

Change-Id: I7c443d2100b6861d736320ac14c1bd9965937a66
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 455e3784882ea1b76bcf8e17724869e37d9c629d
Original-Change-Id: Ia33e98aeaa8e78e3e3d2c7547e673a623ea86ce2
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/284596
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/10879
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Martin Roth <gaumless@gmail.com>
2015-07-13 09:19:42 +02:00
Stefan Reinauer 5d866213f4 libpayload: Have make install save .xcompile file
Useful information, record it in the destination directory,
together with .config.

Change-Id: Icf3282f61f502b37f9f06d7d5a0a630f49c96ed2
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10864
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-09 08:47:41 +02:00
Stefan Reinauer f53dbfaa8c libpayload: Use top level xcompile
Instead of having a second copy that already within 2-3 days
becamer quite outdated, use the same xcompile copy for coreboot
and libpayload, as we do with Kconfig already.

This requires a simple change to the top level xcompile to understand
both CONFIG_COMPILER_GCC and CONFIG_LP_COMPILER_GCC (only one of
them will occur at the same time)

libpayload's .xcompile target was moved later so that it can make use
of $(top)

Change-Id: I44001067f551cd0776dd303cbaeaa40eb3d5c1db
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10863
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-09 08:47:16 +02:00
Julius Werner bf27391da5 libpayload: Add LZ4 decompression algorithm
This patch adds support for the LZ4 decompression algorithm to
libpayload. It's what all the cool kids are using for decompression
these days and has many interesting advantages over LZMA (and everything
else I know of): blazing fast decompression (20(!) times faster than
LZMA, twice as fast as LZO on my Cortex-A72), no memory requirements on
decompression, and possibly in-place decompression support. It pays for
that with a lower compression ratio (about 50% larger compressed size
than LZMA, 10% larger than LZO for an ARM64 Linux kernel binary), but
the boot time math still works in its favor for our IO speeds.

This patch only adds the raw decompression functions for use by external
payloads, we can later try integrating them in CBFS. It copies the
decompression code itself unmodified from the upstream LZ4 library at
github.com/Cyan4973/lz4 which will hopefully make it easy to update. The
frame format parsing is reimplemented since the upstream version looks
unnecessarily complex and unreadable for our needs.

BRANCH=smaug
BUG=chrome-os-partner:32184
TEST=With other patches, booted ARM64 kernel that got compressed from
15M to 5.1M and decompresses in 44ms.

Change-Id: I65bdc4b2b19bd51c7b7e17a4e4b79da301a2a014
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f8a1fc996d5b0234d07f567fa8163d0f802d5144
Original-Change-Id: I15c0620da05561ade2552b15ffdf6bb3afd7eb26
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/282743
Original-Reviewed-by: Stefan Reinauer <reinauer@google.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10845
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-09 00:10:16 +02:00
Patrick Georgi 838c88f1b7 libpayload: update defconfigs
That way they don't need an initial 'make oldconfig' pass to
be useful again.

Change-Id: I3724fffab24b69478b8077f34e9d787555fd157b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10805
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-08 10:25:11 +02:00
Patrick Georgi 9b8c738942 libpayload: don't overwrite CFLAGS
Makefile already sets it to contain the architecture specific flags,
don't drop them, but add to that instead.

Change-Id: I147e6480ab2b3c1ee4f4ace511197b4ba94280b8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10804
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06 18:27:17 +02:00
Patrick Georgi 21fc58b660 libpayload: architecture mapping is now done in xcompile
This helps the build system find i386 and mips compilers.

Change-Id: I17d18019b556190f860d288e66f368f8d29ca24d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10803
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06 18:27:01 +02:00
Patrick Georgi 46eeb339e9 libpayload: drop LIBGCC_FILE_NAME variable
It's unused. If we need something like that, .xcompile provides it,
and in a cross-platform and clang-aware way.

Change-Id: Ic1bdc2e3e252d612a5b99ad4e8caebc5158a485f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10802
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06 18:26:42 +02:00
Patrick Georgi db0325591d libpayload: defer including .xcompile
It needs to come after DOTCONFIG so that the compiler decision can
be made.

Change-Id: I5c6730ac58ab8731f07bb7c5161b2d0a59588e28
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10801
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06 18:26:12 +02:00
Patrick Georgi b7d8f26eec libpayload: Add compiler switch
clang is totally untested, but it mirrors coreboot now.

Change-Id: I0e13ff8bba2007159a4a795ca07d187504b606b2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10800
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06 18:25:52 +02:00
Patrick Georgi 3f02466b00 libpayload: mark util/xcompile/xcompile executable
Change-Id: I97088df1550f580d4648c7cccbd81c696fcfe2dc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10799
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06 18:25:05 +02:00
Daisuke Nojiri 9150e5e0f2 cbfs: define libpayload_init_default_cbfs_media weakly
To allow a payload to define its own libpayload_init_default_cbfs_media,
default implementation needs to be defined weakly.

BUG=none
BRANCH=tot
TEST=dumped a cbfs file from depthcharge cli on jerry

Change-Id: Ice73ae5a63dfd49e79c0eeb92d4eade016d61c39
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1f308177fffb0d525fdb50f8d024568bb9025352
Original-Change-Id: I4721139aea3169c62c10a2a26582bd9277e4cb83
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/283061
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10783
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06 09:42:12 +02:00
Daisuke Nojiri 3740546bd8 sysinfo: remove unused tag for struct spi_flash
This will conflict with struct spi_flash defined in spi_flash.h

BUG=none
BRANCH=tot
TEST=built libpayload for veyron jerry

Change-Id: I7e1be28cf430021944fc96890082a0704d093e9f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0f0b8a7ec114046335fb1a51b6a92e10e5a16520
Original-Change-Id: I6d4f8a8e93aeb055f7dd6e5e8fd5e6c6153ab837
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/282588
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: http://review.coreboot.org/10782
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06 09:41:54 +02:00
Daisuke Nojiri e0a8a88912 update common base header files
IS_ENABLED is defined in kconfig.h, thus, should be included in
libpayload.h.

BUG=none
BRANCH=tot
TEST=built coreboot/libpayload for veyron_jerry

Change-Id: I9c5879b6125ac66a75a507ab07a6816ab54ed0ba
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 51dcd58a841009081fdefcadf9aa74286152dde6
Original-Change-Id: I30e6d87c9de827a214a6100449cd716e773c2ba3
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/282587
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: http://review.coreboot.org/10781
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06 09:41:38 +02:00
Julius Werner d8086876a7 lzma: Return correct amount of decompressed bytes
The LZMA functions are supposed to return the decompressed size, but
what they actually return is just an unaltered field from the LZMA
header that is *supposed* to contain the decompressed size. Apparently
some encoders just overshoot that for no good reason. This patch changes
the code such that the actual amount of decompressed bytes is returned.

BRANCH=smaug
BUG=None
TEST=Printed output bytes when decompressing kernels with LZMA in
depthcharge, noted that amounts now make sense.

Change-Id: Icdd8f782aa87841f770eff4c14a08973530c7446
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 24b2fa8c9a342ca4288dad1430c8965395f00263
Original-Change-Id: Ib4cf8673846aedd34656e594ce7b8ea875b56099
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/282742
Original-Reviewed-by: Stefan Reinauer <reinauer@google.com>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10777
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06 09:40:37 +02:00
Yunzhi Li aa33609d28 libpayload: usb: dwc2: support interrupt transfer
dwc2 host core do not have a periodic schedule list, so try to send
an interrupt packet in poll_intr_queue() function and use frame
number read from usb core register to calculate time and schedule
transfers.

BUG=None
TEST=Tested on RK3288 with two USB keyboards(connect to SoC without
USB hub), both work correctly.
BRANCH=None

Change-Id: I16f7977c45a84b37c32b7c495ca78ad76be9f0ce
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3d0206b86634bcfdbe03da3e2c8adf186470e157
Original-Change-Id: Ie54699162ef799f4d3d2a0abf850dbeb62417777
Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/280750
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Lin Huang <hl@rock-chips.com>
Original-Tested-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: http://review.coreboot.org/10774
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06 09:40:02 +02:00
Daisuke Nojiri 394933640b libpayload: arm(64): add read8/16/32 and write8/16/32
This applys the same change made by
https://chromium-review.googlesource.com/261692
to libpayload.

BUG=none
BRANCH=tot
TEST=built for veyron_jerry, rush_ryu, samus

Change-Id: I26dd66d79cd1559a7852b3c9d252420f2fed5fa0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d0d6f70aa805e18966e80618fbf9e9605274b030
Original-Change-Id: Ib0c199238f8fa58643d51782b17550dbd0d9ebd7
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/282541
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10773
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06 09:39:48 +02:00
Yunzhi Li d8a3ed49a5 libpayload: udc: dwc2: support force_shutdown() routine
Add force_shutdown() routine for dwc2 udc driver to support
disconnect and reconnect case when fastboot receiving data.

BUG=chrome-os-partner:41687
BRANCH=None
TEST=None

Change-Id: I9ec204d8b7088cfafd3164c9779a6fd85d379dba
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9238f87c065ba8a57bfb4a7e65fd1821ff2922f9
Original-Change-Id: I1e584aaf19efa14409bdfa26039c27fa7034b5f0
Original-Signed-off-by: Yunzhi Li <lyz@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/281130
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Lin Huang <hl@rock-chips.com>
Original-Commit-Queue: Jeffy Chen <jeffy.chen@rock-chips.com>
Reviewed-on: http://review.coreboot.org/10770
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-06 09:39:14 +02:00
Patrick Georgi 885ec48b95 libpayload: update xcompile script
Copy from coreboot. at some point it probably should just reuse coreboot's
version.

Change-Id: Iee905a9060983ff85e2e70bde69a221c64a07cbc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10756
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-03 09:38:18 +02:00
Stefan Reinauer e559536daa libpayload: always compile with -ffunction-sections
Always compile with -ffunction-sections and -fdata-sections

This does not hurt, and it allows the linker to produce much
smaller binaries in some circumstances.

Change-Id: Ibf9f24c210d6d2ed40451b4cf0d68ce88220bc5f
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10750
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-01 22:07:48 +02:00
Stefan Reinauer 088c1894f8 libpayload: Fix compilation on ARM with GDB enabled
Without this, gdb_enter() is not defined.

Change-Id: I067dce371ee817d6ac77387fcbe42a9a7deb6438
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10755
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2015-07-01 20:55:29 +02:00
Stefan Reinauer 909b916e56 libpayload: Keep stack boundary small on x86
There is no measurable performance impact, but
this positively impacts the memory used by payloads.

Change-Id: Ib2bdba4a7bf2a4c2391a20b3225bbb44422d3194
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10751
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-07-01 20:55:18 +02:00
Stefan Reinauer 2551f5914e libpayload: Makefile: Use variables defined for Kconfig
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Change-Id: Ia451e8250307ad1944cb0429bdfee4bdf18c706b
Reviewed-on: http://review.coreboot.org/10712
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-30 18:56:19 +02:00