Commit graph

3 commits

Author SHA1 Message Date
Rob Barnes
b132bf5a87 soc/amd/picasso: Set max_speed_mts and configured_speed_mts
ddr_frequency is deprecated. Set max_speed_mts and configured_speed_mts
instead. This will result in SMBIOS type 17 displaying more accurate
speed information.

BUG=b:167218112
TEST=Boot ezkinil and observe dmidecode -t17
  dmidecode -t17
  # dmidecode 3.2
  Getting SMBIOS data from sysfs.
  SMBIOS 3.0 present.

  Handle 0x000B, DMI type 17, 40 bytes
  Memory Device
	Array Handle: 0x000A
	Error Information Handle: Not Provided
	Total Width: 64 bits
	Data Width: 64 bits
	Size: 4096 MB
	Form Factor: SODIMM
	Set: None
	Locator: Channel-0-DIMM-0
	Bank Locator: BANK 0
	Type: DDR4
	Type Detail: Synchronous
	Speed: 3200 MT/s
	Manufacturer: Unknown (0)
	Serial Number: 00000000
	Asset Tag: Not Specified
	Part Number: MT40A512M16TB-062E:J
	Rank: 1
	Configured Memory Speed: 2400 MT/s
	Minimum Voltage: Unknown
	Maximum Voltage: Unknown
	Configured Voltage: Unknown

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I1879676ea9436b6d19c768f1b78487a4e179f8d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44984
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-03 21:28:13 +00:00
Rob Barnes
bcab8b0a41 soc/amd/picasso: Store ddr_frequency in MT/s
This field eventually gets interpreted as MT/s by SMBIOS instead of MHz. Translate from Mhz to MT/s by multiplying by 2.

BUG=b:154654737
TEST=dmidecode -t 17 matches expected speed

Change-Id: I51b58cb0380f2a2bf000347395ac918ac0717060
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-24 09:13:54 +00:00
Rob Barnes
009a23d5c8 soc/amd/picasso: supply SMBIOS type 17
Extract DRAM info from AMD_FSP_DMI_HOB and store it as mem_info in
cbmem with id CBMEM_ID_MEMINFO. Subsquently extract mem_info objects
from cbmem to build SMBIOS type 17 tables.

BUG=b:148277751,b:160947978
TEST=dmidecode -t 17
BRANCH=none

Change-Id: Iacedbb017d19516674070f89ba0aa217f55383e3
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-13 21:39:05 +00:00