Commit Graph

32858 Commits

Author SHA1 Message Date
John Su 9484792ad1 mb/google/drallion/variants/drallion: Update thermal configuration for DPTF
Follow thermal table for first tuning.

BUG=b:144464314
TEST=Built and tested on drallion

Change-Id: I4546622cdc6efb2bf2eb973cfc5c6f22c40cc6ef
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36860
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-11 08:30:28 +00:00
Elyes HAOUAS 12520134f1 mb/google/daisy: Move 'PMIC_BUS' to Kconfig
Change-Id: If40fa38e5b249452a6dacf4a4045b6bd00c27cfa
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-12-10 11:20:59 +00:00
Joel Kitching 9e052c2b6c vboot: remove old vboot_fill_handoff function header
This function was removed in CB:33535.

BUG=b:124141368
TEST=make clean && make runtests
BRANCH=none

Change-Id: Ifded75319c92dcbb4befbb3fbecc1cd2df8a9ad0
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-12-10 11:20:21 +00:00
Frans Hendriks 18aa6fe261 mb/{facebook/portwell}: Remove ITE8258_CMD_PORT
ITE8258_CMD_PORT is used in com_init.c only.
Replace ITE8258_CMD_PORT by fixed value in the c file.
ITE8258_DATA_PORT is removed as this isn't used.

BUG=N/A
TEST=build

Change-Id: I401da3f127db9e65763fd8d115eb274fbadbefbe
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-12-10 11:19:30 +00:00
rkanabar 263f129a8e soc/intel/common: Add Jasperlake Device IDs
Add Jasperlake SA and PCH IDs

Change-Id: I2c9ec1ee4236184b986d99250f263172c80f7117
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
2019-12-10 11:18:48 +00:00
Michał Żygowski 200d213d1b amdblocks/pci: add common implementation of MMCONF enabling
Add common function to enable PCI MMCONF base address. Use the common
function in stoneyridge bootblock.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I1bb8b22b282584c421a9fffa3322b2a8e406d037
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-12-10 11:18:00 +00:00
Kyösti Mälkki a244d5edd4 sb/amd/{agesa,pi}/hudson: Explicitly enable LPC controller
Location in hudson_lpc_port80() was called conditionally.
Also move hudson_lpc_decode() call after enable_acpimmio_decode_pmXX()
due the change from IO to MMIO using pm_read/write.

Change-Id: I38e94e4b04f0a493052cfd3ffdd0a9c2ac0d07fc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-12-10 11:17:40 +00:00
Seunghwan Kim 0a2de7b538 mb/google/kohaku: Update TCC offset setting
This change sets TCC offset to 10 for kohaku.

BUG=b:144532818
BRANCH=firmware-hatch-12672.B
TEST=Checked thermal and performance efficiency internally (b:144532818)

Change-Id: Ia4b53de3a53bc39c1cd0f7626ae23d4c11a7a3db
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37587
Reviewed-by: Kane Chen <kane.chen@intel.com>
Reviewed-by: Grace Kao <grace.kao@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-10 11:17:29 +00:00
Elyes HAOUAS 13746076e9 mainboard/(i945,ich7): Remove commented RCBA32(0x341c) code
PCIe root port clock gate is already enabled at i945/early_init.c
Also fix comments when only PCIe root port is enabled.

Change-Id: Ica38529dbdd5cc51b19b426999a1d9f0b678b4f5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37576
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-10 11:16:07 +00:00
Patrick Georgi e86ded841f Documentation: Describe how to deal with snooping https proxies
Disabling SSL verification is far from optimal, but depending on the
circumstances may be the most practical way, so describe how to do
that instead of leaving users confused.

It's also not _that_ bad because git's hashing scheme should uncover
most attempts to tamper with code, either when checking signed tags
or when people push (and see lots of modified commits).

State the command in a way that isn't conductive to careless
copy & paste.

Change-Id: Idbd52ba5d6e8b0f0e891fca16e4159ccef10771a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-10 11:15:42 +00:00
Christian Walter 19b963ce86 include/device/pci_ids: Add Coffeelake U IGD P630
Change-Id: Ifdb9943e6362b7f29c2079759ea09d7b3a940993
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37608
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-10 10:56:48 +00:00
Nico Huber d83bd535be Kconfig: Drop NO_RELOCATABLE_RAMSTAGE
It's not selected anywhere anymore. Drop it and set the default for
RELOCATABLE_RAMSTAGE directly.

Change-Id: I580e89525ece39418afeefd6a9d0b89b370ca95f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37577
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: ron minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-09 17:02:16 +00:00
Kyösti Mälkki 4841203c3a binaryPI boards: Bulk remove BINARYPI_LEGACY_WRAPPER remains
These boards currently have no build-testing, so they degrade
fast. Apply some of the build-tested changes we know to be
good from pcengines/apu2 to get them a bit closer to using
POSTCAR_STAGE=y.

Change-Id: Ibc9a15ed5e91c6dd857f2dd02e37d0979dd6ae90
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-12-09 16:11:52 +00:00
Angel Pons 3979def529 payloads/bayou: remove unhooked payload
The bayou payload is not attached to the build system in any way, and
has not been for quite a while. Since selecting it in Kconfig does
nothing, remove this payload now that coreboot 4.10 has been released.

Change-Id: Icfb18b88e460a4e4b538b7efe907d4eef6c40638
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-09 09:51:23 +00:00
Peter Lemenkov d01b675067 mb/lenovo/w530/devicetree: Use subsystemid inheritance
Change-Id: I0646b18e823c52109e0fb62c85726622156172b9
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37385
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-09 09:50:11 +00:00
Peter Lemenkov abb0ebbb51 mb/lenovo/s230u/devicetree: Use subsystemid inheritance
Change-Id: I70eabc0b03709409d997ccbe8b8e257d68aec338
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-09 09:49:58 +00:00
Peter Lemenkov b8b9786ad4 mb/lenovo/t430s/devicetree: Use subsystemid inheritance
Change-Id: Ifde5d382eb223bd996b9bb909c751e9d5f0a11e5
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37300
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-09 09:49:24 +00:00
Peter Lemenkov 07b2fdb594 mb/lenovo/t430/devicetree: Use subsystemid inheritance
Change-Id: I53e9e1a8381ca51200dc5306eef32442668607a3
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-09 09:49:16 +00:00
Peter Lemenkov bbb00d7404 mb/lenovo/x230/devicetree: Use subsystemid inheritance
Change-Id: I95dbf55b74deca1e035ee1d042f1549d2583e346
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-09 09:49:09 +00:00
Peter Lemenkov 289b7d65fc mb/lenovo/x220/devicetree: Use subsystemid inheritance
Change-Id: Ia9367d03b6f97f1eb8c35045fd7bb79e5f45b535
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-09 09:49:02 +00:00
Peter Lemenkov 7e128576c2 mb/lenovo/l520/devicetree: Use subsystemid inheritance
Change-Id: I90774e22fb7765f44b6cd4fa05b535236b782023
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-12-09 09:48:51 +00:00
Peter Lemenkov 5ee7e472d1 mb/lenovo/t420s/devicetree: Use subsystemid inheritance
Change-Id: Ia77f0ce89b2234b9c164bb326d76bef98949832a
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37285
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-09 09:48:36 +00:00
Peter Lemenkov f15f310ea4 mb/lenovo/t420/devicetree: Use subsystemid inheritance
Change-Id: Ia321f2b974539ac1684173d767dd9eb64060364a
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-12-09 09:46:53 +00:00
Bill XIE 322635a955 mb/gigabyte/ga-b75m-d3h: Add ga-b75-d3v as a variant
It is an ATX board similar to existing ga-b75* boards. The major
difference is the configuration of pci-e ports on PCH, and on-board
pci-e NIC. (see below)

Tested:
    - CPU i5 3570T
    - Slotted DIMM 8GiB*4 from Kingston
    - usb2 and usb3
    - pci and pci-e ports
    - sata
    - Sound
    - S3
    - AR8161 NIC connected to 1c.2 with mac address burnt in efuse
    - libgfxinit-based graphic init
    - NVRAM options for North and South bridges
    - tpm 1.2 on lpc (similar to ga-b75m-d3h)
    - Linux 4.19.67-2 within Debian GNU/Linux stable, loaded from
      SeaBIOS.

Change-Id: I1a969880e4da02abf8ba73aac60ee1296fe0abf2
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-12-09 09:46:02 +00:00
Elyes HAOUAS aeff512a50 src/device: Fix typo
Change-Id: Ibe99264a82fdea0e185907d2d2d4c57078ef3ae4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-12-09 09:45:25 +00:00
Elyes HAOUAS c79efa822d util/lint: Update spelling.txt to latest linux version
Change-Id: Ife90b61d04e32f307a688d81922bdcf6fa57cfc9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37572
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-09 09:45:07 +00:00
Johanna Schander 808f5c3849 drivers/intel/fsp2_0: Allow to add FSP binaries from repo for IceLake
This commit is adding a dependency check for the FSP_USE_REPO
config option which so far was not able to deal with IceLake
systems.

Change-Id: I29faa8d3acff5680b611951fc193d33f514dc0d3
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37561
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-09 09:44:30 +00:00
Johanna Schander 0b82b3d6fd 3rdparts/fsp: Update fsp submodule
The name for the CoffeeLake FSP.fd was changed to Fsp.fd.
Therefore the CoffeLake / WhiskeyLake default path was
changed.

Change-Id: I0f51e378fcaacb25392d8940a342fc968c730157
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37564
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-09 09:44:07 +00:00
Angel Pons 96e2a5da34 soc/intel/bsw/gpio: Factor out GPI macros
This patch simplifies some GPIO macros by removing redundant code.
Also, for the sake of completeness, add two missing macros.

Change-Id: I838efe8b26f60d3e059f4ce18c116aefbc0b0400
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-09 09:43:48 +00:00
Peichao Wang 3b34db6c0f mb/google/octopus: Create Foob variant
This commit creates a foob variant for Octopus. The initial settings
override the baseboard was copied from variant phaser.

BUG=b:144890301
BRANCH=octopus
TEST=emerge-octopus coreboot

Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: Ibcdda4dd0846612f5e98ab454db7144c1caf0507
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37456
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-09 09:40:47 +00:00
Arthur Heymans edcce07531 Documentation: Move ACPI documentation in a subindex
Change-Id: I17c5263674b805a73d98aaa3e7090083905e37ef
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-09 09:40:28 +00:00
Arthur Heymans 1bb330348d Documentation: Remove redundant 'documentation'
We are already in documentation so it should be obvious that other
links point to other documentation.

Change-Id: I7a021a09bdb88418ec85dbf433465f26445057d0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-12-09 09:40:02 +00:00
Tim Wawrzynczak 14dd073e80 EC sync: Properly handle VBERROR return codes from vb2api_ec_sync
Some return codes were missed when implementing this initially; the vboot
logic can require the system to command the EC to reboot to its RO, switch
RW slots or it can require a poweroff of the SoC.  This patch appropriately
handles these return codes.

BUG=b:145768046
BRANCH=firmware-hatch-12672.B
TEST=ODM verified this patch fixes the issues seen.

Change-Id: I2748cf626d49c255cb0274cb336b072dcdf8cded
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-12-09 09:39:29 +00:00
Wim Vervoorn 57aa8e37dc mb/intel/kblrvp: Remove hex values from VR settings
Change the hex values in the VR configuration tables of the Intel Kaby
Lake RVP boards to the same style that is used in the other mainboards.

Also, correct some numbers in the comment tables that did not match the register values.
The values in the tables haven't changed.

BUG=N/A
TEST=build

Change-Id: I77af544d7d88143e19abedb12a13627779c705c6
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37550
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-09 09:38:41 +00:00
Matt DeVillier 0bb644754d mb/google/poppy: set detachable system type for nocturne/soraka
Set the SMBIOS system type to detachable for nocturne and
soraka variants, to allow the OS to correctly process events.

Change-Id: Ie0ee5ea6666542c0bca2c264b2ed2e6135b78658
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-09 09:38:13 +00:00
Kyösti Mälkki 657d68bddc AGESA,binaryPI: Move PORT80 selection to C bootblock
Because the function is implemented in C, post_code() calls
from cache_as_ram.S and other early assembly entry files may
not currently work for cold boots. Assembly implementation
needs to follow one day.

This effectively removes PORT80 routing from boards with
ROMCC_BOOTBLOCK.

Change-Id: I71aa94b33bd6f65e243724810472a440e98e0750
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2019-12-09 05:23:55 +00:00
Elyes HAOUAS dafc78bb8d mb/asus/am1i-a: Remove defined and not used ITE_CONFIG_REG_CC
Change-Id: I934830c09f7996e8f5aae5d5abe9fb6014fb478d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
2019-12-08 17:52:30 +00:00
Elyes HAOUAS 9f56eeda41 src/superio: Remove unused intel's superio chips
Change-Id: Ie693ff700a804778682daf0cb3990a56ab747a93
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-12-06 15:24:27 +00:00
Peter Lemenkov a0c97590b9 mb/lenovo/w520/devicetree: Use subsystemid inheritance
Change-Id: If7816992e717b4da585b16e5bbe67610c9af867d
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-12-06 15:21:47 +00:00
Peter Lemenkov 2ee6fbf0d7 mb/lenovo/t520/devicetree: Use subsystemid inheritance
Change-Id: Iffeb634c73f58aa1cddac5210d75fda75a3d5e92
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37293
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-06 15:21:38 +00:00
Marshall Dawson 67910db907 arch|cpu/x86: Add Kconfig option for x86 reset vector
Prepare for an implementation supporting the reset vector in RAM and
not the traditional 0xfffffff0.  Add a Kconfig symbol that can be used
in place of hardcoded values.

Change-Id: I6a814f7179ee4251aeeccb2555221616e944e03d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-12-06 15:16:47 +00:00
Wim Vervoorn 4ba70a7575 src: Add Facebook Monolith to maintainers
Add Facebook Monolith maintainers.

BUG=N/A
TEST=build

Change-Id: I4e7f44710deada0331ac9b4e77d6144848faf6cb
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-12-06 15:15:27 +00:00
Wim Vervoorn 7c04acff8a mb/facebook/monolith: Add Facebook Monolith
The board is booting Linux and has been briefly tested.

SeaBIOS, TianoCore payload and Linux as payload all seem to work fine.

BUG=N/A
TEST=tested on Facebook Monolith

Change-Id: I65a2e03334af65cfb3f825d43fa0daa6e6c75913
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-12-06 15:15:08 +00:00
Wim Vervoorn cbc878d2a2 drivers/intel/fsp2_0: Add logo support
Add support for the FSP feature to display the logo.

BUG=N/A
TEST=tested on facebook monolith

Change-Id: Iaaffd2be567861371bbe908c1ef9d7dde483a945
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-06 15:14:27 +00:00
Wim Vervoorn 2ab4f4b2c5 soc/intel/skylake: Add option to control microcode update inclusion
On embedded boards the cpu mounted on the board is known. So it is not
required to include microcode for all possible Sky Lake and Kaby Lake
cpus. This patch provides the possibility to only support the versions
required.

By default all microcode updates will be included and the versions not
required can be removed using Kconfig.

BUG=N/A
TEST=build

Change-Id: Iaa36c2846b2279a2eb2b61e6c97d6c89d0736f55
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-12-06 15:14:15 +00:00
Kyösti Mälkki 05fe16c4f3 console,monotonic_timer: Avoid calls from APs
The code in cpu/x86/lapic/apic_timer.c for timer_monotonic_get()
is not SMP safe as LAPIC timers do not run as synchronised as TSCs.

The times reported for console for boot_states does not accumulate
from APs now. Also remove console time tracking from ENV_SMM.

Change-Id: I1ea2c1e7172f8ab3692b42dee3f669c5942d864a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37398
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-06 15:11:02 +00:00
Philipp Hug 934ae21b52 mb/emulation/qemu-riscv: Implement ipi using clint to enable smp in qemu/spike.
TEST=Set MAX_CPUS=2 and run qemu with -smp 2

Signed-off-by: Philipp Hug <philipp@hug.cx>
Change-Id: I94fb25fad103e3cb5db676eb4caead11d54ae0ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Xiang Wang <merle@hardenedlinux.org>
2019-12-06 15:09:48 +00:00
Elyes HAOUAS 8cb5ea7879 nb/i945: Fix typo
Change-Id: I082ac2c1c13cbe6835a02d703f8651e837a43f37
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-06 15:09:17 +00:00
Julius Werner 879ea7fce8 endian: Replace explicit byte swapping with compiler builtin
gcc seems to have some stupid problem with deciding when to inline byte
swapping functions (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92716).
Using the compiler builtin instead seems to solve the problem.

(This doesn't yet solve the issue for the read_be32()-family of
functions, which we should maybe just get rid of at some point?)

Change-Id: Ia2a6d8ea98987266ccc32ffaa0a7f78965fca1cd
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-12-06 15:08:50 +00:00
Elyes HAOUAS 6fdf122fc3 superio/smsc/lpc47n207: Remove unused <stdint.h>
Change-Id: I9e6b2548ff7eb7224b15ffa2541922790816c947
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-12-06 15:01:08 +00:00