Commit Graph

37717 Commits

Author SHA1 Message Date
Duncan Laurie 30c3f91d33 acpigen: Make gpio set/get arguments const
The 'struct acpi_gpio' arguments passed to acpigen functions are
not modified so they can be made const, which allows drivers to
also use a const pointer.

Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I59e9c19e7bfdca275230776497767ddc7f6c52db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46257
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21 22:24:19 +00:00
Duncan Laurie 36858208e6 acpigen: Add ShiftLeft function helper
Provide a helper function for the ACPI shift left operator that
uses the same operator for the source and result.

ShiftLeft (OP, count, OP)

Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I66ee89bd1c4be583d0e892b02535bfa9514d488a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46256
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21 22:24:11 +00:00
Duncan Laurie 8e391d3452 acpigen: Add helpers for common Store operations
Add helpers for some store operations:

Store(INTEGER, NAME) ex: Store (100, SAVE)
Store(INTEGER, OP)   ex: Store (100, Local0)

Change-Id: Ia1b3f451acbfb2fc50180a8dcd96db24d330c946
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46255
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21 22:24:03 +00:00
Duncan Laurie 095bbf969d acpigen: Add option for reserved bits in Field
Add an option for unused/reserved bits in a Field definition,
allowing for declarations that do not start at bit 0:

Field (UART, AnyAcc, NoLock, Preserve)
{
    , 7,  /* RESERVED */
    BITF, /* Used bit */
}

These just use byte 0 instead of a name.

Change-Id: I86b54685dbdebacb0834173857c9341ea9fa9a46
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46254
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21 22:23:55 +00:00
Srinidhi N Kaushik cf5d58328f drivers/intel/gma: Increase vbt_data size
With TGL FSP v3373 onwards vbt binary size changed from 8KiB
to 9KiB. Due to which cbfsf_decompression_info check failed
when trying to load vbt binary from cbfs because vbt
decompressed_size was greater than vbt_data size. This caused
Graphics init and fw screen issues. Increase the vbt_data to
9KiB to accommodate new vbt binary.

BUG=b:170656067
BRANCH=none
TEST=build and boot delbin and verify fw screen is loaded

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: If6ffce028f9e8bc14596bbc0a3f1476843a9334e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dossym Nurmukhanov <dossym@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-10-21 18:36:08 +00:00
Patrick Rudolph 3e69c0a077 cpu/intel/common: Fix regression
Fix the logic introduced in CB:46276
"cpu/intel/common: only lock AES-NI when supported"
which needs to be negated.

Change-Id: Icaf882625529842ea0aedf39147fc9a9e6081e43
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46634
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21 17:52:24 +00:00
Duncan Laurie 389cb30ced soc/intel/common: Fix/clean up USB4 PCIe virtual/generic driver
This driver is for the root port device and needs to reference the
parent device for its ACPI scope.  Similarly for the debug output it
needs to use the parent device, and fall back to the chip name if
config->desc is not provided in the devicetree.

The UID property is removed.  This value is not the same as the port
number; according to some docs it should be unique but it is not fully
clear what it should be tied to.  Regardless, it is not used by the
Thunderbolt driver in the kernel.

I also renamed some functions/structures to be clear that this is just
an ACPI driver for the PCIe root port and not a driver for the root port
itself.  As part of this I removed the PCI based resource operations and
the scan bus function since this device does not have children itself.

Finally I added a detailed comment with an example describing what the
driver is for and what properties it generates.

TEST=boot on volteer and ensure the USB4 root port device and properties
are added to the SSDT as described by the comment in chip.h.

Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: Id6069a0fb7a0fc6836ddff1dbeca5915e444ee18
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46544
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21 15:35:50 +00:00
Duncan Laurie fcbf18c5df soc/intel/common: Fix ACPI device name for USB4 DMA device
The USB4 host interface (DMA) devices need to use SA_DEVFN_*
instead of SA_DEV_* when determining the ACPI name.

The matching names are removed from the SOC-level ACPI name
handler since they are provided by this driver now.

TEST=boot on volteer and ensure TDM0 device is in the SSDT.

Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: If778bda82b80593452a590962dbffef6eff6484a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-21 15:35:42 +00:00
Duncan Laurie bf69622256 device: Allow virtual/generic devices under PCI in devicetree
This change allows a generic device to be described in the devicetree
under a PCI device, such as a root port.

Previously any device under a PCI device was expected to also be a PCI
device and that does not allow for a virtual/generic device to be
present, for example to provide ACPI properties for a root port.

The changes are:
- Ignore non-PCI devices found under a PCI device when scanning and do
not print an error for each devfn scanned.
- Don't treat non-PCI devices as leftover and remove them, instead
enable them as a static device.
- Don't attempt to configure a static device in the tree that is not a
PCIe device type.

With these changes it is now possible to have a generic device under a
PCI device, for example in a USB4/TBT root port (PCIe hotplug device)
this generic device will add ACPI properties for the PCIe tunnel routed
to the external port:

device pci 07.0 on
  chip soc/intel/common/block/pcie
    device generic 0 on end
  end
end

TEST=boot on volteer with the USB4 root port devices in chipset.cb and
ensure they are enabled properly and there are no errors printed in the
coreboot log, and that the device properties are created in the SSDT.

Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I56a491808067dc862a7adfd46852f0bd6b41cd95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46542
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21 15:35:33 +00:00
Duncan Laurie 3e4a14e153 device: Export enable_static_device() function
The work done by enable_static_devices() and scan_generic_bus()
is common and can be used by other device handlers to enable a
single static device.

Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: Ibfde9c4eb794714ebd9800e52b91169ceba15266
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-21 15:35:24 +00:00
Nico Huber 2a507f734e mb/asus/f2a85-m_pro: Turn super-i/o 0x30 writes into on/off
The 0x30 register is eventually controlled by coreboot's
pnp_enable_resources() based on the on/off setting. Other
register settings were grouped with their respective "virtual"
LDN, where possible.

Note, this temporarily breaks LDN 8 settings, as coreboot will
ignore configuration for disabled devices.

Change-Id: I8585dd08eed407ab12258f2accaa63dab294e7d8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-21 14:49:15 +00:00
Nico Huber 9f7b36a540 mb/asus/f2a85-m_pro: Use `irq` in dt for single-byte registers
The `io` statement will prepare a 16-bit write, hence use `irq` for
miscellaneous 8-bit registers and fix actual `io` settings (i.e. merge
0x61 writes into 0x60). Note, using `irq` is still just a hack as these
are neither I/O nor IRQs, but it's common practice in coreboot.

Change-Id: I2e1c2286be726d126598cc4a97bb15a57faef42f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-21 14:37:48 +00:00
Paul Menzel 947dc64d21 mb/asus/f2a85-m_pro: Enable keyboard controller in devicetree
The mainboard has a PS/2 port, so enable the keyboard controller in the
devicetree.

The PS/2 keyboard now works in SeaBIOS payload, but not in GNU/Linux,
probably as ACPI code still needs to be added.

Change-Id: I7846633bc1a3bdf6bffae628e0542bb8fb684804
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-21 14:37:38 +00:00
Felix Held 4fc4a37038 3rdparty/amd_blobs: update submodule pointer
This now tracks a recently created upstream repository located at
https://github.com/amd/firmware_binaries

BUG=b:166107781

Change-Id: Ib193d646bb51cbf7b86f46828033e619c3f70e16
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46594
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21 13:45:30 +00:00
Kevin Chiu 9cc148d8c5 mb/google/zork: update USB 2.0 controller Lane Parameter for morphius
Enhance USB 2.0 SI by increasing the level of "HS DC Voltage Level"
and "Disconnect Threshold Adjustment".
COMPDISTUNE0: 0x3->0x7
TXVREFTUNE0: 0x6->0xf

BUG=b:162614573
BRANCH=zork
TEST=1. emerge-zork coreboot
     2. check U2 registers are set correctly
     3. test with servo v4 type-c, it's working expectedly.
     4. U2 SI pass

Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I278cc0aaddbc9fce595bf57ca69ee8abfc9f5659
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46537
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21 12:53:17 +00:00
Kevin Chiu 0088b3df28 mb/google/zork: Update telemetry settings for morphius
Correct the two load line slope settings for the SVID3 telemetry.
AGESA sends these values to the SMU, which accepts them as units
of current.  Proper calibration is determined by the AMD SDLE tool
and the Stardust test.

BUG=b:168265881
BRANCH=zork
TEST=emerge-zork coreboot

Change-Id: Id6c4f1a92d7f2ad293df7b63694e9665b85f8018
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46472
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21 12:48:12 +00:00
Michael Niewöhner fb620109a4 mb/google/dedede: drop obsolete ISST workaround
Early JSL silicon hang while booting Linux with ISST enabled. The
malfunctioning silicon revisions have been used only for development
purposes and have been phased out. Thus, drop the ISST workaround.

Change-Id: Ic335c0bf03a5b07130f79c24107a1b1b0ae75611
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-21 12:38:08 +00:00
Michael Niewöhner 63032439f4 {cpu,soc}/intel: replace AES-NI locking by common implemenation call
Deduplicate code by using the new common cpu code implementation of
AES-NI locking.

Change-Id: I7ab2d3839ecb758335ef8cc6a0c0c7103db0fa50
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-21 12:34:28 +00:00
Paul Menzel 2ac743330c mb/asus/f2a85-m_pro: Enable UART A in Super I/O
Currently, the serial console does not work.

With the serial port enabled in the vendor firmware, `superiotool` outputs
the global control register values below.

    Found Nuvoton NCT6779D (id=0xc562) at 0x2e
    Register dump:
    idx 10 11 13 14 1a 1b 1c 1d  20 21 22 24 25 26 27 28  2a 2b 2c 2f
    val ff ff ff ff 3a 28 00 10  c5 62 df 04 00 00 10 00  48 20 00 01
    def ff ff 00 00 30 70 10 00  c5 62 ff 04 00 MM 00 00  c0 00 01 MM

UART A needs to be enabled in CR 0x2a by clearing bit 7. Do this by
selecting the Super I/O Kconfig symbol `SUPERIO_NUVOTON_COMMON_COM_A`.
This changes the default value 0xc0 to 0x40.

Note, due configuring the system as legacy free with
`HUDSON_LEGACY_FREE=y`, AGESA in romstage disables the LPC controller in
`FchInitResetLpcProgram()`.

    coreboot-4.12-3417-g192b9576fe Tue Oct 20 09:15:53 UTC 2020 romstage starting (log level: 7)...
    APIC 00: CPU Family_Model = 00610f31

    APIC 00: ** Enter AmdInitReset [00020007]
    Fch OEM config in INIT RESET

`AmdInitReset() returned AGESA_SUCCESS` is not transmitted anymore. Only
when coreboot enables the LPC controller again in ramstage, serial output
continues.

    PCI: 00:14.4 bridge ctrl <- 0013
    PCI: 00:14.4 cmd <- 00
    PCI: 00:14.5 cmd <- 02
    PCI: 00:15.0 bridge ctrl <- 0013
    PCI: 00:15.0 cmd <- 00
    PCI: 00:15.1 bridge ctrl <- 0013
    […]
    done.
    BS: BS_DEV_ENABLE run times (exec / console): 0 / 30 ms
    Initializing devices...
    CPU_CLUSTER: 0 init
    […]

Note, due to incorrect Super I/O configuration in the devicetree, the boot
hangs in `PCI: 00:14.3 init` when doing `outb(0, DMA1_RESET_REG)`. This
will be fixed in follow-up commits.

TEST=Receive (some) coreboot log messages over the serial console.
Change-Id: I0aa367316f274ed0dd5964ba5ed045b9aeaccf8d
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-21 12:29:44 +00:00
Patrick Georgi 8fed9d638d mb/supermicro/x11-lga1151-series: Follow up GPIO macro changes
Following commit f50ea988b a couple of symbols are gone, so follow up
that change for this board as well.

Change-Id: I09fd3a107447eb45bb46b7f0f821377943f140b2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46621
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-21 10:09:40 +00:00
Michael Niewöhner f50ea988b0 soc/intel,mb/*: get rid of legacy pad macros
Get rid of legacy pad macros by replacing them with their newer
equivalents.

TEST: TIMELESS-built board images match

Change-Id: I078f9bb3c78f642afc6dcfd64d77be823a4485c2
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-21 07:16:01 +00:00
Michael Niewöhner dadcbfbe8c soc/intel: convert XTAL frequency constant to Kconfig
This converts the constant for the XTAL frequency to a Kconfig option.

Change-Id: I1382dd274eeb9cb748f94c34f5d9a83880624c18
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-21 07:14:00 +00:00
Michael Niewöhner fe6070f728 soc/intel/common: add Kconfig for PM Timer emulation support
Add a Kconfig for SoCs to indicate PM ACPI timer emulation support and
select it by the appropriate SoCs.

This Kconfig gets used in the follow-up changes.

Change-Id: I6ded79221a01655f298ff92b8bd2afabd1d2a3ff
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-21 07:13:22 +00:00
Sumeet R Pawnikar 7ea4372d82 mb/google/dedede/variants/drawcia: update PL1 max and min power values
Update PL1 max and min power values

BUG=None
BRANCH=None
TEST=build and verify on dralat system

Change-Id: I75d47fa721576564f71fbd5d5fd2e820fc3f1925
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-10-21 07:13:03 +00:00
Shelley Chen a45f8959c0 mrc_cache: Remove unnecessary data checksum calculation
When MRC_SAVE_HASH_IN_TPM is selected, we can just use the TPM hash to
verify the MRC_CACHE data.  Thus, we don't need to calculate the
checksum anymore in this case.

BUG=b:150502246
BRANCH=None
TEST=make sure memory training still works on nami

Change-Id: I1db4469da49755805b541f50c7ef2f9cdb749425
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-20 23:26:15 +00:00
Shelley Chen c1040f3ef4 mrc_cache: Add tpm_hash_index field to cache_region struct
Pull selection of tpm hash index logic into cache_region struct.  This
CL also enables the storing of the MRC hash into the TPM NVRAM space
for both recovery and non-recovery cases.  This will affect all
platforms with TPM2 enabled and use the MRC_CACHE driver.

BUG=b:150502246
BRANCH=None
TEST=make sure memory training still works on nami and lazor

Change-Id: I1a744d6f40f062ca3aab6157b3747e6c1f6977f9
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-20 23:26:01 +00:00
Shelley Chen df0481e9e1 security/vboot: Add new TPM NVRAM index MRC_RW_HASH_NV_INDEX
Add new index for MRC_CACHE data in RW.  Also update antirollback
functions to handle this new index where necessary.

BUG=b:150502246
BRANCH=None
TEST=make sure memory training still works on nami

Change-Id: I2de3c23aa56d3b576ca54dbd85c75e5b80199560
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-20 23:25:50 +00:00
Shelley Chen a79803cf29 security/vboot: Make mrc_cache hash functions generic
We need to extend the functionality of the mrc_cache hash functions to
work for both recovery and normal mrc_cache data.  Updating the API of
these functions to pass in an index to identify the hash indices for
recovery and normal mode.

BUG=b:150502246
BRANCH=None
TEST=make sure memory training still works on nami

Change-Id: I9c0bb25eafc731ca9c7a95113ab940f55997fc0f
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-20 23:25:39 +00:00
Shelley Chen 1fed53f08a mrc_cache: Move mrc_cache_*_hash functions into mrc_cache driver
This CL would remove these calls from fsp 2.0.  Platforms that select
MRC_STASH_TO_CBMEM, updating the TPM NVRAM space is moved from
romstage (when data stashed to CBMEM) to ramstage (when data is
written back to SPI flash.

BUG=b:150502246
BRANCH=None
TEST=make sure memory training still works on nami

Change-Id: I3088ca6927c7dbc65386c13e868afa0462086937
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-10-20 23:25:31 +00:00
Shelley Chen 9f8ac64bae mrc_cache: Add config MRC_SAVE_HASH_IN_TPM
Use this config to specify whether we want to save a hash of the
MRC_CACHE in the TPM NVRAM space.  Replace all uses of
FSP2_0_USES_TPM_MRC_HASH with MRC_SAVE_HASH_IN_TPM and remove the
FSP2_0_USES_TPM_MRC_HASH config.  Note that TPM1 platforms will not
select MRC_SAVE_HASH_IN_TPM as none of them use FSP2.0 and have
recovery MRC_CACHE.

BUG=b:150502246
BRANCH=None
TEST=emerge-nami coreboot chromeos-bootimage

Change-Id: Ic5ffcdba27cb1f09c39c3835029c8d9cc3453af1
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-20 23:20:30 +00:00
Tim Wawrzynczak 9eabeb53ab acpi: Skip writing references for disabled devices in Type-C config
When emitting ACPI tables for the Type-C connector class, skip writing
out a device reference if it is to a disabled device.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I84cc3e1a54e2b654239ad6e1a4662d582f3465cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-20 21:29:53 +00:00
Felix Singer 09917e10cb libpayload/storage/ahci: Use pci_dev struct in ahci_initialize()
Clean up ahci_initialize() by using pci_dev struct.

Change-Id: I2d5673c631d978d8ebd0c4a90962ab9cccaf40a2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-20 20:39:30 +00:00
Jonathan Zhang 320ad9351b cpu/x86/mtrr: add support for address space higher than 16TiB
On DeltaLake server, there are following entry in MTRR address space:
0x0000201000000000 - 0x0000201000400000 size 0x00400000 type 0

In this case, the base address (with 4k granularity) cannot be held in
uint32_t. This results incorrect MTRR register setup. As the consequence
UEFI forum FWTS reports following critical error:
Memory range 0x100000000 to 0x183fffffff (System RAM) has incorrect attribute Uncached.

Change appropriate variables' data type from uint32_t to uint64_t.
Add fls64() to find least significant bit set in a 64-bit word.
Add fms64() to find most significant bit set in a 64-bit word.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Change-Id: I41bc5befcc1374c838c91b9f7c5279ea76dd67c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-10-20 20:38:59 +00:00
Felix Singer b4b73d4995 libpayload/storage/ahci: Use pacc pointer to read device class
The PCI bus gets already scanned while gathering system information.
Therefore, use the pacc pointer from sysinfo_t to read the device class
of PCI devices instead of rescanning the bus.

Change-Id: I4c79e71777e718f5065107ebf780ca9fdb4f1b0c
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-20 20:35:47 +00:00
Felix Singer 9e5bc74cc7 libpayload/arch/x86: Introduce pacc pointer in sysinfo_t struct
Currently, the PCI bus gets scanned multiple times for various reasons
(e.g. to read the device class). Therefore, and in preparation to
CB:46416, introduce the pacc pointer in the sysinfo_t struct and scan
the PCI bus while gathering system information.

Change-Id: I496c5a3d78c7fb5d7c9f119a0c9a0314d54e729f
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-20 20:35:24 +00:00
Felix Singer 6034b0f184 payloads/coreinfo: Rename pci_scan_bus()
Rename pci_scan_bus() since the name is already used in libpayload.

Change-Id: I9d4a842b77f418484e1fcf60a79723480a53e30d
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-20 20:34:35 +00:00
David Wu ec1926aaff mb/google/volteer/var/terrador: Configure board specific DPTF parameters
Configure board specific DPTF parameters for terrador and todor

BUG=b:171019363,b:170699797
BRANCH=volteer
TEST=build and verify by thermal team

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I19935ca98ec7a078869e73d65ea471df70f37121
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-20 20:27:09 +00:00
Nick Vaccaro d888990cdc mb/google/volteer/variants/lillipup: add generic SPDs
Add generic LPDDR4x SPD support for the following three memory
parts:
• K4U6E3S4AA-MGCR
• H9HCNNNBKMMLXR-NEE
• MT53E512M32D2NP-046 WT:F

BUG=b:170264065
TEST=none

Change-Id: Ie3163763a0ce291f27c43181d35c070c218b461d
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-20 20:00:34 +00:00
Felix Held 059c7910eb 3rdparty/blobs: advance submodule pointer
The 3 commits commits from the blob repository this patch pulls in
remove executable flags from files in the repo that shouldn't have those
flags set:

* pi/amd/00660F01/FP4/AGESA.bin: Remove execute file mode bit
* Remove execute permission from all binaries
* Remove execute permission from plaintext files

Change-Id: I9c2b7c69f07e46bac466bfbfb277595c9fbc5a5a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-20 15:04:03 +00:00
Michael Niewöhner 7f8767de63 cpu/intel/model_{2065x,206ax}: fix AES-NI locking
MSR_FEATURE_CONFIG, which is used for locking AES-NI, is core-scoped,
not package-scoped. Thus, move locking from SMM to core init, where the
code gets executed once per core.

Change-Id: I3a6f7fc95ce226ce4246b65070726087eb9d689c
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-20 14:21:06 +00:00
Zheng Bao 944d00b28c soc/amd/picasso: Use readelf to find bootblock size and location
The Picasso build describes the DRAM region where the PSP places
our bootblock.  Rather than relying on Kconfig values, make the build
more robust by using the actual size and target base address
from the boot block's ELF file.

Sample output of "readelf -l bootblock.elf" is:
------------------
Elf file type is EXEC (Executable file)
Entry point 0x203fff0
There is 1 program header, starting at offset 52

Program Headers:
  Type     Offset   VirtAddr   PhysAddr   FileSiz MemSiz  Flg Align
  LOAD     0x001000 0x02030000 0x02030000 0x10000 0x10000 RWE 0x1000

 Section to Segment mapping:
  Segment Sections...
   00     .text .data .bss .reset
------------------
We can extract the information from here.

BUG=b:154957411
TEST=Build & boot on mandolin

Change-Id: I5a26047726f897c57325387cb304fddbc73f6504
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46092
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-20 12:29:32 +00:00
Angel Pons 77f340a707 sb/intel/ibexpeak: Align to coreboot's coding style
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.

Change-Id: I30512ef7ff7eb091e1f880c43a0a9ecf8625a710
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46530
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-20 11:52:16 +00:00
alec.wang e26e9b556d mb/google/dedede: Add P-sensor for Boten
Add devicetree and device ID for P-sensor

BUG=b:161217096
BRANCH=NONE
TEST=We can get the data from P-sensor if touch the SAR antenna.

Signed-off-by: alec.wang <alec.wang@lcfc.corp-partner.google.com>
Change-Id: I70f303995b106cca9758b36ebcde112ebcc90950
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-10-20 11:50:47 +00:00
alec.wang 3704b6d4ab mb/google/dedede: add PEN for Boten
Update devicetree of boten that enable stylus

BUG=b:160752604
BRANCH=NONE
TEST=build bios and verify function for boten

Signed-off-by: alec.wang <alec.wang@lcfc.corp-partner.google.com>
Change-Id: Ifbcac18fcf758f3d870a6af0d1b03e34369414c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-10-20 11:50:39 +00:00
Angel Pons dbe8415245 mb/asrock/b85m_pro4/Kconfig: Default to 2 MiB CBFS
I often find myself having to increase the CBFS size so that TianoCore
fits. Raise the default CBFS size to 2 MiB to alleviate this issue.

Change-Id: I871bb95dee55cc5bad68bb6e71f89ddfa4823497
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46488
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-20 11:04:59 +00:00
Bill XIE 14ee0f94f3 mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant
This adds another X11 series board, the X11SSH-F, which is similiar to
X11SSH-TF but differs in PCIe interfaces/devices, ethernet interfaces.

Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I92c32bff861f0b5697aea52ff282fae76b3b78ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-20 09:00:18 +00:00
Huayang Duan 075ad63a4f mb/google/asurada: Init dram in romstage
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Ied350570a695cca1424a6562e41120bcaf467797
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44568
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-20 06:59:34 +00:00
Huayang Duan c90a9e68b7 soc/mediatek/mt8192: Do dram fast calibration
Load params from flash and use those params to do dram fast calibration.

Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: I45a4fedc623aecfd000c5860e0e85175f45b8ded
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-10-20 06:58:48 +00:00
Yidi Lin 79a812e536 ec/google/chromeec: Add wrappers to get/set the voltage
Add APIs to get and set the voltage for the target regulator.

BUG=b:147789962
BRANCH=none
TEST=emerge-asurada coreboot

Change-Id: I0e56df45fc3309c387b9949534334eadefb616b2
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-10-20 06:58:11 +00:00
Michael Niewöhner 5611cfd55f soc/intel/cnl: lock AES-NI feature if selected
Lock AES-NI (MSR_FEATURE_CONFIG) to prevent unintended changes of
AES-NI enablement as precaution, as suggested in Intel document
325384-070US.

Locking is enabled by default (as already done in SKL and Arrandale) and
may be disabled by the newly introduced Kconfig in the parent change.

Tested by checking the MSR.

Change-Id: I79495bfbd3ebf3b712ce9ecf2040cecfd954178d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-19 21:02:59 +00:00