This change makes building coreboot related projects more unified.
Change-Id: I0f1181e2fffde1e03675523f7dc9eef3119052c3
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/71
Tested-by: build bot (Jenkins)
Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
upper 128 bytes of NVRAM (if enabled).
For most chipsets this means using I/O ports 0x72/0x73, but at least
on some VIA chipsets (I tested the VIA VT8237R on actual hardware)
these ports won't work and you have to use 0x74/0x75. Thus, make this
a Kconfig option for now.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3202 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This is the initial chunk of code written by me and copyrighted
by AMD. Includes everything but a few files that we pulled from
outside sources.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3170 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Patrick Georgi