Commit Graph

16217 Commits

Author SHA1 Message Date
Martin Roth 7051dea5f4 xcompile: Use local variables in the test functions
Using the local variables instead of positional parameters helps
readability.
- Add and use the local variables in testcc.
- Use the existing local variables in testld.

Change-Id: Ice13288b830a7aa043b360eaee8e36f060589a18
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12844
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07 17:24:50 +01:00
Martin Roth 033abe5e69 xcompile: use $() instead of backticks
While the backtick syntax isn't actually deprecated, the $() syntax
is preferred.  Since both styles were being used in this script, settle
on the new standard for all cases.

Change-Id: I33770d666781b4fa34c909411e0d220c2540dbb4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12843
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07 17:23:50 +01:00
Martin Roth af0216f1b8 xcompile: Only include arm64 erratum check in arm64 section
Clean up the output file a bit by only including the erratum
for arm64 into the that architecture section instead of
every architecture.

Change-Id: Ib6276f12aee5deb92a03e1c4fa2ad57db46bdc8f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12842
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07 17:23:02 +01:00
Martin Roth c4b684ebee xcompile: Put compiler variables outside of 'if' to allow checking
In order to be able to check the compiler versions, we need to be
able to access the compiler variables.  Move the original assignments
outside of the GCC check, and assign either the GCC or CLANG compiler
to the actual CC_ environment variable later.  This ends up with the
same value set, while allowing the compiler versions to be checked.

Change-Id: Iffad02d526420ebbdfb15ed45eb51187caaa94fb
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12841
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07 17:17:09 +01:00
Martin Roth f3e60d0d69 xcompile: Separate flags from clang executable
We already have a CFLAGS variable - Use it for all of the flags.

Change-Id: I22b4c5cf24b8743e85ffab29ddcccdc6c732ea3b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12840
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07 17:15:03 +01:00
Martin Roth 51d4de818d xcompile: Add XGCCPATH to clang compiler
The XGCCPATH prefix is on all the other tools and compilers,
so add it to clang as well, so it can be found correctly.

Change-Id: Ibc250a81433f37bbb0555d32605aebe3a68aaf40
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12839
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07 17:10:58 +01:00
Martin Roth 03f7a49f5a xcompile: Add separation for architectures to improve readability
- Add bar at the top of each architecture
- Make the architecture name and the TARCH_SEARCH to two lines
- Add a second line at the bottom of each architecture
- Add a comment about the two blank lines so they don't get
accidentally removed.

Change-Id: Ib4326bd94fe39b979244816ce54b752d083f6b16
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12838
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07 17:08:12 +01:00
Martin Roth c2054f3212 xcompile: Use tabs for indentation
Change-Id: I96a5048050f8016c3c569f20318b4d421a4470a7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12837
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07 17:07:21 +01:00
Martin Roth 4fdd8030a4 Makefile.inc: update location of dsdt
The dsdt file moved from the mainboard directory to the top level of
the build directory.  Remove it from the new location when cleaning.

Change-Id: If9f72c78e5c03e0db384b3181c169aa2ecbb5c18
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12822
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-01-07 16:56:47 +01:00
Martin Roth d59d1b61da intel/fsp1_1: Disable GOP support by default
Since the GOP drivers aren't published in the 3rdparty blobs repo yet,
disable the GOP support for now so that abuild can build these
platforms.

Change-Id: Ic98671c163b433ebde89c8bf240ef4b2be393586
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12829
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07 16:54:54 +01:00
Timothy Pearson 6dc53b485a mainboard/asus/kgpe-d16: Enable romstage microcode spinlocks
Change-Id: I93687efc5405359286d3197f0e59ec3b118c5100
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12809
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-07 16:53:00 +01:00
Timothy Pearson c764c7488b cpu/amd/microcode: Introduce CBFS access spinlock to avoid IOMMU failure
When microcode updates are enabled, this fixes an issue identical
to that described in GIT hash 7b22d84d:
 * drivers/pc80: Add optional spinlock for nvram CBFS access

Change-Id: Ib7e8cb171f44833167053ca98a85cca23021dfba
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12063
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-07 16:52:31 +01:00
Andrey Korolyov 046d217420 inteltool: add NetBSD compatibility
Tested on NetBSD-7.0/i386

Change-Id: I6a693633d3a80ea07ade233b1b4fd1c5a1412032
Signed-off-by: Andrey Korolyov <andrey@xdel.ru>
Reviewed-on: https://review.coreboot.org/12835
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07 15:33:13 +01:00
Andrey Korolyov 0ff8f9048b viatool: add NetBSD support
Change-Id: I033044e4b781475d6d60a49a61313a720103ce38
Signed-off-by: Andrey Korolyov <andrey@xdel.ru>
Reviewed-on: https://review.coreboot.org/12836
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-07 15:31:35 +01:00
Timothy Pearson 4ba946c1e1 Revert "util/crossgcc: Regenerate MPFR autotools files before build"
This reverts commit 68d0e4a5a1.

Special handling of MPFR is no longer needed with the latest
MPFR release.

Change-Id: I96d9ea92cfb74eed6af2ba62254f0678081e2b4f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12833
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07 15:16:17 +01:00
Timothy Pearson 74432e1b61 util/crossgcc: Bump MPFR version to 3.1.3
The current MPFR version contains a stale config.guess file
that requires special handling on ppc64el systems.  Bump
the MPFR version to the latest release.

Change-Id: I5e86c732c09f8a6a43f9812452124d64d337ea3f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12832
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-07 15:16:13 +01:00
Andrey Korolyov b47dc52f30 viatool: Add VIA C3 MSRs
Tested on C3/EPIA board and Linux x86

Change-Id: I8df551f4b385ee8702af78df00169bdc8e180925
Signed-off-by: Andrey Korolyov <andrey@xdel.ru>
Reviewed-on: https://review.coreboot.org/12851
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-06 22:04:04 +01:00
Timothy Pearson bfa19e1e47 cpu/amd/fam10h-15h: Add tsc_freq_mhz() function
The AMD Family 10h/15h processors use a TSC that increments at
the P0 core frequency.  Allow coreboot to query the TSC frequency.

Change-Id: I73ead4fd4af18991452d59985b667a54689778cd
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12834
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-01-06 17:46:21 +01:00
Aaron Durbin bb826ef661 cbfstool: correct add-master-header logic to match runtime expectations
The cbfs master header's offset and romsize fields are absolute values
within the boot media proper. Therefore, when adding a master header
provide the offset of the CBFS region one is operating on as well as
the absolute end offset (romsize) to match expectations.

Built with and without CBFS_SIZE != ROM_SIZE on x86 and ARM device. Manually
inspected the master headers within the images to confirm proper caclulations.

Change-Id: Id0623fd713ee7a481ce3326f4770c81beda20f64
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12825
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2016-01-06 17:45:15 +01:00
Aaron Durbin 12c55eda11 Revert "x86: Align CBFS on top of ROM"
This reverts commit 65e33c08a9.
This was the wrong logic to fix the master header.

Change-Id: I4688034831f09ac69abfd0660c76112deabd62ec
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12824
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-06 17:44:54 +01:00
Martin Roth f812c44f00 intel/braswell: Build in both C0 and 'other' vbios
The Braswell CPU seems to have two different Video BIOS roms, one for
the C0 revision, and one for other revisions.  Build them both into
the coreboot image, and let coreboot sort out which one should be used
at runtime.  This should allow one rom to be used for all revisions.

The initial reason for this patch was that the Kconfig symbol
C0_DISP_SUPPORT didn't exist, and was causing issues.  This
seems like the best way to eliminate the need for that symbol.

Change-Id: I5b9f225c0daf4e02fda75daf9cd07bb160bf0e0f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12826
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-06 17:41:49 +01:00
Martin Roth 331c722dd7 Documentation: Add information about patches from other git repos
This is more tribal knowledge that I don't think I've seen written down
anywhere else.  It's not a huge issue, but when looking through the git
log, it helps to be able to differentiate the information from the old
gerrit with the information from the new one.

Change-Id: I7993bda1e9aab79dc26940aaba9ddc52382ed0df
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12804
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-06 17:41:13 +01:00
Aaron Durbin 272a1f05b9 cbfstool: Add 'hashcbfs' command to compute hash of CBFS region.
For the purposes of maintaining integrity of a CBFS allow one to
hash a CBFS over a given region. The hash consists of all file
metadata and non-empty file data. The resulting digest is saved
to the requested destination region.

BUG=chrome-os-partner:48412
BUG=chromium:445938
BRANCH=None
TEST=Integrated with glados chrome os build. vboot verification
     works using the same code to generate the hash in the tooling
     as well as at runtime on the board in question.

Change-Id: Ib0d6bf668ffd6618f5f73e1217bdef404074dbfc
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12790
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-06 01:12:38 +01:00
Patrick Georgi 29a04d9ed1 cbfstool: keep cbfs master header pointer
Adding new files overwrote the header with the empty file (ie 0xff),
so carve out some space.

BUG=chromium:445938
BRANCH=none
TEST=none

Change-Id: I91c292df381c2bac41c6cb9dda74dae99defd81d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/12789
Tested-by: build bot (Jenkins)
2016-01-06 01:12:30 +01:00
Patrick Georgi bd0bb23838 cbfstool: Adapt "cbfstool copy" to only use fmap regions.
These need to go together, so the commit became a bit larger than
typial.

- Add an option -R for the copy source fmap region.
  Use: cbfstool copy -r target-region -R source-region.
- Don't generate a CBFS master header because for fmap regions, we
  assume that the region starts with a file header.
  Use cbfstool add-master-header to add it afterwards, if necessary.
- Don't copy files of type "cbfs master header" (which are what cbfstool
  add-master-header creates)
- Leave room for the master header pointer
- Remove -D command line option as it's no longer used.

BUG=chromium:445938
BRANCH=none
TEST=Manual test on image and integration test w/ bundle_firmware
     changes.
CQ-DEPEND=CL:313770,CL:313771

Change-Id: I2a11cda42caee96aa763f162b5f3bc11bb7992f9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12788
Tested-by: build bot (Jenkins)
2016-01-06 01:12:21 +01:00
Patrick Georgi 214e4af102 cbfstool: Use buffer over offset/size pair for cbfs_copy_instance
This allows adding support for FMAP based cbfstool copy more easily.

BUG=chromium:445938

Change-Id: I72e7bc4da7d27853e324400f76f86136e3d8726e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/12787
Tested-by: build bot (Jenkins)
2016-01-06 01:12:12 +01:00
Aaron Durbin cbb6c75061 commonlib: Add function to hash contents of a CBFS region.
Provide a common routine to hash the contents of a cbfs
region. The cbfs region is hashed in the following order:
1. potential cbfs header at offset 0
2. potential cbfs header retlative offset at cbfs size - 4
3. For each file the metadata of the file.
4. For each non-empty file the data of the file.

BUG=chrome-os-partner:48412
BUG=chromium:445938
BRANCH=None
TEST=Utilized in chromeos cros_bundle_firmware as well as at
      runtime during vboot verification on glados.

Change-Id: Ie1e5db5b8a80d9465e88d3f69f5367d887bdf73f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12786
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2016-01-06 01:12:04 +01:00
Patrick Georgi 3e6303ebe2 commonlib/cbfs: Add type ids for empty files
We will soon need to handle empty files.

Change-Id: Ia72a4bff7d9bb36f6a6648c3dd89e86593d80761
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/12785
Tested-by: build bot (Jenkins)
2016-01-06 01:11:54 +01:00
Aaron Durbin ca0a67624b commonlib: Prepare code to be included in cbfstool builds.
Some of the files need to be adjusted so that they can be used
both in cbfstool as well as coreboot proper. For coreboot,
add a <sys/types.h> file such that proper types can be included
from both the tools and coreboot. The other chanes are to accomodate
stricter checking in cbfstool.

BUG=chrome-os-partner:48412
BUG=chromium:445938
BRANCH=None
TEST=Built on glados including tools. Booted.

Change-Id: I771c6675c64b8837f775427721dd3300a8fa1bc0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12784
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-06 01:11:32 +01:00
Aaron Durbin 295d58bda8 commonlib: Add common cbfs parsing logic to coreboot and cbfstool.
To continue sharing more code between the tools and
coreboot proper provide cbfs parsing logic in commonlib.
A cbfs_for_each_file() function was added to allow
one to act on each file found within a cbfs. cbfs_locate()
was updated to use that logic.

BUG=chrome-os-partner:48412
BUG=chromium:445938
BRANCH=None
TEST=Utilized and booted on glados.

Change-Id: I1f23841583e78dc3686f106de9eafe1adbef8c9f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12783
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-06 01:11:19 +01:00
Aaron Durbin 990ab7efe5 commonlib: Add function to compute relative offsets from two region_devices.
Provide a helper function which returns the relative offset
between 2 region_devices that have a parent-child child relationship.

BUG=chrome-os-partner:48412
BUG=chromium:445938
BRANCH=None
TEST=Utilized and booted on glados.

Change-Id: Ie0041b33e73a6601748f1289e98b6f1f8756eb11
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12782
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-06 01:11:15 +01:00
Martin Roth af91b8b086 toolchain.inc: Test for valid toolchain when ANY_TOOLCHAIN is used
Even when ANY_TOOLCHAIN is selected, a valid compiler for the requested
architecture is needed.

Change-Id: If1a0a1ca6b726e8e58d29c69de93546510582548
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12681
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-06 00:09:40 +01:00
Martin Roth 31c4b64ab4 xcompile: Remove warnings about missing tools & architectures
Let toolchain.inc error out when the architecture or tool is missing.

Change-Id: I39a51e5a2c778d6bbc50354807e5e2b717fa9e52
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12682
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-05 22:08:47 +01:00
Timothy Pearson a9f62359e2 util/crossgcc: Add ppc64el support
Change-Id: I619f7c3cef7f0aaa6fccb3d52f2ac1f6ace6d0d6
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12818
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-01-04 21:54:38 +01:00
Timothy Pearson 68d0e4a5a1 util/crossgcc: Regenerate MPFR autotools files before build
The config.guess file included with MPFR is completely obsolete,
leading to build failures on ppc64el due to the system architecture
not being detected.  Regenerate the files from the host system via
automake before attempting to build MPFR.

Change-Id: I00fc16003906e373d112c25978197ac907adccfd
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12816
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-01-04 21:54:13 +01:00
Timothy Pearson 9631016660 util/crossgcc: Bump GMP version to 6.1.0
The previous official GMP release (6.0.0) contains a bug that
prevents compilation on ppc64el systems.  Increase version
to the latest version (6.1.0).

Bug details:

gcc build on ppc64el fails with:
(.text+0x4c): undefined reference to `BMOD_1_TO_MOD_1_THRESHOLD'

While I don't have an exact commit hash due to Hg use upstream,
a missing BMOD_1_TO_MOD_1_THRESHOLD define on ppc64el was quietly
fixed in Hg before the 6.1.0 release.

Change-Id: I1c05a1c194141db5f8522148c2e20e7558d34714
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12811
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-01-04 21:53:52 +01:00
Timothy Pearson 77133afe31 sb/amd/sr5650: Correctly locate CPU MMCONFIG resource
The code committed in GIT hash
 * 1eaaa0 southbridge/amd/sr5650:Add MCFG ACPI table support
did not correctly locate the CPU MMCONFIG resource, leading to failures
with operating systems and firmware (e.g. SeaBIOS) when the PCI
extended configuration space option was activated.

Due to the southbridge routing not being set up, MMCONFIG accesses were
targetting DRAM and therefore the PCI devices were not being configured.
The failure normally manifests as a system hang immediately after PCI
configuration starts.

Search for the CPU MMCONFIG resource on all domains below the root
device.

Change-Id: I0df2f825fef2de46563db87af78d0609ab3d8c5a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12821
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-04 16:59:21 +01:00
Martin Roth ada36d4cff toolchain.inc: Update help text, Add TODO.
- Update the help text to be more informative.
- Add todo about IASL - we shouldn't require it if the build doesn't
use it.

Change-Id: Iffeb94f78c1ae7535a8a7b9b0b9f1728301a42b3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12680
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-04 16:54:56 +01:00
Martin Roth 5981a63a9f toolchain.inc: Skip how to use any toolchain if it's selected
If ANY_TOOLCHAIN is selected, don't bother telling the user how to
do what they've already done.

Change-Id: I7182d18a91e832aa56638ec64fe8b3b0c38cff7a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12679
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-04 16:53:03 +01:00
Martin Roth 73b7997ba4 toolchain.inc: Move nocompile around entire check, Comment endifs
Move the check for NOCOMPILE flag around the whole block.  There's
no need to test COMPILERFAIL if NOCOMPILE is set.
Comment the endif lines to make it easier to understand.

Signed-off-by: Martin Roth <martinroth@google.com>
Change-Id: Id7bb5ca13e6bf1cabf4b7b2ff3256b47b966bac1
Reviewed-on: https://review.coreboot.org/12678
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-01-04 16:52:20 +01:00
Martin Roth a23e2ce5b7 toolchain.inc: Test for toolchain when using llvm/clang
Change-Id: I45ed5e289f9bfae90d71938243f921588b256e39
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12676
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-04 16:51:33 +01:00
Ben Gardner 2ab652f606 genbuild_h.sh: allow coreboot to be a git submodule
When coreboot is pulled in as a submodule, the .git "folder" is a file,
not a folder.  Use the '-e' test instead of '-d' to allow for that.

Change-Id: I0dd8866b0016f7ba099cdaf4d7db442ff22612b5
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/12819
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-01-04 16:41:40 +01:00
Kyösti Mälkki bb85f9eb73 Revert "AMD OemS3Save: refactor for Merlin Falcon"
This reverts commit d3deecdd9c.

Do not mix open-source AGESA and binary PI trees. Once you have
working S3 support for binaryPI platforms, add the adapted
oem_s3.c file as northbridge/amd/pi/oem_s3.c instead.

Change-Id: I7c981d0023a5c0225e046f9c0104acfa07436b79
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/12282
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2016-01-04 11:18:04 +01:00
Vladimir Serbinenko 42d55e0caf sb/intel/bd82x6x: Add missing PCIIDs for variants .
Change-Id: I917b8167a028aa9412b0cc6dedf8f09a1d1fae7f
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/12820
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-01-03 21:22:41 +01:00
Nico Huber 5aaeb27de9 nb/intel/gm45: Export low-power and (SFF) options
Make the low-power and small form factor (SFF) options overridable
from romstage main. Also disable both options by default. That's ok
as there aren't yet any in-tree users of the GS45 chipset. As a nice
side-effect, this adds X200s support to the lenovo/x200 port.

Change-Id: I94373851262e6d424cf4885ceca7260c31bc9f61
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/12814
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-31 17:45:09 +01:00
Nico Huber 0a207399ce lenovo/x200: Revise onboard IRQ routing
All southbridge interrupt pin and routing registers (D*IP and D*IR)
are left at their default values (see ICH9 datasheet) and this file
just has to reflect them.

Change-Id: I687262556d918311757fda9afda9ebfdd7edf947
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/12813
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-12-31 17:43:38 +01:00
Ted Kuo 08debacad1 superio/it8772f: Add register to set the default value of FAN speed
Original-Signed-off-by: Ted Kuo <tedkuo@ami.com.tw>

Change-Id: I70d7b572e9ae030136a39fb6fa933f486d559aef
Original-Reviewed-on: https://chromium-review.googlesource.com/262832
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Original-Commit-Queue: Ted Kuo <tedkuo@ami.com.tw>
Original-Tested-by: Ted Kuo <tedkuo@ami.com.tw>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/12799
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-31 17:40:17 +01:00
Ted Kuo 4e8f23b896 superio/it8772f: Add switch to enable HWM (Hardware Monitor)
Set up External Temperature to read via thermal diode/resistor
into TMPINx register by setting thermal_mode switch.

Original-Signed-off-by: Ted Kuo <tedkuo@ami.com.tw>

Change-Id: I0e8621b92faa5c6246e009d2f852c8d4db484034
Original-Reviewed-on: https://chromium-review.googlesource.com/260545
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Original-Tested-by: Ted Kuo <tedkuo@ami.com.tw>
Original-(cherry picked from commit 973e2d393f2595b756f8aa20f6fbe3b6e045621a)
Original-Reviewed-on: https://chromium-review.googlesource.com/262340
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/12798
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-31 17:39:47 +01:00
Ionela Voinescu 4f3d400a30 imgtec/pistachio: disable default RPU gate register values
The RPU Clock register defaults to on for all clocks.
This is modified to OFF, and the MIPS clock control modified to ON,
by default. This is because the linux kernel will manage the
clocks at all times, but the RPU can only disable clocks if the WIFI
module has been loaded.

Change-Id: I155fb37afd585ca3436a77b97c99ca6e582cbb4f
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12773
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-31 17:36:06 +01:00
Ionela Voinescu 3218e794ba imgtec/pistachio: memlayout: update GRAM size
GRAM is 421056 bytes. The end of the SRAM region (GRAM plays the role
of SRAM) was placed at a 4K aligned address, resulting in a size of
408KB.

Change-Id: I9fa32ab818d600e7447bcac895e4b8c438f2f99d
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12772
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-12-31 17:35:40 +01:00