Commit Graph

3778 Commits

Author SHA1 Message Date
Paul Fagerburg b4eb02aa8b hatch: automate creating a new variant in coreboot
To create a new variant of the hatch baseboard, we need to
add the variant's GBB_HWID and other information to Kconfig
and Kconfig.name, and set up a skeletal build based on the
hatch baseboard.

BUG=b:140261109
BRANCH=none
TEST=``./create_coreboot_variant.sh sushi && git show``
Kconfig will have three new lines for the SUSHI variant, and
Kconfig.name will have an entirely new section.
New files created are:
variants/sushi/Makefile.inc
variants/sushi/overridetree.cb
variants/sushi/include/ec.h
variants/sushi/include/gpio.h
variants/sushi/include/variant/acpi/dptf.asl

Also run the script with an existing board name to verify that you
can't create a variant that already exists.

Change-Id: I1a5b9c8735faafebb2e4e384cb3346867d64c556
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-09-19 09:37:12 +00:00
Sellerie 409a5dc8af util/inteltool: Add Intel HD 4400 (Haswell IGD)
Add the 8086:041e integrated graphics controller.
Adding the definition makes the Intel HD 4400 graphics
recognized by inteltool.

It is found on the ark page of e.g. the Intel i3-4130 CPU.

Change-Id: I6d6b2eaa7cc5aa3912592ed3fcb73751b224eede
Signed-off-by: Christoph Pomaska <sellerie@aufmachen.jetzt>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34588
Reviewed-by: Mimoja <coreboot@mimoja.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-15 17:18:22 +00:00
Manoj Gupta 297e9c826f futility: Use HOSTPKGCONFIG for host PKG_CONFIG
futility is built for the host. However, when cross-compiling,
the target's pkg-config is called to get the library paths which
can add paths from the cross-compilation tree instead of host.
e.g. /build/elm/usr/bin/pkg-config gets called instead of /usr/bin/pkg-config
. /build/elm/usr/bin/pkg-config adds the paths specific to the
cross-compilation target e.g. /build/elm/usr/lib instead of /usr/lib.

This causes linker to complain that files in library paths do not
match the architecture. BFD produces a warning while LLD errors out.

Fix this by passing PKG_CONFIG from host when building futility.

BUG=chromium:999217
TEST=coreboot builds
BRANCH=None

Cq-Depend: chromium:1778519
Change-Id: Id3afbf25001cf3daa72f36a290c93136cf9f162d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35316
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-11 20:41:47 +00:00
Elyes HAOUAS 9890bd98b0 crossgcc: Upgrade CMake to 3.15.3
Changes: https://cmake.org/cmake/help/v3.15/release/3.15.html

Change-Id: Id3283b4a091a5a8afd76235059636bba1c238f0f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-09-10 12:55:18 +00:00
Kyösti Mälkki 5e2a2cd5e7 util/sconfig: Expose usable PCI and PNP device names
These devices can be accessed directly by symbolname,
without a search and walk through the tree, as they
have static paths.

Change-Id: I711058f5c809fa9bc7ea4333aaebad6847ebdfd4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31933
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-06 00:18:29 +00:00
Maxim Polyakov 1317689066 inteltool: Add Skylake Xeon E DMI3 Host bridge Id
Tested on Intel S2600WF and SUPERMICRO MBD-X11DPL-I-O

Change-Id: I4b429536fc2db16d770120487e4c383da437593a
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-09-05 15:00:04 +00:00
Maxim Polyakov b89ce2e1b4 inteltool: add Lewisburg C62x GPIOs support
These changes are in accordance with the documentation:
[*] page 361, Intel(R) C620 Series Chipset Platform Controller Hub
    (PCH) Datasheet, May 2019. Document Number: 336067-007US

Tested on SUPERMICRO MBD-X11DPL-I-O and Intel S2600WF Wolf Pass

Change-Id: I43f8f3701de6ab7f89a78c2f5b939b5edd6d5b9d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-09-05 14:59:09 +00:00
Maxim Polyakov ec32e61bb8 inteltool: add Lewisburg family C62x chipset PCI IDs
These changes are in accordance with the documentation:
[*] page 39, Intel(R) C620 Series Chipset Platform Controller Hub
    (PCH) Datasheet, May 2019. Document Number: 336067-007US

Change-Id: I7a1ae0cc4c5d4b02599dfafd30f4a87b3ce74b74
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34941
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-04 08:16:04 +00:00
Raul E Rangel 7b2deddbb0 Kconfig: Write tmp files into same directory as target files
This removes the need for COREBOOT_BUILD_DIR in Kconfig. Since the
original files will be replaced with the tmp file, the parent directory
already needs to be writable.

Before this change, the tmp files would be created in the CWD (src) if
COREBOOT_BUILD_DIR was not specified.

BUG=b:112267918
TEST=emerge-grunt coreboot and verified no tmp files were created in the
src directory.

Change-Id: Icdaf2ff3dd1ec98813b75ef55b96e38e1ca19ec7
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34244
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-30 10:42:29 +00:00
Raul E Rangel d2f90a0659 kconfig: Use config's full path when generating tmp file
If KCONFIG_CONFIG is set to a full path, we should generate the tmp file
in the same directory instead of the current working directory.

BUG=b:112267918
TEST=emerge-grunt coreboot and verified with print statements that the
correct path was used.

Change-Id: Ia21e930a9b0a693f851c34bcde26b34886cbe902
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-30 10:41:38 +00:00
Raul E Rangel 4007d7f8c7 Makefile: Pass .xcompile into genbuild_h
I'm moving the .xcompile file into the $(obj) directory so we can leave
the source pristine. We need to pass the location of .xcompile into
genbuild_h.sh.

BUG=b:112267918
TEST=Ran genbuild_h with and without an .xcompile and verified it was
passed.

Change-Id: I8b3a75b478fad92a0b09246f0a00b0580f8c4aef
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-28 18:29:15 +00:00
Patrick Georgi 3beb108a62 what-jenkins-does: Use abuild's -Z option
This reduces disk usage during builds by removing all object files and
other intermediate files directly after a build instead of waiting for
the entire build to pass.

Change-Id: Ic2feecd58658e8bac8c6e7a851737784e35b83ef
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35112
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28 16:30:04 +00:00
Patrick Georgi 93bcebcfff abuild: Add -Z / --clean-somewhat option
This option removes everything in the build tree but coreboot.rom,
config.build, config.h and make.log - a useful subset of the tree for
further testing.

Change-Id: I27e559d8d7dc90d8fe5c4ed8e25249e202e5da36
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35136
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28 16:30:00 +00:00
Patrick Georgi 19e1d631e3 what-jenkins-does: keep essential artifacts arounds
Keep for every board: coreboot.rom, config.h, config.build

That way these can be used in follow-up jobs.

Change-Id: I5ca5cb84ab1bcffbc92a972980cd0769ebf02462
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-26 21:55:47 +00:00
Jacob Garber 1b7b7a3697 mb,autoport: Fix GCC 9 Port_List build error
Port_List is an array of 8 elements, and GCC 9 is warning that there
are no 'others' when all 8 elements are explicitly initialized, which is
causing the build to fail. Remove the 'others => Disabled' clause to
silence this.

Change-Id: Id082e7a76641438f3fb4c4d976dbd254a7053473
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34918
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-20 15:31:54 +00:00
Jacob Garber 4f387e1240 util/nvidia/cbootimage: Update to upstream master
This brings in 4 new commits from the upstream repository.

65a6d94 Free image buffer on read error
9de64c7 Fix various abort(), crashes, and memory errors
7c9db58 Bump to version 1.8
3b3c3cc Use C99 uintXX_t instead of implementation-specific u_intXX_t types

Change-Id: If949309a7481537de6529c205fe745d5509906a9
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-08-20 15:28:49 +00:00
Jacob Garber 5fa756cc97 util/cbfstool: Remove unused assignment
This variable is overwritten on one branch of the next if statement, and
the other branch returns, so this assignment does nothing.

Change-Id: I63737929d47c882bbcf637182bc8bf73c19daa9f
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: scan-build 8.0.0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-08-20 15:20:30 +00:00
Matt Parnell 063b162008 util/superiotool: add IT8987 detection and register support
Signed-off-by: Matt Parnell <mparnell@gmail.com>

Change-Id: I3674bc7035a28c4174a1bc1ee014c88e0ac96e8d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-08-19 10:36:17 +00:00
Raul E Rangel cccb815c5e util/abuild: Clean up the missing_arches check
This change adds the following improvements:
* Easier to read.
* Checks to see if .xcompile is complete.
* Checks the make return code. This will catch if .xcompile is missing.

BUG=b:112267918
TEST=Modified my .xcompile and ran abuild and verified that
missing_arches got set correctly. Also deleted .xcompile and verified
there was a failure.

Change-Id: I7604d431f398fc0c80a857a0c7c21e164004cc99
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-08 03:42:24 +00:00
Arthur Heymans 3071c8114a util/arm_boot_tools/mksunxiboot: Remove tool
Support for allwinner sunxi was dropped.

Change-Id: I0d4cbcac3e96e381185338455a773bcccc3401ad
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34688
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-05 08:27:40 +00:00
Martin Roth 0baad5ad6d util/nvidia: Change ENODATA to ENOATTR for FreeBSD
FreeBSD doesn't have ENODATA defined, so the cbootimage utility wouldn't
build.  It looks like the BSDs use ENOATTR in the same fashion, so
update the error to use that.

Change-Id: Ic70710d5726476755585fd1a3ae3f256a430e8df
Signed-off-by: Martin Roth <martinr@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/28365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-08-03 17:20:42 +00:00
Raul E Rangel c989e0bd56 util/abuild: Use realpath for FAILED_BOARDS/PASSED_BOARDS
The abuild script will `cd` into the build directory. FAILED_BOARDS
defaults to a relative path, so it ends up trying to echo into a
directory that doesn't exist.

If we set the realpath to the file then we can correctly update the
failed/passed boards file.

BUG=none
TEST=make what-jenkins-does and verified there was a failed_boards and
passed_boards in coreboot-builds.

Change-Id: Ib3af003b090668380a9425583a9f4367023820a6
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-08-03 17:11:17 +00:00
Felix Singer f98dc48386 inteltool: Add GPIO support for Skylake-H chipsets
PCH IDs:
  - H170, Z170, Q170, Q150, C232, QM170, HM170

Used documents:
  - Intel 332690-005EN

Change-Id: I33bf67c0c9d8a5a079fcc78f24a43bc421b2910c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-31 18:06:07 +00:00
Patrick Georgi fa781fa52c util/release/genrelnotes: Emit more markdown-ish output
It's better to format lists with bullet points.

Change-Id: I503ef2dea9146d67c220236b8a5b64c2ba2d794f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34504
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31 08:47:24 +00:00
Patrick Georgi b11a342703 util/release: Make sure intel-microcode ends up in the blobs tarball
Change-Id: Ib41c196cf543070e237d240cf31e019c9b2bf339
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34503
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31 08:47:21 +00:00
Pavel Sayekat 9429b70f91 util/inteltool: Add H110 GPIO support
Change-Id: I0ce22da3d201c2443bb5a7fcfd779c2c6ee71577
Signed-off-by: Pavel Sayekat <pavelsayekat@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34602
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-29 18:06:13 +00:00
Marshall Dawson b85ddc5d44 util/amdfwtool: Correct fletcher32 algorithm
Change the fletcher32 checksum calculation to match PSP and AGESA
implementations.

The symptom of the failure has only been noted in Picasso's BIOS
Directory Table, when a BIOS binary image of different sizes were
passed to amdfwtool.  The PSP halts the boot process with the bad
BDT checksum, and if allowed to continue, AGESA asserts later due
to a failed BDT verification.

This version has been verified to produce the same result as found
at https://en.wikipedia.org/wiki/Fletcher%27s_checksum.

TEST=Build apu2, bettong, grunt and verify before/after amdfw.rom
     is unchanged.

Change-Id: I2ba2c49a70aa81c15acaab0be6b4c95e7891234f
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-29 05:58:08 +00:00
Martin Roth 57e257d987 util/abuild: Add asserts flag to getopts
We recently added the --asserts option to set asserts as fatal in abuild
but didn't add the flag to getopts, so it gets rejected as an invalid
argument.

Change-Id: Ic70e9a2bec039955cf62c175875598773ade2d3d
Signed-off-by: Martin Roth <martinr@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-28 09:58:20 +00:00
Patrick Georgi 99f0e0c4dc util/testing: Allow adding abuild options to what-jenkins-does
JENKINS_ABUILD_OPT is passed in abuild's command line

Change-Id: I5e7fbb77a3c6592a4414a6c1e3f7556c7e3a824c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2019-07-26 11:07:01 +00:00
Patrick Georgi 3a0cad30f2 util/abuild: Add --asserts flag
This enables fatal asserts, which can be useful to get better
diagnostics by the build tools (both compilers and static analysis.)

Change-Id: I1e1653f465fe1f545878d6eec83b8645dc17d9cb
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2019-07-26 11:06:29 +00:00
Patrick Georgi c199973f78 util/testing: Factor out abuild options in what-jenkins-does
The abuild command line can vary a lot depending on options and the line
became unwieldy (plus, it's on two lines because we run abuild twice),
so factor it out into a variable.

Change-Id: I102756fb95c93f542d534610bf9737a13ac1ad62
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2019-07-26 11:06:22 +00:00
Nico Huber 517ed8b0e4 xcompile: Store XGCCPATH
It can be useful to pass along to external projects, e.g. payloads.

Change-Id: I61c7bb162e2737a562cbef08b32ebbafd9cf1cb0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-25 20:18:52 +00:00
Martin Roth d70f5fae1c crossgcc: Add nasm to toolchain
Tianocore payload uses nasm.  Supply it in the coreboot toolchain
instead of relying on system version.

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I086cbe6c46f7c09b2a7a83e177b32fd1bdf99266
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33024
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25 19:05:22 +00:00
Elyes HAOUAS 1662c0bbfe crossgcc: Upgrade CMake to 3.15.0
Changes: https://cmake.org/cmake/help/v3.15/release/3.15.html

Change-Id: Ic9db9050bec45d33d56ee53e3692276494f306de
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33053
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25 18:41:23 +00:00
Elyes HAOUAS 43e9bd6b9c crossgcc: Upgrade acpica to version 20190703
Changes: https://acpica.org/node/171

Change-Id: I3883718623e4a23a901a446f738a9e8c988d8433
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-25 18:40:56 +00:00
Elyes HAOUAS 1e9473cc25 crossgcc: Upgrade Expat to version 2.2.7
Change-Id: If3611494228a9228b0b323038ba1e884a1bde10f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33825
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25 18:33:01 +00:00
Elyes HAOUAS 7e3eab2c13 crossgcc: Upgrade Python to version 3.7.4
Change-Id: I2d4a93fa43cf662685d4c439bcff04e338d51375
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32077
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25 18:32:39 +00:00
Elyes HAOUAS 31270646ba crossgcc: Upgrade GDB to version 8.3
Change-Id: I7a85ad171fa259e0dcb0019941d735ef41511737
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32754
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25 18:28:00 +00:00
Jacob Garber 52f0e84ba7 util/*/Makefile: Rename -W to -Wextra
-W is the old name for -Wextra, so let's rename it to be consistent with
the rest of the utility Makefiles.

Change-Id: I0e50f13d2617b785d343707fc895516574164562
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-23 09:10:47 +00:00
Jacob Garber 3a82e9b8a3 util/cbfstool/flashmap: Fix memory leaks on failure
Fix several memory leaks on failed printing or tests. These don't matter
much, but it keeps Coverity happy.

Change-Id: Ie750acb50ae1590c3aea533338a8827c03459c1a
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 130245{1,2,3}
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-21 18:54:43 +00:00
Patrick Rudolph b30a47b841 sb/intel/{bd82x6x|ibexpeak}: Drop p_cnt_throttling_supported
The processor P_BLK doesn't support throttling. This behaviour could be
emulated with SMM, but instead just update the FADT to indicate no support
for legacy I/O based throttling using P_CNT.

We have _PTC defined in SSDT, which should be used in favour of P_CNT by
ACPI aware OS, so this change has no effect on modern OS.

Drop all occurences of p_cnt_throttling_supported and update autoport
to not generate it any more.

Change-Id: Iaf82518d5114d6de7cef01dca2d3087eea8ff927
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-07-19 15:06:23 +00:00
Kyösti Mälkki 1557a67c83 device: Move pci_irqs outside DEVTREE_EARLY
Only needed in ramstage, and only for MP tables.

Change-Id: Ia7c1e153b948aeefa4c3bea4920b02a91a417096
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33922
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-17 16:05:28 +00:00
Jacob Garber 198c2e63ac util/inteltool: Shrink buffer size
512 bytes is much too big for this buffer, which only needs to hold a
path that will have a length of at most 20. The large buffer size also
triggers a -Wformat-truncation warning with GCC since it is later
printed into the smaller temp_string array, so shrink it down to
something reasonable.

Change-Id: I6a136d1a739c782b368d5035db9bc25cf5b9599b
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-16 16:25:11 +00:00
Martin Roth d3ce8c8442 util/amdfwtool: Add option to build verstage binary into the PSP
For AMD's Family17h processors, verstage needs to be run in the PSP,
before memory is initialized.  This adds that binary into the PSP
directory.

See the Family17h documentation in the coreboot documentation directory
for more information.

BUG=b:137338769
TEST=Build, add test binary to mandolin board, boot

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I29002a1af51c59a2e6c715e15f3dc63e59cd5729
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-07-15 17:47:04 +00:00
Martin Roth ec933135ce util/amdfwtool: Do misc cleanup
- Correct command line argument for microcode patches from -u to -O
- Add #if PSP_COMBO around new_combo_dir() as it's only called when
that's enabled.
- Remove unused variable in integrate_bios_firmwares()
- Correct enum type from amd_fw_type to amd_bios_type in
register_fw_addr()

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I51c6dbe700505bc2e32443000ae55cb644051e42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-07-15 17:46:46 +00:00
Keith Short 31af70dd96 util/testing: Ensure coreboot-gerrit fails if libpayload build fails
The JUnit output from the libpayload builds was getting deleted by the
coreinfo build.  Move the libpayload to later in the coreboot-gerrit
job.

Also add messages to stdout indicating the various libpayload configs
that are built and a message indicating when all libpayload builds are
complete.

BUG=b:137380189
TEST=Upload test commit that includes a libpayload compile error and
verify buildbot fails.

Change-Id: I43b55f402216582dcf81be34171437be345572ab
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34183
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-13 18:33:51 +00:00
Maxim Polyakov aae7552b24 util/superiotool/aspeed: fix SUART number
Change-Id: I20c4436d414bc6b9a3ff5138d6fd59ead8fd4a47
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-12 12:27:45 +00:00
Werner Zeh ac14a40d0e util/sconfig: Fix compile error with older glibc-headers
In patch e29a6ac16a (util/sconfig: Add
commonlib/helpers.h) helpers.h has been added to the include-list.
In headers.h we have a definition for __unused:

On a host system environment where glibc-headers-2.12-1.212 is
installed, a file included by <sys/stat.h> called bits/stat.h have the
following content on line 105 and onwards:

	long int __unused[3];
where the mentioned part is part of the structure called struct stat.

If we include commonlib/helpers.h _before_ <sys/stat.h>, the symbol for
__unused will be defined by the preprocessor to be
'__attribute__((unused))', therefore the above mentioned structure member
will be expanded by the preprocessor to be
'long int __attribute__((unused))[3];', which is not a valid C syntax
and therefore produces a compile error for sconfig tool.

To handle this case we need to make sure commonlib/helpers.h is included
_after_ <sys/stat.h>. As the needed part of stat.h (which is
struct stat) is only used in main.c it is safe to move the include from
sconfig.h directly into main.c while taking care of the order.

Change-Id: I9e6960a318d3dd999e1e9c1df326d67094f3b5ce
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-12 11:02:29 +00:00
Jacob Garber 967f862e47 util/amdfwtool: Close file descriptor on error
Prevents a resource leak.

Change-Id: Id5da2df3e37cba499cd2e9a7c3ede34e4de2ed77
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1402139
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-10 18:21:41 +00:00
Jacob Garber 3dbaf4f336 util/romcc: Correct format specifiers
The right specifier for printing ptrdiff_t is %td.

Change-Id: I7bae4d47f15cfe85ca870f687c6f702339f680bb
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 14021{64,68,76}
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-10 18:21:23 +00:00
Jacob Garber 2e31ea05bb util/cbfstool: Close file on error
Prevents a resource leak.

Change-Id: I032227228c8e37e989960ad6292ded39b81835a9
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1383919
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-10 18:21:00 +00:00
Kyösti Mälkki e29a6ac16a util/sconfig: Add commonlib/helpers.h
Followup work injects ARRAY_SIZE() in static.c

Change-Id: Ifbcaa1b613aef312d3876e8b536499a9f01a8d19
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-10 10:18:13 +00:00
Kyösti Mälkki 5ccce7cdc7 util/sconfig: Declare the repeated devicetree storage
With DEVTREE_EARLY we could create incomplete device
objects with topology links removed to reduce footprint
for bootblock.

Declare everything with 'static __unused DEVTREE_CONST'
to avoid compiler errors and to not expose unusable
device object names to global scope.

Change-Id: Ie4cb9e75f179f44edf4f8256ad8320bc2d4ae71a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-07-10 10:17:48 +00:00
Nico Huber 45564050ec crossgcc: Fix runtime initialization of a constant
GNAT had a constant initialized at runtime which led to trouble
with compilers that decided to place it into an actual constant
section (e.g. GCC 9). Usually, this would be handled gracefully
if the Ada compiler knew about the runtime initialization. How-
ever, as the initialization was done by taking the address of
the variable, the compiler had no clue.

Change-Id: I73ce4cadc612c814ed2e22b44f429af2ad3db288
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34147
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-09 10:42:08 +00:00
Patrick Rudolph 674bb3bf65 util/superiotool: Add AST2400
Add support for AST2400 Super I/O.

The device doesn't have an ID register, so probe for scratch register
not to read as 0xff.

Tested on platform which has an AST2400.

Change-Id: I86af69c6b2ccefe2c88eef875bc858239df834f1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-07-08 16:13:29 +00:00
Jacob Garber 2d58bf6a03 util/cbfstool: Prevent overflow of 16 bit multiplications
Considering the following integer multiplication:

    u64 = u16 * u16

What on earth, one might wonder, is the problem with this? Well, due to
C's unfortunately abstruse integer semantics, both u16's are implicitly
converted to int before the multiplication, which cannot hold
all possible values of a u16 * u16. Even worse, after overflow the
intermediate result will be a negative number, which during the
conversion to a u64 will be sign-extended to a huge integer. Not good.

The solution is to manually cast one of the u16 to a u32 or u64, which
are large enough to not have any overflow and will prevent the implicit
conversion. The type of the u64 is preferred, though a u32 is used
instead of size_t, since that can change depending on the platform.

Change-Id: I5391221d46d620d0e5bd629e2f9680be7a53342e
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 12297{03,04,05,06,07,08,09,10}
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-07 20:59:04 +00:00
Jacob Garber 96e0ce30db util/nvramtool: Mark out_of_memory() as noreturn
This silences several false positives from scan-build.

Change-Id: I327a967c75d6aeec0b3aba16ee696dbae8cf997d
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-07 20:55:59 +00:00
Jacob Garber b592917dcf util/nvramtool: Enable -Wmissing-prototypes
Change-Id: Id751250b07a495dc25293ff703602bfefa9011bd
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-07 20:54:04 +00:00
Jacob Garber f2a2137ae2 util/nvramtool: Make internal function static
This function is only used in this file, so it can be made static.

Change-Id: I90e673da91eb926424d1730c268860da7fa1627b
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-07 20:26:44 +00:00
Jacob Garber 4177bedd65 util/nvramtool: Include missing header
The prototype for is_ident() is in this header, so include it.

Change-Id: I45e0d58d1b891b18b3eb7741897ab691188a2bd9
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-07 20:26:25 +00:00
Jacob Garber 57f2188d86 util/inteltool: Enable -Wmissing-prototypes
Change-Id: I6bf041d089498780ea2b7c52402d7452d44d3f87
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33946
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-07 20:23:55 +00:00
Jacob Garber 6faccd1f00 util/inteltool: Make internal functions static
None of these functions are used outside of the files they are defined
in, so they can all be static.

Change-Id: Ie00fef5a5ba2779e0ff45640cff5cc9f1d096dc1
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-07-07 20:23:42 +00:00
Marshall Dawson 30cf155168 util/cbfstool: Add AMD BIOS compression tool for PSP
Add a utility to generate a compressed BIOS image for AMD Family 17h.

If the input is an elf file, the utility extracts the program portion
for compression.  Otherwise the file is compressed as-is.

In modern AMD systems, the PSP brings up DRAM then uncompresses the
BIOS image into memory prior to x86 beginning execution.  The PSP
supports a zlib engine, and interprets the first 256 bytes as a
header, where offset 0x14 containing the uncompressed size.  For
further details, see AMD Platform Security Processor BIOS Architecture
Design Guide for AMD Family 17h Processors (NDA only, #55758).

BUG=b:127766506
TEST=Use with WIP Picasso

Change-Id: Id1c54e0a6dae9e4a0362c6635fe8b8aa48a369d8
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2019-07-03 21:28:43 +00:00
Patrick Georgi 848e30daa1 cbfstool: show "preserved" flag in cbfstool layout output
The flag is useful for updaters to determine which areas to leave
alone, such as VPD (vital product data) regions that are set in
factory and might contain unique (MAC addresses) or hard to obtain
(calibration output) data.

It's also useful to see which regions are marked as such.

Change-Id: Ic0a229d474b32ac156cfabc917714ce9d339bac6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-02 18:48:02 +00:00
Jacob Garber 0476332161 util/cbmem: Enable -Wmissing-prototypes
Change-Id: Ia8482dc9b6ad800826152c2d3e9813190b0b574e
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-02 16:12:21 +00:00
Jacob Garber 79a2f4767d util/cbmem: Make internal functions static
These functions are only used in cbmem, so they can be made static.

Change-Id: I21f7d7c21064a8ae951e6d96b28c2ddcf52c0006
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-02 16:12:09 +00:00
Jacob Garber 4d543b5aa6 util/cbmem: Enable -Wextra
This enables extra useful warnings.

Change-Id: I4afbbb0fefb32a7d954aafd87df17075b0abe6f7
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-02 16:11:57 +00:00
Jacob Garber 414d5d8698 util/cbmem: Use correct integer types for loop indices
Make sure that the type of the loop index matches the type of the upper
bound. This fixes several -Wsign-compare warnings.

Change-Id: Iaa94ce93bc35d523bc782ad914bfd283606becac
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-02 16:11:46 +00:00
Patrick Georgi 328d2e2a7d util/docker/coreboot.org-status: Add more "nice" names for CPUs
It's not perfect and we'll need to find a better place for that,
but I'll look into that as part of the big board-status rework.

Change-Id: I2ae50c58e3796563e0b2370105abc82b7e2e042a
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-02 16:08:18 +00:00
Patrick Georgi 3b34ef29b3 util/release: add more categories
Change-Id: I73cd50da7b2f1aaf1ab05daad4997c5e48172f25
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-02 16:08:05 +00:00
You-Cheng Syu 1430b3995f util/cbmem: Update banner string regular expression
Banner string format has been changed (CB:30935). We should update our
regular expression correspondingly.

Also add "verstage" into the stage search list since some boards (e.g.,
Kukui) might start console initialization at verstage.

Change-Id: I16eba3ac5e203e80b0bfd42a4294401dbccd4463
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-01 21:21:57 +00:00
Jacob Garber 02b1e20f00 util/ifdtool: Enable -Wmissing-prototypes
Change-Id: Idc31144024f785a42cbad78bf2c965d08dcc5178
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-01 14:30:53 +00:00
Jacob Garber 595d926bc2 util/ifdtool: Make internal functions static
These functions are only used in ifdtool, so they can be made static.

Change-Id: Ia48bfecb89a7445dbd0f140acb5ac0592da2ebe7
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-01 14:30:42 +00:00
Pandya, Varshit B 36cc664bc7 util/cbfstool/ifittool: use strtol function instead of atoi
Fix error "Invalid option -A" by adding "A" to options list.

Also, atoi does not parse hex string, for instance 0x200 is interpreted as 0,
and this causes a failure when updating second FIT table using -j option.
Use strtol instead of atoi

BUG=none
BRANCH=none
TEST=Build and boot hatch after enabling dual bootblock feature.

Change-Id: Ib227437f88ffcccda1ce2f20a9ab098e5aa091c7
Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-07-01 13:44:48 +00:00
Pavel Sayekat 40dc75efcb util/superiotool/nuvoton.c: Minor tag update/removal
Signed-off-by: Pavel Sayekat <pavelsayekat@gmail.com>
Change-Id: Ic193f31b9776683849578bf9009c51bf22d1dae6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-07-01 08:30:44 +00:00
Joel Kitching b4a1981289 cbfstool/fit: need inttypes.h for PRIx64
This is causing coreboot build in Chromium OS to fail.

BUG=None
TEST=emerge-eve coreboot
BRANCH=none

Change-Id: I4faa140b3046651b4ed0a9aeefe437048c6ef0da
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-06-26 09:19:00 +00:00
Elyes HAOUAS 741000d31b util/cbfstool/flashmap: Correct local includes
Change-Id: I78ba7afd2085c7e9c93e892470111bfee154bb04
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-06-24 10:52:53 +00:00
Patrick Rudolph 9ab80a33a5 cbfstool: Drop update-fit option
The ifittool is used instead. Drop old code.

Change-Id: I70fec5fef9ffd1ba3049badb398783f31aefb02f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-06-24 09:45:00 +00:00
Philipp Deppenwiese 5ada0023d1 cbfstool: Add ifittool
Add the IntelFirmwareInterfaceTable-tool to modify the FIT.
As cbfstool is overloaded with arguments, introduce a new tool
to only modify FIT, which brings it's own command line syntax.

Provide clean interface to:
* Clear FIT
* Add entry to CBFS file
* Add entry to REGION
* Delete entries
* Add support for types other than 1
* Add support to dump current table
* Add support for top-swap
* Sort entries by type

Most code is reused from existing cbfstool and functionality of cbfstool
is kept. It will be removed once the make system uses only ifittool.

Based on "Intel Trusted Execution Technology (Intel TXT) LAB Handout"
and https://github.com/slimbootloader/slimbootloader .

Change-Id: I0fe8cd70611d58823aca1147d5b830722ed72bd5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-06-24 09:42:31 +00:00
Arthur Heymans 6beaef983a sb/intel/bd82x6x: Set up io_gen_dec in romstage based on devicetree
Set up generic decode ranges based on the devicetree settings.

Change-Id: Ie59b8272c69231d6dffccee30b4d3c84a7e83e8f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-06-21 09:00:57 +00:00
Nico Huber 6d7564cdfe Move -Wlogical-op into xcompile
Clang doesn't know `-Wlogical-op`, so let's move it into xcompile where
we can easily distinguish between the two. However, this requires us to
split out `GCC_ADAFLAGS*` from `GCC_CFLAGS*`.

Change-Id: I6a50de0bc5372f61337f237383d32645ba86b0fd
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33579
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-21 08:44:49 +00:00
Marshall Dawson ce2b2bad77 util/amdfwtool: Update for Family 17h
Add arguments for additional PSP blobs needed with Family 17h support,
including the new AGESA binary loaders.

Create a new type of structure and entry for a BIOS directory table,
containing PMU code, microcode updates, as well as the BIOS initial
code.

Details on each of these items may be found in the AMD Platform Security
Processor BIOS Architecture Design Guide for AMD Family 17h Processors
(NDA only, #55758).

BUG=b:126593573
TEST=Used with WIP Picasso

Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-19 19:14:39 +00:00
Nico Huber c6a584182e xcompile: Fix harmless typo
As CFLAGS_GCC and CFLAGS_CLANG are still the same at this point, this
just removes some duplicate flags.

Change-Id: I532e5fa146891b70e4c1949c614b280055524593
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-06-19 11:27:09 +00:00
Pavel Sayekat cc48009631 util/superiotool/nuvoton.c: add NCT5539D register dump
Values taken from NCT5539D datasheet V1.1 (June 30th, 2015).
Tested on ASUS-H110M-E/M.2 mainboard (Kabylake i3-7100 CPU).

Change-Id: Ib55068035ca574b22d0fea81e1a291f7cf0329d3
Signed-off-by: Pavel Sayekat <pavelsayekat@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-14 12:17:26 +00:00
Patrick Georgi 7945f75417 lint/clang-format: set to 96 chars per line
coreboot has decided to go with 96 characters per line.

Original Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original Reviewed-on: https://review.coreboot.org/c/coreboot/+/31651

Change-Id: I9c99e5cca6548e23cf755dc37193ff2aa669ac10
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-06-13 20:14:00 +00:00
Marshall Dawson 24f73d4f53 util/amdfwtool: Add multilevel PSP directory table
Add the ability to generate two PSP directory table levels.  The PSP
is capable of supporting two levels, with the primary intended to
remain pristine for the life of the system, and the second updatable.
In the event the second becomes corrupted, the primary is still
sufficient to allow a recovery of the other.

This patch modifies no directory table structures currently in use.
The soc or southbridge must pass an argument to force building the
secondary table.

BUG=b:126593573
TEST=Used with WIP Picasso

Change-Id: Id321f5142e461d4a7f3343c0835a09a1a1128728
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-13 18:01:07 +00:00
Marshall Dawson 7c1e1428ad util/amdfwtool: Align PSP NVRAM
Align the PSP's NVRAM item since it's intended to be updateable
in the flash device.

Change-Id: I6b28525624b95b411cc82de0cbe430ea7871149d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-06-13 18:00:27 +00:00
Marshall Dawson ef79fccf4e util/amdfwtool: Add argument for soft fuse override
Allow the soc build to pass a soft fuse value to the utility.  This
helps maintain compatibility across PSP generations.

Add a generic 'other' item to the amd_fw_entry structure that may
be used by non-fuse entries in the future.

TEST=Verify google/grunt amdfw.rom unchanged before and after.
     Compare internal board using override before and after.

Change-Id: I26223f0b42ad28c43d9bd87419a2a8f719ee91cb
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-06-13 18:00:05 +00:00
Felix Held e5b05d61df util/superiotool: clarify usage of MISC and NANA defines
Change-Id: I0b3c5c810bfb05eaec13511391ecd55d7b9eb4e8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-13 14:07:57 +00:00
Iru Cai cd980abe18 autoport: Generate a libgfxinit template when IGD is detected
Change-Id: I213628e525cc11c502de7d538bd60f49f3a930b9
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-06-09 17:10:44 +00:00
Duncan Laurie 7775d67218 ifdtool: Enable GbE/PDR/EC region access only if they exist
Instead of assuming GbE/PDR/EC regions may exist or not, check if there
is a valid region defined in the descriptor and set the region access
permissions based on that.

The net effect change is to enable the use of the PDR region on the
sarien platform, which also uses the GbE and EC regions.

This results in the following example changes:

mb/google/sarien (GbE, PDR, EC)
.      DESC BIOS ME GbE PDR EC
-BIOS  r    rw      rw      r
-------------------------------
+BIOS  r    rw      rw  rw  r

mb/google/eve: (no GbE, no PDR, no EC)
.      DESC BIOS ME GbE PDR EC
-BIOS  r    rw      rw      r
-ME    r         rw r
-GbE   r            rw
-EC    r                    rw
-------------------------------
+BIOS  r    rw
+ME    r         rw
+GbE
+EC

BUG=b:134703987

Change-Id: I7aeffc8f8194638c6012340b43aea8f8460d268a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33273
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-07 20:51:27 +00:00
Nico Huber ec017590e5 util/lint: Make usage of IS_ENABLED() an error
As long as we keep the IS_ENABLED() definition in libpayload for
compatibility, we should check that IS_ENABLED() usage doesn't
sneak back in.

Also remove all other IS_ENABLED() checks.

Change-Id: Id30ffa0089cec6c24fc3dbbb10a1be35f63b3d89
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-06-04 13:16:16 +00:00
Nitheesh Sekar 6681f05373 qcs405: util/qualcomm: Add T32 debug scripts
Add T32 scripts that allow debug of any coreboot stage
on qcs405.

Change-Id: I4e792a2806e5ebd3b4075c7bb69c43587920deae
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29951
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-03 13:20:38 +00:00
Damien Zammit 9b5e8c1718 xcompile: Remove --rtlib switch from clang CFLAGS
Fix the following error from clang invoking gcc linker with wrong arg:

i386-elf-gcc: error: unrecognized command line option '--rtlib=libgcc';
did you mean '-static-libgcc'?
clang-4.0: error: linker (via gcc) command failed with exit code 1

Just remove --rtlib switch from CFLAGS relating to clang

Change-Id: Ife7ef6b6b47a04598fc67b40751bc59eed93b4af
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/21354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-05-29 20:33:35 +00:00
Evgeny Zinoviev 3d90d3bfce util/autoport: Add info about rank 1 mirroring
inteltool can't detect whether address mapping is normal or
mirrored, which in turn may be cause RAM initialization to
fail when using spd.bin generated by inteltool.

Mention this in readme as it may help someone.

Change-Id: I8d24e4d9332bdcf484987581dd6941e2bf9c4f87
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-05-29 20:07:10 +00:00
Alan Green 1470c7367b util/xcompile/xcompile: apply -march to clang as well as gcc
For x64 and x86_32 configurations, apply the -march flag to both GCC and
Clang flags.

This solves the problem of Clang-compiled coreboot failing due to Clang
emitting SSE instructions for code that is executed while SSE is not
enabled.

This patch takes functionality targeted for GCC configurations and moves
it down a few lines, modifying CFLAGS instead of GCC_CFLAGS in order
that it applies to both GCC and Clang.

This is an alternate patch to CB:32887.

Signed-off-by: Alan Green <avg@google.com>
Change-Id: I6a6a6136b01a64d46f730ed19ebbeaadaf2183df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-28 20:33:37 +00:00
Jacob Garber 298afb3140 util/romcc: Add extra null pointer check
It is possible that 'lnode->val' is set to 0 on a previous iteration of
the loop, so check that it is non-null here before dereferencing it.

Change-Id: I9827dd5623eaf11240df605a8b50ff9e27a5fce0
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1129149
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-23 09:02:18 +00:00
Jacob Garber 9742ae1d11 util/romcc: Fix memory leak
The 'new_type' function already allocates memory, so it is only
necessary to clone the existing type if this function is not called.

Change-Id: I47065204c5f4b6bab022bd7ccf19838c3ce1f86e
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity Scan CID 1129106
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-23 09:02:07 +00:00
Jacob Garber 4b688ab3fe util/romcc: Add null check for filename
It is possible that 'filename' is still null in this if statement,
so we add an extra check to prevent a null dereference in strcmp.

Change-Id: Iaba95b63a4d552051e0c56445522de7274dfd0b3
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1395330
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-23 09:01:57 +00:00
Jacob Garber b4222a65ad util/romcc: Add extra NULL checks for member
In each of these cases it is possible that 'member' is NULL at the
beginning, which will skip the earlier while loops entirely and cause
a NULL dereference later on. Add extra error checks to prevent this.

Change-Id: Ib5873c0830b71397ef661976d387fc6ce33c5cd1
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1129147, 1129152, 1129153, 1129154
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-23 09:01:42 +00:00
Evgeny Zinoviev 7687617d00 util/autoport: Mention i2c-i801 module in readme.md
SMBus adapter will not appear if i2c-i801 module is not loaded.
Added it to the readme.

Change-Id: I3de0e02f13178d78b8cc02a74a745ad66e929070
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-23 08:59:48 +00:00
Elyes HAOUAS fa40e82270 util/sconfig: Move 'static' at beginning of declaration
When using -Werror=old-style-declaration, gcc reports an error:
"'static' is not at beginning of declaration"

Tested on 945G-M4 board.

Change-Id: I7216a4fab2d5878066c871166e6a481d1f201a9d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-05-22 10:09:33 +00:00
Jacob Garber 9b0d8e7a1f util/romcc: Prevent out-of-bounds read
If 'class > LAST_REGC', then there will be an out-of-bounds read when
accessing 'regcm_bound'. Prevent this by skipping to the next iteration
of the loop. Note that this should not generally happen anyway, since
'result' represents a bitset for the indices of 'regcm_bound', and so
iterations where 'class > LAST_REGC' should already be skipped by the
previous continue statement (since those bits of 'result' should all be
zero).

Found-by: Covericy CID 1129122
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Id5f5adb0a292763251054aeecf2a5b87a11297b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-05-22 10:03:11 +00:00
Jacob Garber ae8301fddb util/romcc: Fix parsing of empty string literal
The corner case of an empty string literal was causing romcc to
segfault. This checks if the literal is empty, and if so allocates a
size one buffer for the terminating null character. A test case for
this is added to ensure it doesn't happen again.

Found-by: Coverity CID 1129099
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I067160a3b9998184f44e4878ef6269f372fe68bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-21 09:28:36 +00:00
Jacob Garber b79d2dee2b util/romcc: Free variable after it is used
Free 'arg_type' after it is used to prevent a memory leak.

Found-by: Coverity Scan CID 1129114
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I5e8661547bb7623463ed23fc45269049ffb8c50e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-21 09:27:57 +00:00
Jacob Garber 40a85f85c6 util/romcc: Use 64 bit integers when shifting
'used_indices' is 64 bits wide, so use a fixed-width type to make
that clear. As such, 'index' can have a value of up to 63, so use a
64 bit integer when doing the shifts to prevent overflow.

Found-by: Coverity Scan CID 1287090
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Ibd089df6be60c8ea46da11e5e83cd58b2e2c54d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32854
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-21 09:27:03 +00:00
Elyes HAOUAS bd96a84300 util: Fix typo on plural form of index
Change-Id: Idc165f8eafacf3130a29b701bc3610c1a67f69d5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
2019-05-20 14:45:35 +00:00
Jett Rink 1eeb94ff4a util/scripts: update references to cross-repo-cherrypick
It appears that the rebase.sh script was renamed to
cross-repo-cherrypick and changed directories. Update comments to
reflect that change.

Change-Id: I863df48378feb48c9b195b1778dcaf1972a4f105
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-20 14:44:08 +00:00
Alex James 7aeeb48390 util/lint/check-style: Don't hardcode clang-format path
Signed-off-by: Alex James <theracermaster@gmail.com>
Change-Id: I688cb60c98370bf74aa8554bab43594ff84c4e24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-15 19:46:39 +00:00
Elyes HAOUAS 65209de411 autoport: Remove unneeded include <arch/io.h>
Change-Id: I7cb4b47e2fd893274303bb20dc7fa895830b4493
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-05-15 17:58:20 +00:00
Christian Walter 9a8c5e7ac0 util/inteltool: Add Kabylake E3-1200 Support
Change-Id: I5c55102d7ce15dbb708e9433500ebd1ed53179ad
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-15 17:21:39 +00:00
Elyes HAOUAS c15e600490 crossgcc: Upgrade acpica to version 20190509
Changes: https://acpica.org/node/170

Change-Id: I6779a20005ffc0d4781bb60de3ba48759ef67d40
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-05-13 09:32:24 +00:00
Jacob Garber a75440739d util/inteltool: Use appropriate channel for printing timings
At least one channel must be present, so print an error if there is
not. However, we cannot always assume it will be the first channel,
so make the appropriate selection when printing the timings.

Found-by: Coverity Scan #1370{584,585,588,589,590-596,600}
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I6b59989242e498474782876302e0850e3e4cf2d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-13 09:24:14 +00:00
Jacob Garber 554e55b0f0 util/kconfig: Use snprintf to avoid buffer overflow
'name' and 'env' are supposed to be file system paths,
but could overflow the buffer if configured incorrectly.
Let's avoid that entirely.

Found-by: Coverity Scan #1362515
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I1aef36819d49ebcbde1c51995dc0961c85e74150
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-13 09:14:42 +00:00
Jacob Garber 4fbd22e38d util/intelvbttool: Add error checking for memory allocation
It is possible that 'malloc_fo_sub' and 'remalloc_fo' can
fail, so add appropriate error checks for those cases.
This incidentally fixes a possible memory leak when
'malloc_fo_sub' succeeds but 'remalloc_fo' does not.

Found-by: Coverity Scan #1396050
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I944b67f5cdcfd7a687e81d8bb01a209c9dc9b0b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-13 09:12:35 +00:00
Jacob Garber 2be617b58b util/intelvbttool: Free file object on error path
Prevents a memory leak.

Found-by: Coverity Scan #1396047
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I4c72a17351d8afbe23302edfeeba74b17608aef2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-13 09:12:27 +00:00
Jacob Garber 9bb0461fbd util/ifdtool: Add find_fd null check
As the previous comment indicated, this null check is
currently superfluous, but adding it in makes Coverity
happy, and future-proofs the code in case someone changes
the internals of 'find_fcba' later and forgets/doesn't know
to update this error check.

Found-by: Coverity Scan #1395066
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I594cd0098f5b36cef5b3efc4c904710d3ba9b815
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-13 09:12:14 +00:00
Nico Huber 772a154d39 nb/intel/snb: Drop NORTHBRIDGE_INTEL_IVYBRIDGE
We keep the support, though. Just now that `libgfxinit` is fixed, we
don't need the distinction anymore. Causally, we also don't need
CPU_INTEL_MODEL_306AX any more.

TEST=Played tint on kontron/ktqm77. Score 606

Change-Id: Id1e33c77f44a66baacba375cbb2aeb71effb7b76
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-05-12 15:03:03 +00:00
Joel Kitching 2eb89c8b14 vboot: include vb2_sha.h when required
Should include vb2_sha.h header when SHA library functions or
constants are required.  This replaces NEED_VB2_SHA_LIBRARY.

BUG=b:124141368, chromium:956474
TEST=make clean && make test-abuild
BRANCH=none

Change-Id: I9f32174dbf3de05fbe5279cb8017888757abf368
Signed-off-by: Joel Kitching <kitching@google.com>
Cq-Depend: chromium:1583820
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-05-09 06:32:44 +00:00
Elyes HAOUAS 1d3b3c3c09 {src,util}: Remove duplicated includes
Change-Id: Id09cec6b2aae58b131b208e96fec539d068ff68a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-05-07 16:15:56 +00:00
Patrick Rudolph ac24d3c311 sconfig: Add SMBIOS type 9 entries
Add the new field 'smbios_slot_desc', which takes 2 to 4 arguments.
The field is valid for PCI devices and only compiled if SMBIOS table
generation is enabled.

smbios_slot_desc arguments:
1. slot type
2. slot lenth
3. slot designation (optional)
4. slot data width (optional)

Example:

    device pci 1c.1 on
        smbios_slot_desc "21" "3" "MINI-PCI-FULL" "8"
    end # PCIe Port #2 Integrated Wireless LAN

Tested on Lenovo T520.

Change-Id: If95aae3c322d3da47637613b9a872ba1f7af9080
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-05-07 16:04:56 +00:00
Felix Singer 0a7543db2d inteltool: Add Sunrise Point-LP Skylake PCH IDs
Sunrise Point-LP is used on Skylake and KabyLake platforms,
but the PCH IDs differ.

This commit adds the PCH IDs for Skylake mobile platforms
and renames the Kabylake macros to distinguish them.

Used Intel documents:
- 332995-001EN (I/O datasheet vol. 1)
- 332996-002EN (I/O datasheet vol. 2)

Change-Id: Id46224fcc44b06c91cbcd6c74a55c95e1de65ec6
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-05-06 10:38:49 +00:00
T Michael Turney 101098c41a sdm845: Combine BB with QC-Sec for ROM boot
TEST=build & run

Change-Id: I222a56f1c9b74856a1e1ff8132bab5e041672c5d
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25207
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-03 21:59:05 +00:00
Furquan Shaikh 4d99b27018 util/sconfig: Throw an error if override tree has no devices
If override tree does not have any device, then the chip info
structure in it cannot be associated with the correct device and ends
up being added as a standalone chip info structure without any device
actually using it. This change prevents this condition by throwing an
error during compilation.

BUG=b:130342895

Change-Id: I7b8bb6b3228030a465976ca32ce8ef63f41365dd
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-04-24 16:23:51 +00:00
Patrick Rudolph e28fa4049d cbfstool: Fix cbfs_file_next_attr
The last attribute was never returned.
Fix size compare to retrieve all attributes.

Manually tested and seen all attributes, including the last one.

Change-Id: I08df073158a0f285f96048c92aa8066fa4f57e6f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-04-23 10:23:56 +00:00
Elyes HAOUAS 5f28639a93 crossgcc: Update acpica to version 20190215
Support for ACPI specification version 6.3:

Add PCC operation region support for the AML interpreter. This adds PCC
operation region support in the AML interpreter and a default handler for
acpiexec. The change also renames the PCC region address space keyword to
PlatformCommChannel.

Support for new predefined methods _NBS, _NCH, _NIC, _NIH, and _NIG.
These methods provide OSPM with health information and device boot
status.

PDTT: Add TriggerOrder to the PCC Identifier structure. The field value
defines if the trigger needs to be invoked by OSPM before or at the end
of kernel crash dump processing/handling operation.

SRAT: Add Generic Affinity Structure subtable. This subtable in the SRAT
is used for describing devices such as heterogeneous processors,
accelerators, GPUs, and IO devices with integrated compute or DMA
engines.

MADT: Add support for statistical profiling in GICC. Statistical
profiling extension (SPE) is an architecture-specific feature for ARM.

MADT: Add online capable flag. If this bit is set, system hardware
supports enabling this processor during OS runtime.

New Error Disconnect Recover Notification value. There are a number of
scenarios where system Firmware in collaboration with hardware may
disconnect one or more devices from the rest of the system for purposes
of error containment. Firmware can use this new notification value to
alert OSPM of such a removal.

PPTT: New additional fields in Processor Structure Flags. These flags
provide more information about processor topology.

NFIT/Disassembler: Change a field name from "Address Range" to "Region
Type".

HMAT updates: make several existing fields to be reserved as well as
rename subtable 0 to "memory proximity domain attributes".

GTDT: Add support for new GTDT Revision 3. This revision adds information
for the EL2 timer.

iASL: Update the HMAT example template for new fields.

iASL: Add support for the new revision of the GTDT (Rev 3).

More changes in this version at https://acpica.org/node/166

Change-Id: I3a825f568423c3a703ad1c13da976af322ed9de2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-04-23 10:03:12 +00:00
Elyes HAOUAS b1f4d52580 crossgcc: Update CMake to version 3.14.2
Release Note :
https://cmake.org/cmake/help/v3.14/release/3.14.html
"The FindFontconfig module added by 3.14.0 accidentally used uppercase
FONTCONFIG_* variable names that do not match our conventions.
3.14.1 revises the module to use Fontconfig_* variable names.
This is incompatible with 3.14.0 but since the module is new in the 3.14
series usage should not yet be widespread"

Change-Id: Ief7f5e8309597093f061789926bd3bd2ed3aec2d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-04-23 10:03:06 +00:00
Elyes HAOUAS 095c2617a3 crossgcc: Upgrade GCC to version 8.3.0
Change-Id: I135fd62619fc33bbc3fd29e93eeafcf695700c9a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-04-23 10:03:01 +00:00
Thejaswani Putta 6f5225c7e0 Klocwork: Fix the Null pointer derefernce found by klocwork
Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com>
Change-Id: I15973ac28e9645826986cf63d2160eedb83024e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32290
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-23 09:56:37 +00:00
Robin Broda 21f9b3ecd7 util/intelmetool: Add Intel Cannon Lake PCH HECI Controller to supported PCI devices
Signed-off-by: Robin Broda <robin@broda.me>
Change-Id: I0f9e83b3bdf35e3e3e119ffcb93b092121a67666
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-04-23 09:55:31 +00:00
Elyes HAOUAS 75380d3a16 src/mb/Kconfig: Fix PCI subsystem IDs
References to MAINBOARD_PCI_SUBSYSTEM_{DEVICE_ID,VENDOR_ID} were removed
in commits

 dbd3132 sb/intel/{i82801g/i/j,bd82x6x}: Make use of generic set_subsystem()
 00bb441 sb/intel/lynxpoint: Remove PCI bridge function

Change-Id: I72bba8406eea4a264e36cc9bcf467cf5cfbed379
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32107
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-19 17:48:15 +00:00
Martin Roth 26c43b7a77 util/docker: Update JRE in coreboot-jenkins-node Dockerfile
openjdk-8-jre-headless is no longer available in the debian image we're
basing the coreboot-sdk off of.  Update it to 'default-jre-headless'.

Change-Id: I60f6ecbaedccc0da61f96e0bce4122406ba4bd91
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-04-17 14:48:32 +00:00
Patrick Georgi e8367c0c5e util/genbuild_h: Prefer iasl from .xcompile over a hard code
build.h provides iasl's version but right now assumes that it's kept in
util/crossgcc/xgcc/bin. Often true, but not always, so use the one found
in .xcompile to query the version as that's the version that is used in
coreboot builds.

Change-Id: Iaeedc22e0e14fa96b4f2a68127f405c7f0c9d5cc
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-04-15 16:35:09 +00:00
Patrick Georgi 237baa1433 util/genbuild_h: Allow operation with older git versions
if git log --no-show-signature is not supported, retry without.

Change-Id: I9ee1f8e887cde5e4d6c5e6958f269c62572cdd53
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32299
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-12 10:19:59 +00:00
Sergey Alirzaev 8f6f3ac199 util/genbuild_h: Do not print PGP verification results in `git log` output
Signed-off-by: Sergey Alirzaev <zl29ah@gmail.com>
Change-Id: I102ecc79bb649a67661c3d22988453dc7741acda
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32129
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-11 12:07:51 +00:00
Jacob Garber 94d61ecab0 util/inteltool: Swap conditions to prevent uninit reads
Both values in each array are only initialized if
`two_channels` is true, so we need to check that first.

Found-by: Coverity Scan #1370{584,585,588,589,590-596,600}
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I592bc6ae00f834f74a61668d7a3919014ec635f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-11 11:27:11 +00:00
Hung-Te Lin 0043a3db20 Documentation: Explain FMAP and FMD
The Flashmap (FMAP) was not clearly documented. The new flashmap.md
explains where to find more details about that and how / why it was used
in coreboot. Also explained what is FMD and how to use it (based on
original README.fmaptool).

BUG=None
TEST=None (only documentation)

Change-Id: Ia389e56c632096d7c905ed221fd4f140dec382e6
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-04-11 11:24:32 +00:00
Julius Werner f028604718 kconfig_lint: Make uses of CONFIG() on an unknown option an error
This check had very few false positives which were all easily resolved,
and it's unlikely that further false positives will become problematic
in the future. On the other hand, it does detect a very severe bug (when
you think you're using a Kconfig but you aren't due to a typo), so since
warnings are currently not very visible, let's turn this into an error
because the pros clearly outweigh the cons for that.

Change-Id: I897b5e13d3242fb77b69f0bd3585baa7476aa726
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32257
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-11 11:21:55 +00:00
Martin Roth d727fb5035 util/docker: Update coreboot-sdk Dockerfile for new debian image
libssl1.0-dev is no longer available:
- Update to libssl-dev
- Add libcrypto++-dev to provide additional crypto libraries not
available in libssl-dev.

Change-Id: Ie10e14ebf7ae849301302008ee6ffeec1f40ccab
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-04-09 14:12:54 +00:00
Martin Roth b0fe89d31b util/docker: work around toolchain autotools issue
The patches added to `make` require that we use automake & aclocal
to rebuild the configuration, but version 1.15 of autotools is
expected. After debian sid updated to autotools 1.16, the tools can't
be located.

We'll just pretend to have version 1.15 with symbolic links. This
doesn't seem to be a good solution but gets the job done.

Change-Id: I9f616b96e728106e7adf321325caa06808e064c2
Signed-off-by: Martin Roth <martinr@coreboot.org>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/28544
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-04 14:56:24 +00:00
Jacob Garber 3eebb16c05 util/arm_boot_tools/mksunxiboot: Correct format strings
%lx is the right format string for printing longs.

Found-by: Coverity Scan, CID 1229686, 1229687
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Ib7ab54dc039bdd60969c79f3c881d69fc68f0d2a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-03 16:57:19 +00:00
Werner Zeh 622a28d22b util/kconfig: Fix missing library issue with ld 2.24 and newer
When invoking 'make menuconfig' with gcc 4.9.2 an error is thrown:

ld: build/util/kconfig/lxdialog/checklist.o: undefined reference
to symbol 'acs_map'

This happens with ld version 2.24 and newer when menuconfig is
executed for the first time after make clean. This does not happen
with ld 2.20 (part of gcc 4.4.7).

It can be fixed with the flag -ltinfo in HOST_LOADLIBES.

Change-Id: I6216bb4d276d4bf98aa4ec06457b809fdcd73235
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-03 05:29:16 +00:00
Balazs Vinarz 28def8b5a0 util/lint: list files with whitespace issues
Change-Id: I8ae13f62c6e2cd87278fefab8de5faf0d1bc0a90
Signed-off-by: Balazs Vinarz <vinibali1@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-04-02 14:58:12 +00:00
Patrick Rudolph 9b545df90b util/spdtool: Add tool to extract SPD from BLOBs
Opens a binary file to extract DDR SPDs using known bits.
At the moment only DDR4 SPDs are supported.
Dumps the found SPDs into the current folder, as either
binary or hex encoded file.

Works with python2 and python3.

Change-Id: I26dd73d43b724ea6891bb5b6e96856c42db8577c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-04-01 08:03:29 +00:00
Elyes HAOUAS 2d22d335dc crossgcc: Upgrade LLVM to 8.0.0
Change-Id: I80efe90e21947aac631d54fd7983319602fc39c2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-25 10:59:41 +00:00
Elyes HAOUAS 2ec5015f02 crossgcc: Update CMake to version 3.14.0
Change-Id: I9fec45429d80500d80cc6b774718ecc91720f3f2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-22 09:36:19 +00:00
Julius Werner e5eb2decd0 lint/kconfig: More checks, more errors
This patch changes a few more Kconfig linter warnings to errors that
currently do not show up in the tree and that seem unlikely to become
false positive in the future. One instance of duplicated code that
essentially checks for the same thing was consolidated.

It also adds a new test for references to boolean Kconfig options that
do not use the CONFIG() wrapper macro. It's a little flaky (e.g. hard to
handle multi-line comments), but it should be helpful the majority of
the time as a warning in a Jenkins comment.

Change-Id: I975ee77d392ed426f76f7671d9b6ef9441656e6a
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-22 09:31:11 +00:00
Angel Pons 22add8ea30 util/autoport: Rewrite readme.md
The last part of the file has not been modified much.

Change-Id: Icc45824d5d1298146f459d75f0a5121dbdd70d41
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30969
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-18 09:22:06 +00:00
Angel Pons 08caa792e6 util/autoport: Trim gfx.did to size
Since the values are hardcoded, we might as well hardcode values that
make sense.

Change-Id: I3ac0e2d74a42c1fe55b1cdc3e2a970ae80cc9f37
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30963
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-18 09:20:05 +00:00
Angel Pons 9b1ae44b28 util/autoport: fix default headers
Change-Id: I1b46d76a86f5db02ebc452d43472b51f0414ad96
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-03-18 09:19:30 +00:00
Julius Werner 0e3f7d4780 Revert "lint/clang-format: set to 96 chars per line"
This reverts commit 626ba097a2.

This change was submitted under the incorrect assumption that there was
agreement on a coding style change. There wasn't, so while the issue is
under discussion we should revert to the previous status quo.

Making clang-format honor the line length is a separate issue from
changing the line length, and can be reuploaded as a separate CL.

Change-Id: I433c82c95a897b3113cace3668cc8ce0f1ab75bf
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-15 23:05:06 +00:00
Thomas Heijligen 725369fd0c inteltool: add 300 and C240 Series PCH
Values from
- Intel doc 337347 rev4
- coreboot soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h

On Coffeelake H (using Cannonlake / Cannonpoint PCH) p2sb is not
accessible. Using a static value instead. 0xfd000000 is a common value
chosen by coreboot and non-coreboot firmware.

Change-Id: Id637f703ab0a99eb0908ecdc3da27ba80db1c6b8
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-15 12:58:28 +00:00
Marshall Dawson 02bd77379b util/amdfwtool: Allow 0-length blobs
A side effect of the change 8e0dca05
"util/amdfwtool: Add generic image copy function"
was to treat a read operation of zero bytes as a failure.  Some
implementations exist that use zero length files as a means of
removing functionality.  This causes amdfwtool to exit with an
error.

Put the zero length capability back in, and generate the requested
table entry with a length field of 0x0.

TEST=Boot google/grunt, inspect PSP directory table
BUG=b:128507639

Change-Id: Ifc9204dbbf6b107f06116362358ab9d22caa71df
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31891
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-15 12:57:57 +00:00
Alexander Couzens 96a437f4aa util/autoport: remove obsolete symbol SANDYBRIDGE_IVYBRIDGE_LVDS
This symbol was removed in
a6be58fece ("nb/intel/sandybridge: Remove the C native graphic init")

Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Change-Id: I87801552e1c37162897949ec0db3904f850f0bfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-03-14 11:25:47 +00:00
Angel Pons 8296fdd979 util/autoport: Separate NB and SB PCIe port IDs
The root port IDs on bd82x6x.go were for both the PCH and the CPU PCIe
root ports. Put the latter on sandybridge.go instead, and add missing
IDs.

Change-Id: I04b5220c460f1930accd64b63c11f512581f2c6c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30962
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-13 09:48:40 +00:00
Julius Werner ef7a326787 lint/kconfig: Update to support new CONFIG() macro
This patch updates the Kconfig linter to support the new CONFIG() macro
in the same manner that IS_ENABLED() was previously supported. It will
be flagged when it is used on non-bool Kconfigs or used with #ifdef, and
it is supported for checking used Kconfigs. Remaining uses of
IS_ENABLED() are flagged with a deprecation warning.

Change-Id: I171ea8bc8e2d22abab7fc4d87ff4cf8aad21084f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31776
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-08 08:33:56 +00:00
Damien Zammit 8e3b842b8b intelmetool: Add more flag descriptions
Obtained by inspecting intel SPSinfo tool output

Change-Id: I69eb0dd86761984b6f0a450b7d8757268b0b248e
Author: roncapat
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31589
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07 17:22:31 +00:00
Damien Zammit f4491e73ca intelmetool: Consolidate all model support from upstream
Some of the older chipsets that are known not to have ME at all
were removed for some reason, add them back in.

Also some newer chipsets/ME models were missing, add them in.

Change-Id: Iaed9a342e478a483113bf81d25042a6041fbc4ba
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-03-07 17:22:22 +00:00
Marshall Dawson 67bbb6db41 util/amdfwtool: Remove fanless SMU options
Complete the removal of the fanless command line options.  The only soc
using them has been converted to use the subprogram option instead.

TEST=Verify amdfw.rom is unchanged before and after the conversion
BUG=b:126691068

Change-Id: I187f17743cc98cc136b0df61caf8e95d17f98d51
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31737
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07 16:03:59 +00:00
Marshall Dawson dbae632fec util/amdfwtool: Split type field for PSP entries
Separate the type field for the PSP directory table to better match the
AMD Platform Security Processor BIOS Architecture Guide (order #55758,
NDA only).  Instead of a 32-bit type, change to an 8-bit value and an
8-bit subprogram field to allow for a more generic application across
family/model products.

This patch also eliminates the "fanless" types, previously added for
stoneyridge, and converts the --smufnfirmware and --smufnfirmware2
arguments to use a subprogram value of 1.

Subsequent patches will change the stoneyridge makefile to use the
new option, and eliminate the fanless arguments.

TEST=Boot google/grunt, confirm no difference in amdfw.rom file.
BUG=b:126691068

Change-Id: If8f33000c31cba21f286f54459de185c21e46268
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31735
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07 16:03:07 +00:00
Marshall Dawson 2794a86b1b util/amdfwtool: Streamline functions with context
Replace variables and function arguments with a context that may be
maintained and passed.  Add macros to clarify the pointer math.  Add
functions to generate tables instead of relying on correct ordering
and math.  Use defined sizes for tables instead of arbitrary additions
to an index.

TEST=Verify no difference in amdfw.rom for google/grunt before and
     after, and verify a grunt build with PSP_COMBO=1 runs.

Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-07 16:02:49 +00:00
Marshall Dawson 8e0dca05fb util/amdfwtool: Add generic image copy function
Consolidate the code that opens, stats, copies, and closes the
individual files into a single function.

TEST=Verify no difference in amdfw.rom for google/grunt before
     and after the patch is applied

Change-Id: I2da0dd79186ccc8c762b58cf3decb9980378a5f7
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-07 16:02:25 +00:00
Marshall Dawson a378c22f77 util/amdfwtool: Combine table header population
Rename psp_fill_head() and call it with the cookie to populate the
header.  The combo header and PSP directory header are similar and
should be calculated the same way.

Change-Id: I7e634542de65576addadbe683596cbe572de3dcd
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31732
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07 16:02:10 +00:00
Marshall Dawson 0e02ce83a1 util/amdfwtool: Remove duplicate PSP2 support
There are effectively two unique sets of arguments for the utility,
causing one of two tables to be constructed.  Both tables are
identical, however, and therefore the only practical difference is
the offset in the Embedded Firmware Structure which holds the pointer
to the table.

This patch is part 2 of 2 to reduce the number of command-line options
to amdfwtool.  Part 1 added the --combo-capable option that helps
put the PSP directory pointer in the correct location.  Part 2
removes the duplicated table, the support code, options, and updates
the usage text.

TEST=Build before/after images for grunt, bettong, apu2, and diff
     hexdumps of the amdfw.rom files.  Built/ran grunt with PSP_COMBO
     defined as 1.
BUG=b:126691068

Change-Id: I542a7f5023137f30fbe00533452d4448117df487
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-07 16:01:40 +00:00
Marshall Dawson 67d868d04b util/amdfwtool: Introduce combo-capable option
There are effectively two unique sets of arguments for the utility,
causing one of two tables to be constructed.  Both tables are
identical, however, and therefore the only practical difference is
the offset in the Embedded Firmware Structure which holds the pointer
to the table.

This patch is part 1 of 2 to reduce the number of command-line options
to amdfwtool.  Create a new option that is used as an indicator for
which Embedded Firmware offset to use.  Part 2 will be added once
makefiles no longer use the duplicated options.

This patch also adds two new options for fanless SMU firmware to be
used instead of the ones that will be removed in part 2.

TEST=Verify no difference in amdfw.rom for google/grunt before
     and after the patch is applied
BUG=b:126691068

Change-Id: I249700c6addad1c0ecb495a406ffe7a022dd920b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-07 16:01:03 +00:00
Marshall Dawson 8a45a4dc3f util/amdfwtool: Clarify call to fletcher32
The fletcher32 algorithm generates a sum over a range of 16-bit
WORDs.  Change the function's interface to be more generic,
accepting a more intuitive size in BYTEs.  Don't require the
caller to understand the nature of the algorithm and convert to
WORDs prior to calling.

TEST=Verify no difference in amdfw.rom for google/grunt before
     and after the patch is applied

Change-Id: Iad70558347cbdb3c51bd598479ee4484219c0869
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31728
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07 16:00:30 +00:00
Marshall Dawson 239286ca44 util/amdfwtool: Clarify calculations with structures
Replace the use of multiples of DWORDs with structures that
describe the Embedded Firmware Table, and PSP directory
headers & entries.

TEST=Verify no difference in amdfw.rom for google/grunt build
     (Family 15h Models 70h-7Fh), amd/bettong (F15h 60h-6Fh),
     and pcengines/apu2 (F16h 30h-3Fh).  PSP_COMBO builds but
     was not verified.

Change-Id: If05952d9282a0fa5a397984eaae671fb33f6134a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-07 16:00:17 +00:00
Marshall Dawson c38c0c91aa util/amdfwtool: Fix iteration of PSP firmwares
Correct an oversight in the utility that attempts to match up eligible
PSP directory table entries with blob names passed on the command
line.  A 1:1 matchup of items shouldn't be assumed, so the i iterator
shouldn't be used to walk both lists.

This change has no effect on google/grunt (Family 15h Models 70h-7Fh),
but eliminates blank entries of all FF's on builds of amd/bettong
(F15h 60h-6Fh) and pcengines/apu2 (F16h 30h-3Fh).  Removal of entries
also affects the checksum accordingly.

TEST=Build before/after images for grunt, bettong, apu2, and diff
     hexdumps of the amdfw.rom files

Change-Id: I13e359d3cc6f5ce408bbf077feec3707ee2b3838
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31726
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-07 15:58:42 +00:00
Philipp Deppenwiese c9b7d1fb57 security/tpm: Fix TCPA log feature
Until now the TCPA log wasn't working correctly.

* Refactor TCPA log code.
* Add TCPA log dump fucntion.
* Make TCPA log available in bootblock.
* Fix TCPA log formatting.
* Add x86 and Cavium memory for early log.

Change-Id: Ic93133531b84318f48940d34bded48cbae739c44
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-03-07 12:47:01 +00:00
Patrick Rudolph 0c590f064e pci_drivers/cpu_drivers: Fix constructed arrays on x86_64
The __pci_driver and __cpu_driver uses variable length arrays which are
constructed by the linker at build-time.

The linker always place the structs at 16-byte boundary, as per
"System V ABI". That's not a problem on x86, as the struct is exactly
16 Bytes in size. On other platforms, like x86_64 it breaks, because the
default data alignment isn't SysV compatible.

Set -malign-data=abi to make x86_64 gcc use the SysV psABI.
Fixes broken __pci_driver and __cpu_driver on x86_64.

Change-Id: I2491d47ed03dcfd8db110dfb181b2c5281449591
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30116
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-06 20:00:38 +00:00
Felix Singer 24b000a160 inteltool: Add multiple device IDs of Intel GPUs
* Intel HD Graphics 510
* Intel HD Graphics 515
* Intel HD Graphics 520
* Intel HD Graphics 530 (2x)
* Intel UHD Graphics 615 (2x)
* Intel UHD Graphics 617
* Intel UHD Graphics 620 (3x)
* Intel UHD Graphics 630 (7x)
* Intel UHD Graphics 640
* Intel Iris Graphics 540
* Intel Iris Graphics 550
* Intel Iris Pro Graphics 580
* Intel Iris Plus Graphics 650
* Intel Iris Plus Graphics 655

Change-Id: I299a5fc082433b0aab4861a24aecbe83b61a404a
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30610
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-06 11:29:51 +00:00
Krystian Hebel 9e3c30283f util/superiotool/ite.c: add support for IT8613E
Based on not publicly available IT8613E Preliminary Specification V0.3.

Change-Id: Iec99d4d998f645dbad9c803d6d5477580b0bccc4
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-03-06 11:28:28 +00:00
Julius Werner d60cc97526 lint/kconfig: Fix check for IS_ENABLED(XXX) where someone forgot CONFIG_
This is a great check, but unfortunately it's currently not effective
because most uses of IS_ENABLED() do not have whitespace in front of
them (they're mostly used as part of an if (IS_ENABLED(...)) condition).
This patch makes the linter a little more generous in what it considers
in scope to avoid these false negatives in the future.

Change-Id: I2296410c73cd6e918465c90db33e782936bec0f9
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31746
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-06 01:15:26 +00:00
Hung-Te Lin 49a4450563 cbfstool: Support new FMD flag "PRESERVE"
When updating firmware, it is very often that we may want to preserve
few sections, for example vital product data (VPD) including serial
number, calibration data and cache. A firmware updater has to hard-code
the section names that need to be preserved and is hard to maintain.

A better approach is to specify that in FMAP area flags (the `area_flag`
field) using FMAP_AREA_PRESERVE. With this patchset, a FMD parser flag
"PRESERVE" is introduced and will be converted to FMAP_AREA_PRESERVE
when generating FMAP data (by fmap_from_fmd.c).

For example, The FMD statement:

  RO_VPD(PRESERVE)@0x0 16k

will generate an FMAP firmware section that:

  area_name = "RO_VPD"
  area_offset = 0
  area_size = 16384
  area_flags = FMAP_AREA_PRESERVE

BUG=chromium:936768
TEST=make; boots on x86 "google/eve" and arm "google/kukui" devices
     Manually added 'PRESERVE' to some FMD files, and verify (by running
     fmap.py) the output coreboot.rom has FMAP_AREA_PRESERVE set

Change-Id: I51e7d31029b98868a1cab0d26bf04a14db01b1c0
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-03-05 20:51:39 +00:00
Patrick Rudolph 44b4ec740d rmodule: Add support for R_X86_64_PLT32
The recent toolchain update also updated binutils, which has a new
relocation type, introduced with commit bd7ab16b
(x86-64: Generate branch with PLT32 relocation).

Add support for R_X86_64_PLT32, which is handled as R_X86_64_PC32.
Add comment explaining the situation.
Fixes build error on x86_64.

Change-Id: I81350d2728c20ac72cc865e7ba92319858352632
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31468
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-05 19:36:52 +00:00
Hung-Te Lin 9497fcb742 cbfstool: Change FMD annotation to flags
The idea of "annotation" for firmware sections was pretty flexible, but
in future we will want multiple attributes applied to same area. For
example, indicate the section must be preserved when updating firmware
so serial number or MAC address can be preserved.

The solution here is to extend annotation so it can take multiple
identifiers (flags) in a row. For example, to declare a 64KB COREBOOT
section as CBFS using annotation:

 COREBOOT(CBFS)@0x0 64k

If there's a new flag "PRESERVE" indicating the section must be
preserved before update, we can declare it following CBFS flag:

 COREBOOT(CBFS PRESERVE)@0x0 64k

The flags are directly parsed in fmd_parser, and stored in an union
flashmap_flags. Output modules can choose to ignore or process the
flags.

Currently the only supported flag is "CBFS" (for backward compatible
with annotation). There will be more new flags in follow up patches.

BUG=chromium:936768
TEST=make; boots on x86 "google/eve" and arm "google/kukui" devices

Change-Id: Ie2d99f570e6faff6ed3a4344d6af7526a4515fae
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31706
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-05 19:31:43 +00:00
Patrick Georgi 2785290989 util/lint: Fix clang-format test and enable it by default
git diff needed to emit diffs without prefix (e.g. a/ and b/) for
clang-format-diff to be able to work.

Also require that the test succeeds, but note that it only runs on
trees whitelisted in $(top)/.clang-format-scope.

Change-Id: I7e9a32eb9281b5cb0b45506a206500fd1d315372
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-03-05 16:13:10 +00:00
Patrick Georgi 626ba097a2 lint/clang-format: set to 96 chars per line
80 chars + 2 tabs was the compromise we got to in the last round of
discussion.

Change-Id: I9293a69d1bea900da36501cde512004d0695ad37
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-05 12:45:47 +00:00
Nico Huber 8a95c6c48d util/inteltool: Add Apollo Lake GPIO groups and names
Apollo Lake has four GPIO communities each with a single group named
after the physical location of the pads (I guess): North West, North,
West and South West.

Also add some logic to be able to tag the default function of a pad
(with an asterisk before its name). This seems easier to review in the
tables, but we could also encode the number of the default explicitly
instead.

Used Intel documents:
- 334817-001 (datasheet vol. 1)
- 334819-001 (datasheet vol. 3)

Change-Id: I5cd687fdc1d2ae81f2e948178bf319897b47f031
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-05 11:56:02 +00:00
Hung-Te Lin 4708612061 fmap: Add FMAP_AREA_PRESERVE
When updating firmware, we may need to preserve some sections like VPD,
calibration data, ... etc. The logic can be hard-coded in updater as a
list of known names, but a better solution is to have that directly
declared inside FMAP area flags.

To do that, the first step is to apply the changes in flash map
(http://crosreview.com/1493767). A new FMAP_AREA_PRESERVE is now
defined and will be set in future with new syntax in FMD parser.

BUG=chromium:936768
TEST=make; boots an x86 image.

Change-Id: Idba5c8d4a4c5d272f22be85d2054c6c0ce020b1b
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-03-04 13:25:01 +00:00
Patrick Rudolph 62b4b44961 rmodule: Don't emit reloc for R_X86_64_PC64
Relocations for PC relative instructions must not emitted.
As PC64 are unlikely with current code, it never was an issue.

Change-Id: Ife472a287ff15b1c04a516e25ff13221441fd122
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/31469
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-03 16:46:30 +00:00
Kyösti Mälkki a37a1a65a7 util/cbmem: Improve utility description
Change-Id: Ieddcf100d8db25f3ae9ac182cd374918e38d4f4c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-03-01 10:00:46 +00:00
Nico Huber 4829af17e3 cpu/intel: Rename socket_mFCPGA478 to socket_m
The name was wrong. mFCPGA478 is actually a pseudonym for mPGA478MN,
the successor of the socket that was meant.

The official name of this socket is mPGA478MT. But "Socket M" is much
easier to distinguish.

Change-Id: I4efeaca69acddfcdc5e957b0b521544314d46eeb
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-02-28 13:47:54 +00:00
Martin Roth 3361120bc8 util/abuild: Set fatal asserts when running scanbuild
Because coreboot's asserts aren't fatal by default, scan-build finds
problems in code that is actually protected by an assert.  This
change fixes that and allows us to add asserts to protect
against other failures.

Change-Id: I9fa605d6309bb40a9cef33b434c9256bf731f457
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/31650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-27 19:33:43 +00:00
Elyes HAOUAS b134368942 ACPI: Fix error on asl_compiler_revision format
dmesg report wrong asl compiler version as this value wasn't
in hexadecimal:
FACP 0x00000000CFB5D6C0 0000F4 (v04 COREv4 COREBOOT 00000000 CORE 01341407)
DSDT 0x00000000CFB5B280 002436 (v02 COREv4 COREBOOT 20190112 INTL 20190215)

This error was introduced on change-Id: I91b54b43c8b

Tested on 945G-M4 board, dmesg now report the right value:
FACP 0x00000000CFB5D6C0 0000F4 (v04 COREv4 COREBOOT 00000000 CORE 20190215)
DSDT 0x00000000CFB5B280 002436 (v02 COREv4 COREBOOT 20190112 INTL 20190215)

Change-Id: I5494bb1e7af17eba0c2da8a0c2eb9e40ffd8d065
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31612
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-26 21:44:01 +00:00
Philipp Deppenwiese 66f9a09916 security/vboot: Add measured boot mode
* Introduce a measured boot mode into vboot.
* Add hook for stage measurements in prog_loader and cbfs.
* Implement and hook-up CRTM in vboot and check for suspend.

Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-25 22:29:16 +00:00
Damien Zammit f0a9128424 intelmetool: Use GPLv2+ where possible
Upstream intelmetool is out of date; I suggest I archive it
instead of trying to merge coreboot's changes into it.

However I would like to preserve the licensing of files in the tool
as GPLv2+ where possible instead of GPLv2-only.

Change-Id: I47b1ff2734f54c65f4214b39244bd868ef44b83c
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/c/31587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-02-25 11:19:37 +00:00
Alex Feinman 2223cbf7de intelvbttool: Add support for reading vbt from sysfs
VBT on Intel(R) systems is available via sysfs as
    /sys/kernel/debug/dri/0/i915_vbt
However the size of this file reads as 0 causing
intelvbttool to fail. This patch implements incremental reads
with realloc for such cases or whenever the file size is not
available (e.g. reading from stdin).
After this patch is applied, intelvbttool can be used as follows:
    sudo intelvbttool -f /sys/kernel/debug/dri/0/i915_vbt -d

Change-Id: I5d17095a5747550b7115a54a7619b7294a846196
Signed-off-by: Alex Feinman <alexfeinman@hotmail.com>
Reviewed-on: https://review.coreboot.org/c/31531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-02-22 11:09:58 +00:00
Elyes HAOUAS 26071aaadf ACPI: Correct asl_compiler_revision value
Change-Id: I91b54b43c8bb5cb17ff86a6d9afa95f265ee49df
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-21 19:07:31 +00:00
Elyes HAOUAS 94ad37619f SMBIOS: Fix bios version
Change-Id: I142f08ed3c2704b8fde6d176f23772f5d6b33e85
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-21 19:07:18 +00:00
Nico Huber 55e3a6ae09 util/lint: Exclude util/inteltool from checkpatch
It's causing too much noise during review of register tables.

Change-Id: Iae6cd4454c5ed84b5fe0ea5f8a244e2a2fa13407
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31367
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-20 12:17:32 +00:00
Elyes HAOUAS c3c9afbdf1 crossgcc: Update MPFR to version 4.0.2
Change-Id: I5569e61c2a3a64cf353afe3195eca82709362305
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31218
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-18 20:20:58 +00:00
Elyes HAOUAS 7340a499fb crossgcc: Update binutils to version 2.32
Change-Id: I943863587dff6db72d12673bc30ea46f4fd4b66f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-15 17:16:11 +00:00
Bora Guvendik 85ea91ae3c util/ifdtools: Make EC region readable to BIOS/CPU
Allow EC region to be readable by BIOS/CPU so that flashrom
can read it.

BUG=b:123199222
TEST=Build coreboot with CONFIG_LOCK_MANAGEMENT_ENGINE set,
run firmware_LockedME test.

Change-Id: I306c74a0893355e57632a22a712b1f4fdaa19306
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-02-14 07:53:16 +00:00
Arthur Heymans 12431d6eef Makefile.inc: Create a default SMMSTORE region
Change-Id: I7b7b75050e0139ea9a0a4f2ad3c0d69a482fb38b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-02-06 18:15:59 +00:00
Arthur Heymans 0b75679cbb Makefile.inc: Optimize generating the default x86 fmap
Put the FMAP FMAP region right above the coreboot CBFS region.
The other regions like RW_MRC_CACHE and CONSOLE often have alignment
requirements so it makes sense to put those on top. This also
simplifies the code the generate the default fmap a little.

Change-Id: I24fa6c89ecf85fb9002c0357f14aa970ee51b1df
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30419
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-06 18:15:27 +00:00
Aaron Durbin eb722282da cbmem: use aligned_memcpy for reading cbmem address information
The coreboot table entry containing the memory entries can have
fields unnaturally aligned in memory. Therefore one needs to perform
an aligned_memcpy() so that it doesn't cause faults on certain
architectures that assume naturally aligned accesses.

BUG=chromium:925961

Change-Id: I28365b204962ac89d65d046076d862b6f9374c06
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Manoj Gupta <manojgupta@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-01 14:53:19 +00:00
Patrick Georgi ec31d1ac76 util/docker: Update container for doc.coreboot.org
Now running 1.8.3, with a fix to the theme so search still works, and
a recommonmark version that properly rewrites links to .md files.

Change-Id: Ice25554c77a398a71782c8d1cb9e205debd80d67
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/31129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-01-29 18:28:47 +00:00
Lijian Zhao 9871b04183 util/ifdtools: Consider EC region access
Version 2 IFD will have flmstr5 as EC region access control, consider it
during descriptor lock/unlock process.

BUG=N/A
TEST=Build coreboot with CONFIG_LOCK_MANAGEMENT_ENGINE set, and check
flmstr5 value by hexdump the SPI image at offset FMBA+0x90.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I970064dcf6114a15f054ab7c44349841deb99dc8
Reviewed-on: https://review.coreboot.org/c/31111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-01-29 12:29:35 +00:00
Lijian Zhao 3e88b18bb6 util/ifdtool: Add lock support for CNL and ICL
Cannonlake and Icelake have same read/write region permission settings
with skylake and kabylake, so add it here as well.

BUG=b:123199222
TEST=Turn on CONFIG_LOCK_MANAGEMENT_ENGINE and build image, check the
setting matches 0x0D for read and 0x04 for write.

Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I71d8b815c7dff7dcbcff2bf77c85ebf80b8df6d2
Reviewed-on: https://review.coreboot.org/c/31104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-01-29 12:29:24 +00:00