Commit Graph

40542 Commits

Author SHA1 Message Date
Felix Held bb4bee8572 soc/amd/cezanne: select soc-specific ACPI functionality
This doesn't select HAVE_ACPI_TABLES, so no ACPI tables will be
generated for now. There's also no globalnvs.asl that corresponds to
nvs.h yet. The added nvs.h has some currently unused fields, but still
having them in the struct aligns it with Picasso and also might reduce
the noise in future ACPI patches a bit. When most of the ACPI code for
Cezanne has landed, we need to do a cleanup though.

Change-Id: I3d658d284fa67e4da43a89d74686445fd5e93b1f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-11 16:18:01 +00:00
Felix Held 2e97897ea3 soc/amd/*/smihandler: use size_t and unsigned int
signed int should only be used when we need negative values and in those
cases the value shouldn't became negative.

Change-Id: Iefac021260ff363c76bf5cd3fe3619ea1dbabdba
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50486
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 16:17:15 +00:00
Felix Held a2db88eb5a soc/amd/*/smihandler: remove replace southbridge references with fch
Change-Id: I96fc8082263800b731f1d4d9ecdc8a99c28bff32
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50485
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 16:17:01 +00:00
Felix Held c3ce09cdac soc/amd/cezanne/chip: set device operations for UART MMIO devices
Change-Id: I5df3a61741f05364e2c20725b0b85164b197dbdc
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50484
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 16:16:47 +00:00
Felix Held b2d8a5c017 soc/amd/cezanne: add empty mp_init_cpus
Change-Id: I845a7e2cfea58ca08cd2a6f0d884dbbbe1a7bdef
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50483
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 16:16:37 +00:00
Felix Held aa77d1364f soc/amd/cezanne/cpu: add basic zen_2_3_init functionality
The MCA MSRs aren't getting cleared and no microcode update gets applied
for now. Both will be added later.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I38ce5d11787ffefdd0183c5540ae2683158cbee8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50482
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 16:16:29 +00:00
Idwer Vollering 68bcc083bd util/msrtool: teach the configure script to use clang
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Change-Id: I5d0cbbb0c415df0d7b899cf5eb1a9a52dd98bef9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-11 14:32:02 +00:00
Elyes HAOUAS ad581984a6 src: Remove unused <cpu/intel/model_206ax/model_206ax.h>
Change-Id: I67862a6a5110e2cab4f77388caa702494e4d71c9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11 10:25:44 +00:00
Elyes HAOUAS 45ce5d8973 src: Remove unused <arch/cpu.h>
Change-Id: I1112aa4635a3cf3ac1c0a0834317983b4e18135a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11 10:25:23 +00:00
Angel Pons d152837d34 soc/intel/broadwell: Remove _ADR from SerialIO ACPI devices
SerialIO is in ACPI mode for google/auron and intel/wtm2, and is
disabled for google/jecht and purism/librem_bdw. Since Broadwell
SerialIO is never used in PCI mode, _ADR can safely be dropped.

Change-Id: I9a99b8209b5c139146012aa4a92f563692b62c5e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-11 10:24:43 +00:00
Elyes HAOUAS 4f880b9ab8 sb/amd/agesa/hudson/acpi/fch.asl: Sync whitespace
Make it look more like the file under amd/pi/hudson.

Change-Id: I5b40dc5b6f54bf68113826e693ca5963fec83d38
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2021-02-11 10:24:03 +00:00
Elyes HAOUAS a03058a22a soc/intel/xeon_sp; Remove unneeded whitespace before tab
Change-Id: I56f0d4aa627155ee318362f626347d7990571dcb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11 10:23:45 +00:00
Elyes HAOUAS f4f2132c64 src/mainboard: Remove unneeded whitespace before tab
Change-Id: I37f12f5cb35ea1a6ad33edb114688ce1619030a4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11 10:23:17 +00:00
Elyes HAOUAS 388aaf734b security/intel/txt/Makefile.inc: Use tab for indent
Change-Id: Ic85a3b6cfb462f335df99e7d6c6c7aa46dc094e7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11 10:23:04 +00:00
Elyes HAOUAS c2dd4c7a6b mb/google/volteer/variants: Remove unneeded whitespace before tab
Change-Id: I4c991e6119f14d949a2e103024132d70674f29a1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11 10:22:34 +00:00
Elyes HAOUAS e2856be098 mb/amd/mandolin/Kconfig: Remove unneeded whitespace before tab
Change-Id: I2b52c32a607386cdc1ca00531eda4dfc0bfaab1e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11 10:22:25 +00:00
Elyes HAOUAS f26b2e5c91 arch/x86/id.S: Remove unneeded whitespace before tab
Change-Id: I053a2a8cff3fda1a1074f74e4d4c174a0cb24d86
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11 10:22:07 +00:00
Elyes HAOUAS 89c05c56c0 src/superio: Fix typo in comment
Change-Id: I2e5cac310af824eb9756b2aa9459239e0b5784da
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11 10:21:54 +00:00
Angel Pons 4dc85f11d1 sb/intel/common/rtc.c: Define __SIMPLE_DEVICE__
Change-Id: Ie11fffdf907227ab315bfd4887aaa5de3602bd24
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-02-11 10:19:31 +00:00
Angel Pons 6f4dc8f7a4 lib/selfboot.c: Fix indentation and drop one newline
Change-Id: Ica4254297f5d05e75f852d7e9a9e7bb833dfcea7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50397
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 10:19:17 +00:00
Elyes HAOUAS 56a676e5d0 cpu/intel/microcode: Fix typo in function parameter
Change-Id: I9b03105a6808a67c2101917e1822729407271627
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-02-11 10:19:04 +00:00
Elyes HAOUAS f843e0a8ef nb/intel/{haswell,sandybridge}/*/mchbar.h: Fix typo in comment
Change-Id: Ie41433ed8fcadec25007c436ec12163d729a2afe
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11 10:18:54 +00:00
Angel Pons b53dfc727e sb/amd/agesa/hudson/amd_pci_int_defs.h: Fix comments
Change-Id: Iff701d8e6d672b3ca97d9d6361ba48736c06c6c1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-02-11 10:18:37 +00:00
Angel Pons 39a223724d sb/amd/agesa/hudson: Drop setting `ACPI_FADT_RESET_REGISTER`
It is already set in `src/arch/x86/acpi.c` function `arch_fill_fadt`.

Change-Id: Ica7e112ca253d1332ed2ea414948c8f1970d0a69
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-02-11 10:18:28 +00:00
Angel Pons 73c73dded6 sb/amd/agesa/hudson/sm.c: Drop unused `BITx` macros
Tested with BUILD_TIMELESS=1, Lenovo G505s remains identical.

Change-Id: I759bdef44f7ca0f35350901998f6820820005b38
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-02-11 10:18:21 +00:00
Angel Pons c64465f212 sb/amd/pi/hudson/pci.c: Remove empty init operation
Change-Id: I5620867b3044936be8ad1bf95255be5a3565bb51
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-02-11 10:17:58 +00:00
Angel Pons c3d88eee64 sb/amd/pi/hudson/imc.c: Remove duplicated comment
Change-Id: Ie2de3948a78352bbb68c9215222b8489cacb91ce
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2021-02-11 10:17:55 +00:00
Kevin Chiu 788eb99448 mb/google/zork: modify ELAN TP i2c IRQ to LEVEL active for dirinboz
configure IRQs as level triggered to prevent TP lost.

BUG=None
BRANCH=zork
TEST=1. emerge-zork coreboot chromeos-bootimage
     2. power on, suspend DUT to check TP is functional

Change-Id: I81ffa889fbdfb01bf3057a8258fb4dd4ad7e88d5
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50420
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 10:17:35 +00:00
Patrick Georgi d510b60f5b Revert "mb/intel/shadowmountain: Add the ASL code"
This reverts commit 2151f7561d.

Reason for revert: It depends on the shadowmountain ramstage patch.

Error on the builder:

    IASL       /cb-build/coreboot.0/default/INTEL_SHADOWMOUNTAIN/dsdt.aml
src/mainboard/intel/shadowmountain/dsdt.asl:4:10: fatal error: baseboard/ec.h: No such file or directory
 #include <baseboard/ec.h>
          ^~~~~~~~~~~~~~~~
compilation terminated.

Change-Id: I9fa5e8cc2ad485bf82bfbda151bc46d26faef7ab
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-11 10:15:41 +00:00
V Sowmya 2151f7561d mb/intel/shadowmountain: Add the ASL code
This patch includes the DSDT ASL code for shadowmountain board.

BUG=b:175808146
TEST= Boot shadowmountain board, dump and verify the DSDT ASL entries.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I511b2d23c424b0565ad1abcc3b41cace1b89936e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49733
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 07:43:16 +00:00
Felix Held a90854d429 soc/amd: fully commonize clear_tvalid
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I90526a566a5fbc19a7368f90421067a6c716614e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50466
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 02:49:34 +00:00
Felix Held 3c4fd70d61 soc/amd/cezanne/smihandler: add missing southbridge_io_trap_handler
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4140fbf93e84a2620ffb88e5c65df17b23135553
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50465
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 02:47:49 +00:00
Felix Held 574b1b9674 soc/amd: include cpu/x86/smm directory in common SMM Makefile
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id6be7aa7f295e61f873bfae1fca42260d3b0db78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50464
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 02:46:41 +00:00
Felix Held a3a66b6e68 soc/amd: move southbridge_smi_handler to common code
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I650498321736eee3d33af51216eda1b650f11744
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50463
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 02:45:48 +00:00
Felix Held bc134812c3 soc/amd: factor out common SMM relocation code
The common code gets moved to soc/amd/common/block/cpu/smm, since it is
related to the CPU cores and soc/amd/common/block/smi is about the SMI/
SCI functionality in the FCH part. Also relocation_handler gets renamed
to smm_relocation_handler to keep it clear what it does, since it got
moved to another compilation unit.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I45224131dfd52247018c5ca19cb37c44062b03eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50462
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 01:44:24 +00:00
Felix Held a6fc2125e7 soc/amd*/smihandler: factor out and rename clear_smi_sci_status
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifd6c3bebee1ccf7e7e7987d8ae3d9fa654019791
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50460
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 00:50:52 +00:00
Felix Held 4f69ab729a soc/amd*/smihandler: factor out and rename clear_all_smi_status
The old name was misleading, since it doesn't disable the generation of
SMIs, but clears the status registers.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iddadbec013091c2e5993a6303e291451c3d1e7ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50459
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 00:50:14 +00:00
Felix Held ee2a365872 soc/amd/cezanne: add empty SMM-handler
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I95908fac3b1e17a16542e5d80001fac3d22d839a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50455
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 00:49:23 +00:00
Felix Held a8d4a718e3 soc/amd/stoneyridge: drop empty sb_enable
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9b6e0bd5c7358e2f18f929d5b098d95acbf59a5c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50437
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-11 00:46:12 +00:00
Felix Held e094b1f137 soc/amd/cezanne/fch: add HAVE_SMI_HANDLER case to fch_init_acpi_ports
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie7bab29ae8d0e28c392210f8dcbaa4441ca61114
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50454
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10 23:25:21 +00:00
Paul Fagerburg 259cccd7e7 mb/google: order matters in mem_parts_used.txt
* Add comments to mem_parts_used.txt to point out that the order of
the entries matters when assigning IDs, so always add a new part
to the end of the file.
* Update existing mem_parts_used.txt to add the same comment.
* No updates to Zork variants, because they use an optional ID, so
the order actually doesn't matter there.

BUG=b:175898902
TEST=create a new variant of dalboz, trembyle, volteer, waddledee,
or waddledoo, and observe that mem_parts_used.txt has the new
verbiage.

Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: Iffbd8e69a89b1b7c810c5d25c7a6148d459d8b02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-02-10 22:15:52 +00:00
Felix Held 237bc2efaa soc/amd/stoneyridge/chip: rewrite enable_dev as switch case statement
This also aligns Stoneyridge with Picasso and Cezanne.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I35bf9915e3502c22e9dd9efa80b00a1ce70f187d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50436
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10 21:50:36 +00:00
Raul E Rangel 72616b3813 soc/amd/cezanne: Add verstage support
Setup the config required to support verstage.
The offsets are the same as picasso.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I82874d649db3c9c370e32841e6a9898efb70082e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-02-10 21:46:54 +00:00
Felix Held a634257f13 soc/amd/common/psp_gen2: print error for uninitialized MSR_PSP_ADDR
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8b6362a9eb2344293dad22357651f646774af789
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50448
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-10 21:11:09 +00:00
Felix Held 583d531bd6 soc/amd/common/block/psp: factor out soc_get_psp_base_address
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib73ac92e69f1be5852a1406ba714acb6a8a04989
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-02-10 21:10:11 +00:00
Elyes HAOUAS 517453a6cc src/ec/quanta/ene_kb3940q/acpi/battery.asl: Convert to ASL 2.0
Change-Id: I7cc47536b0c1e2c903df29402090abfccde82406
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-10 19:18:09 +00:00
Elyes HAOUAS 81d55cf6d6 src/ec/lenovo/h8/acpi/battery.asl: Convert to ASL 2.0
Change-Id: I5de6c7da2440d682378a4ceb89b4bedd689dad60
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-02-10 19:17:34 +00:00
Raul E Rangel 5461662c66 soc/amd/cezanne: Enable SOC_AMD_COMMON_BLOCK_SPI
Required so we pass SPI information down to depthcharge.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4ce819b537333c28d394c925331e3dbf260b7732
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-10 19:01:22 +00:00
Raul E Rangel 466edb51b4 soc/amd/common/blocks/lpc: Remove common SPI registers
Use the SoC versions instead.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia0b8129b165f8a2e6be6706ab2e3f2d39e1025a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-10 19:00:49 +00:00
Raul E Rangel 6ba1fcac34 soc/amd/cezanne: Add SPI registers
These are identical to picasso.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3ef4c51ef6d656b3b035d97a56b1875b40e89210
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-02-10 19:00:34 +00:00