Commit Graph

37888 Commits

Author SHA1 Message Date
Jes Klinke 5c7311a524 mb/google/volteer: clang-format mainboard.c
This CL is entirely generated by running the automatic formatter on this
one file.

BUG=None
TEST=abuild -t GOOGLE_VOLTEER2 -c max -x

Change-Id: Ibdd8cc2222e7af11c11df963b088ca2db07a3214
Signed-off-by: Jes Bodi Klinke <jbk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-04 09:37:42 +00:00
Patrick Rudolph b5f580e03c mb/prodrive/hermes: Set tcc offset to 1
Prevent early throttling when the ambient temperature is high.

Change-Id: Ie6881c9c0942aae3e43509170352271a74244d42
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-04 09:37:31 +00:00
Arthur Heymans b38d6bbe1c soc/intel/xeon_sp/cpx: Align coreboot CAR symbols to FSP-T
The CAR set up by FSP-T is at base 0xfe800000 and has a 0x200000 size.
FSP-M seems to have a very large stack usage so it would overflow
other car symbols located below the coreboot stack such as timestamps
and the pre-ram console, which are now fixed.

TEST: boot with ocp/deltalake.

Change-Id: I886f9391ad79fcfa0724109393e3781a08d954b4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46895
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-04 08:27:31 +00:00
Furquan Shaikh 3cea0594df mb/google/volteer: Log EC events in case of S0ix resume
This change adds the callback
`elog_gsmi_cb_mainboard_log_wake_source()` to volteer to enable
logging of EC events in case of S0ix resume.

BUG=b:172272078
BRANCH=volteer
TEST=Verified that EC events are logged correctly for S0ix resume:

11 | 2020-11-02 14:11:05 | S0ix Enter
12 | 2020-11-02 14:11:08 | S0ix Exit
13 | 2020-11-02 14:11:08 | Wake Source | Power Button | 0
14 | 2020-11-02 14:11:08 | EC Event | Power Button
15 | 2020-11-02 14:11:17 | S0ix Enter
16 | 2020-11-02 14:11:21 | S0ix Exit
17 | 2020-11-02 14:11:21 | Wake Source | GPE # | 112
18 | 2020-11-02 14:11:21 | EC Event | Lid Open

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I7aa9dc2470da3226925927f2a0cc39fdd426e3b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47142
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-03 23:58:55 +00:00
Furquan Shaikh 7c36dc12df soc/intel/{tgl,jsl}: Enable logging of wake sources for S0ix
This change adds elog.c to smm-y for Tiger lake and Jasper Lake
platforms to enable the logging of wake sources in eventlog for S0ix.

BUG=b:172272078,b:169731044
BRANCH=volteer
TEST=Verified on volteer that wake sources are correctly logged for
S0ix:
8 | 2020-11-02 13:54:27 | S0ix Enter
9 | 2020-11-02 13:54:33 | S0ix Exit
10 | 2020-11-02 13:54:33 | Wake Source | RTC Alarm | 0
11 | 2020-11-02 13:54:49 | S0ix Enter
12 | 2020-11-02 13:54:54 | S0ix Exit
13 | 2020-11-02 13:54:54 | Wake Source | Power Button | 0
14 | 2020-11-02 13:55:04 | S0ix Enter
15 | 2020-11-02 13:55:10 | S0ix Exit
16 | 2020-11-02 13:55:10 | Wake Source | GPE # | 112

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ie1c40dfba6c82ca45a21d35c5a2725e4d30855d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47141
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-03 23:58:45 +00:00
Angel Pons 1b85692fc4 sb/intel/lynxpoint/sata.c: Don't enable Bus Master
Bus Master is not required and reference code does not set it.

Tested on Asrock B85M Pro4, still boots from SATA SSD with TianoCore.

Change-Id: I7a84da5b712e6fa569ad9f412c440afeb6a8cc5d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-03 23:40:48 +00:00
Angel Pons 4c2389e28c soc/intel/broadwell: Relocate PCH ACPI files
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.

Change-Id: I7f87085c70149d02c544e2d43e1bdb58c7502d6d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46754
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-03 19:12:35 +00:00
Angel Pons 96a480d507 cpu/intel/haswell: Move smmrelocate.c MSR definitions to header
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change.

Change-Id: Ia271718477ea227b9ba7e836b0abe02264778129
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46733
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-03 19:12:01 +00:00
Angel Pons 55a890fe3a Revert "broadwell: Switch to using common ACPI _SWS code"
This reverts commit 81a4c85acf.

Reason for revert: Blocks merging Haswell and Broadwell together.

Tested on out-of-tree Acer Aspire E5-573, still boots.

Change-Id: I29c4ad9174ab84c7e9111daa0491ede9e1d639b4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46734
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-03 19:09:51 +00:00
Angel Pons 3d8b6e25bb sb/intel/bd82x6x/sata.c: Replace bad uses of `find_resource`
The `find_resource` function will never return null (will die instead).
Given that the existing code gracefully handles null pointers already,
it is reasonable to replace these function calls with `probe_resource`.

Change-Id: Ibd8f5ebd561cbde22ce5cd83de8270177bad1344
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-03 19:09:34 +00:00
Matt DeVillier bf355e7159 mb/purism/librem_cnl: Adjust in preparation for new variants
- Move the SoC select to board config (vs baseboard config)
- Qualify the VGA PCI ID and CBFS size values based on board selection
- Move devicetree to variant dir and add Kconfig entry
- Use a separate board_info.txt for the baseboard and each variant

Change-Id: I4764f2c1243ea49bd08e0735865cc3cb7a66441f
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-03 19:03:54 +00:00
Matt DeVillier 54e0fd21b1 mb/purism/librem_whl: rename to librem_cnl
Since Whiskeylake SoC code is actually a subset of soc/intel/cannonlake,
rename the baseboard so that boards using other 'cannonlake family' SoCs
(e.g., Cometlake) can be added with minimal confusion.

Rename the mainboard dir and baseboard name, and adjust any references
to them.

Change-Id: I2af7977f1622070eb8bf8449bc8306f9d75b9851
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-03 19:01:40 +00:00
Marc Jones 2c707160a9 soc/intel/xeon_sp/acpi: Fix uncore dsdt for multiple cpus
Fix the asl to use CONFIG_MAX_CPUS  to create entries for
multiple cpu uncores. Don't add the RTxx resource entries multiple
times. The function is called for each CPUs.

Change-Id: Ia4eb9716ae4bd72fb4eb98649105be629623cbef
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47060
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-03 17:20:23 +00:00
Marc Jones 995a7e25a1 soc/intel/xeon_sp; Use soc specific stack-port function
Separate the get_stack_for_port into soc specific functions. This
removes a #if in common code.

Change-Id: Ib38a7d66947ded9b56193a9163e5128b2523e99c
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2020-11-03 17:18:52 +00:00
Angel Pons 3dea2b63ee soc/intel/common/block/systemagent/memmap.c: Align cached region
When asked to place cbmem_top(), FSP does not seem to care about
alignment. It can return an address that is MTRR poison, which will
exhaust all variable MTRRs when trying to set up caching for CBMEM.
This will make memory-mapped flash and TSEG caching fail as well.

Safeguard against this by aligning the region to cache to half of its
size, and move it upwards to compensate. It is assumed that caching
memory above the provided bootloader TOLUM address is inconsequential.

TEST=Boot Purism Librem Mini WHL, observe no MTRR exhaustion error
     messages in console. The boot process also feels more fluid.

Change-Id: Ic64fd6d3d9e8ab4c78d68b910a476f9c4eb2d353
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-03 17:04:03 +00:00
Patrick Rudolph 88991caf00 include/list.h: Add support for GCC9+
When getting the address of a structure's member that is not on
offset 0, GCC9+ assumes that the address can never be NULL. However
the code relied on the fact that it can be NULL by letting the pointer
intentionally overflow.

Manually calculate the address using uintptr_t. This allows to
gracefully terminate the list_for_each MACRO instead of crashing at the
end of the list.

Tested on qemu-system-arm:
coreboot no longer crashed in the devicetree parser and is able to boot
Linux 5.5.

Change-Id: I0d569b59a23d1269f8575fcbbe92a5a6816aa1f7
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-03 09:11:21 +00:00
Angel Pons e8e0418d98 configs: Add a weird config for Portwell M107
This is not meant for actual use, but to build-test several options.
Please do not try to use it on real hardware. Or maybe do try.

The purpose of this config is to build-test the individual options, not
their combination. So, for instance, if it would be hard to keep options
x, y and z build together in the future, this config shouldn't block a
change but should instead be adapted, e.g. split into multiple chunks.

Change-Id: Ife40d055e4c9b295c54cfc6a27af06e9358f7761
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45974
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-03 06:48:16 +00:00
Angel Pons 2d7d0d0e66 configs/config.asrock_b85m_pro4...: Select X86_SMM_LOADER_VERSION2
This allows build-testing the code while it isn't used anywhere.

Change-Id: I754c661fbad0bc5fbddfab9747607e664ad1e2b6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44174
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-03 06:47:59 +00:00
Angel Pons 67888e26e6 configs/config.asrock_b85m_pro4...: Clarify its purpose
The purpose of this config is to build-test the individual options, not
their combination. So, for instance, if it would be hard to keep options
x, y and z build together in the future, this config shouldn't block a
change but should instead be adapted, e.g. split into multiple chunks.

Change-Id: Ibd8f6513fae6cd02fcf889d2510dc7e0a97ce40c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47068
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-03 06:47:51 +00:00
Subrata Banik 21974ab86d soc/intel: Select SOC_INTEL_COMMON_BLOCK_CAR as per alphabetical order
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I7adf430e6ce5f78f68a0c73af841fbdc62bb5dc9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47057
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-03 04:07:02 +00:00
Patrick Rudolph 6c46b6f84c cpu/x86/mp_init: Add support for x86_64
Fix compilation on x86_64.

Tested on HP Z220:
* Still boots on x86_32.

Change-Id: Id7190d24172803e40acaf1495ce20f3ea38016b0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44675
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-03 02:09:12 +00:00
Kangheui Won 1464b0edea soc/amd/picasso: pass verstage timestamps to x86
Initialize timestamp table with data from psp_verstage on bootblock.

PSP keeps its own timestamp and pass it in transfer_buffer. However PSP
timestamp and TSC may be out of sync so we can't just merge two tables
without modification.

info->timestamp contains PSP's clock value (in us) when x86 processor
released and base_timestamp contains TSC value when bootblock is
started. The time between x86 release and bootblock entry should be very
short so we can think those two happened at the same time and use them
for sync.

In some cases there will be underflow in timestamp entries but cbmem
utility can handle wrap-over in entries. Few timestamp values including
1st timestamp can be very large but we can still get the time spent on
boot without any problem.

BUG=b:159220781, b:167148121, b:171422583
BRANCH=zork
TEST=boot to kernel, run 'cbmem -t' and check verstage timestamps are
included in the result.

Change-Id: I5e89bb54f478153fb40ba51b5ab61fa20af3b99a
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45059
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 22:17:37 +00:00
Kangheui Won 9f7df5c18a soc/amd/picasso: add monotonic_timer
On Zork(picasso) platform we run verstage on the PSP. It has its own
timer, but the frequency is not matched with TSC.

To ease the work to merge timestamps from the PSP and TSC, add a layer
around tsc to have microsecond granularity for timestamp table. PSP
already records timestamp in microseconds.

BUG=b:159220781
BRANCH=zork
TEST=build, flash and boot, check timestamps are correct

Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Ifced4a84071be8da547e252167ec21cd42f20ccc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46058
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 22:17:29 +00:00
Jacob Garber 5e6c30bc42 coreinfo: Add support for link time optimization
This introduces a Kconfig option for compiling coreinfo with LTO.
This option can be used independently of LTO in libpayload, though will
benefit most if that is enabled as well. If both are enabled, the
final size of coreinfo.elf is reduced from 95 KiB to 92 KiB.

Tested in QEMU and on Thinkpad T500.

Change-Id: I6feacdb911b52b946869bff369e03dcf72897c9f
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38293
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 22:10:23 +00:00
Jacob Garber 04540f1549 libpayload: Add support for link time optimization
Link time optimization is a technique for whole-program optimization.
Instead of doing code generation during compilation, the compiler saves
its intermediate representation to the object files. During the final
linking step, it will then merge all the object files together and
perform optimizations on the entire program. This can often reduce the
final binary size, but also may increase the total compilation time.

This patch introduces a Kconfig option for enabling link time
optimization in libpayload. Since libpayload does no linking of its own,
its LTO archive files will contain only IR and no generated code.
Downstream projects will need to use LTO-aware tools when manipulating
the archives (eg. gcc-ar and gcc-nm), but otherwise do not need to use
LTO themselves -- the compiler will recognize which files are LTO and
which are not, so enabling this option should mostly be "drop in".

For example, when building coreinfo.elf using tinycurses libpayload:

		binary size	compilation time
default		114 KiB		11.49s
LTO		95 KiB		10.36s

In this case the total compilation time was actually shorter -- despite
the final linking step taking longer, this was offset by the shorter
compilation times for each individual file (since there is no code gen
until the very end).

Change-Id: I048f2ff6298ed0d891098942e1e8b29d35487b91
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38291
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 22:05:02 +00:00
Vinod Polimera b524d2bb1f sc7180: Fix prefill requirement and correct the fetch start check
With Innolux panel timings, the fetch_start has evaluated to be more than
v_total which is invalid. Add a check to accommodate the extra h_total addition
in fetch_start calculation. Secondly, made the prefill line requirement
same as Kernel driver.

Change-Id: If7624c0b28421759fdf47dd92f23214a78058199
Signed-off-by: Vinod Polimera <vpolimer@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-11-02 22:04:33 +00:00
mkurumel a9d225b3e8 sc7180: Add Modem region in memlayout to avoid modem cleanup in Secboot reboot.
two different modem regions wifi and lte to be handled in QC_SEC and modem

Change-Id: Ib4592ca66d3d0db4c4768be4cd27422fe9f786b8
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-11-02 21:58:52 +00:00
Angel Pons 82689d2ac8 mb/google/volteer/var/volteer2: Merge `common_soc_config`
SCONFIG complains because of the duplicate devicetree entry.

Change-Id: Ibdd60efdbcee5bda7c570d4b98f29cc8ede584cb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jes Klinke <jbk@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-11-02 17:31:55 +00:00
Duncan Laurie f78ade3e31 mb/google/volteer/variants: Describe USB ports in devicetree
Add the USB ports to the devicetree for describing them in ACPI,
including defining the port relationships and defining the reset
GPIO for the bluetooth device.

BUG=b:151731851
TEST=tested on volteer, all other boards were checked against the
latest available schematic.

Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: Ia1e5b71e7750a478ff79372c48616bbf5c21b79c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-02 16:53:01 +00:00
Subrata Banik 4ed9f9a507 soc/intel: Use of common reset code block
This patch removes all redundant reset code block from each SoC
and make use of common reset code block(fsp_reset.c) based on
SOC_INTEL_COMMON_FSP_RESET.

Respective SoC Kconfig to choose correct FSP global reset type as
per FSP integration guide.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I71531f4cf7a40efa9ec55c48c2cb4fb6ea90531f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-02 10:43:53 +00:00
Subrata Banik 2b2ade9638 soc/intel/common: Create common Intel FSP reset code block
Create SOC_INTEL_COMMON_FSP_RESET Kconfig to have IA common code block
to handle platform reset request raised by FSP. The FSP will use the
FSP EAS v2.0 section 12.2.2 (OEM Status Code) to indicate that a reset
is required.

Make FSP_STATUS_GLOBAL_RESET depends on SOC_INTEL_COMMON_FSP_RESET.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I934b41affed7bb146f53ff6a4654fdbc6626101b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-02 10:43:40 +00:00
Angel Pons 22d4397913 azalia: Use `HDA_GCTL_CRST` macro as unset-mask
The `HDA_GCTL_CRST` corresponds to bit zero, so this is equivalent.

Change-Id: I5f4455aa1255f8954ac8b5f1ea5cf8f0874f77a4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46728
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 10:41:35 +00:00
Angel Pons 554713ee0a azalia: Treat all negative return values as errors
Instead of checking whether the return value equals -1, just check if it
is negative. Some Azalia implementations already do it, but most do not.

Change-Id: I43ce72a01c07eff62d645db28c09584b386532ff
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46727
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 10:41:15 +00:00
Angel Pons 90cdf705aa sb/intel/lynxpoint: Align with Broadwell
Tested with BUILD_TIMELESS=1, Google Wolf does not change.

Change-Id: Iaed0ba1c14e3f6fac1c9d71f1d4334efc4f0f4e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46726
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 10:40:50 +00:00
Angel Pons 4fe4661d4e sb/intel/lynxpoint/lpc.c: Simplify PM init sequence
This sequence used to be an array of reg-and-or triplets, but can be
simplified. The resulting sequence is closer to what Broadwell does.

Change-Id: I21e79cbc1e995707b87c40187ddf03b872d02058
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46725
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 10:39:48 +00:00
Usha P 412679d892 util/ifdtool: Enable CPU read of the ME region
We are implementing a mechanism in coreboot to update CSME firmware,
this requires coreboot to be able to read CSME region. Exposing the
CSME data is not an issue since the data stored by CSE is all encrypted.

This patch provides a command line option "-r" which will enable read
access to CSME region when locking.

Without this change, locking SPI regions using ifdtool will block BIOS
access to read/access CSME. This will cause failure since BIOS can't
read basic information such as CSME version.

TEST=Flashrom returns success while erasing the SI_ME region.
After rebooting the DUT, DUT boots into OS without any issues on
Drawlat EVT.

Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I1d9a8e17fba19b717453476fbcb7bcf95b278abe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-02 10:39:27 +00:00
Duncan Laurie 5abf040265 mb/google/volteer: Add DB_USB3_NO_C option for DB_USB field
Define option value 6 for DB_USB where there is a Type-A port but
no Type-C port on the daughterboard.

BUG=b:151731851
TEST=build volteer boards

Change-Id: I489d24316556dedfecd821e502f1461010b1400f
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-11-02 10:36:59 +00:00
Felix Singer 3d9fa08bf1 device: Rework bus master option
As an intermediate step for CB:45150, add an additional Kconfig option
which is used to configure bus mastering for any devices and use
PCI_ALLOW_BUS_MASTER to allow coreboot setting the bus mastering bit in
general.

Change-Id: I33b37a79022007a16e97350db61575b63fa8256b
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45149
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 06:30:32 +00:00
Sunway d7511f8054 mb/google/kukui: Enable MT8183_DRAM_EMCP for kakadu
The Kakadu project will be using eMCP board design.

BUG=b:171841122
TEST=Boots on chromebook Kakadu successfully.

Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com>
Change-Id: I44668ce630758e49fbf2c6028f56c01f83ff08f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46871
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 06:29:18 +00:00
Duncan Laurie 78a0160bed soc/intel/denverton_ns: Add PCH_DEVFN_PMC for finding PMC device
In order to support the common PMC functions this device needs to
be able to be located with the common lookup macro.

BUG=b:160996445
TEST=build intel/harcuvar board

Change-Id: If04a82582c07c15bf841d0baa84e31561d211502
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46642
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 06:28:50 +00:00
Eric Lai aec4d81e65 mb/google/octopus/var/fleex: Add variant.c into smm stage
variant_smi_sleep is called in smm stage so we need to add
variant.c into smm stage. Otherwise it will call the dummy one.

BUG=b:168075958
BRANCH=octopus
TEST=build image passed.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I41df1a30b119ab3e04f9ae01955b6044f137527f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46847
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 06:28:38 +00:00
Jes Klinke fbb568347d mb/google/volteer: New variant for Volteer reworked with Dauntless
For development of the firmware to run on the Dauntless TPM, a number of
Volteer2 devices are being reworked to replace the H1 chip with probe
wires to connect to an external Dauntless development board.

Some modification to the AP firmware is required, not least because the
Dauntless chip is connected via I2C bus, instead of SPI.  Most of the
Dauntless developers will not otherwise have a Chrome OS chroot.
Because of the above, I think it makes sense to have a new variant, for
the reworked devices, which I intend to create with this CL.

BUG=b:169526865
TEST=abuild -t GOOGLE_VOLTEER2_TI50 -c max -x

Change-Id: Ibdcd6c2ce3941c229518f21f0e479890b5d76dd1
Signed-off-by: Jes Bodi Klinke <jbk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-02 06:28:00 +00:00
Patrick Rudolph 49da0cfe46 cpu/intel/car/non-evict/cache_as_ram.S: Add support for longmode
* Use heap for linker script calculated constant to fix relocation
  symbols in mixed assembly code.

Tested on HPZ220:
* Still boots in x86_32.

Tested on Lenovo T410:
* Doesn't need the MMX register fix in long mode.

Change-Id: I3e72a0bebf728fb678308006ea3a3aeb92910a84
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-11-02 06:26:43 +00:00
Tim Chen f9bc5baee5 mb/google/dedede/var/metaknight: Generate SPD ID for supported parts
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory part being added is:
MT53E512M32D2NP-046 WT:E
K4U6E3S4AA-MGCR
H9HCNNNBKMMLXR-NEE
MT53E1G32D2NP-046 WT:A
K4UBE3D4AA-MGCR

BUG=b:169813211
TEST=Build the metaknight board.

Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Change-Id: I0d0d22f4790f66b5265803e4dcf01234a16b1993
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-11-02 06:26:08 +00:00
Ronak Kanabar 8586b4020d soc/intel/jasperlake: Set the GpioOverride configuration
Set "GpioOverride" config to override FSP gpio
configuration. FSP will not configure any GPIOs
and rely on GPIO settings programmed before moved to FSP.

BUG=b:150666058
TEST=Build and boot JSLRVP

Cq-Depend: TBD
Change-Id: Ia4036cf0be3a6036d70920743958dc327a652077
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45901
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 06:25:53 +00:00
David Wu 77a23d10bf mb/google/volteer/var/terrador: Enable SaGv support
Enable SaGv for terrador.

BUG=b:171763116
BRANCH=volteer
TEST="emerge-volteer coreboot" compiles successfully.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ie00166a619424a67f70f870e55822ae2cc6d023d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-11-02 06:25:31 +00:00
Nico Huber bc2c12c728 libpayload/x86: Try to discover invariant TSC rate
We can skip the PIT-based TSC calibration if we can derive the invariant
TSC rate from CPUID/MSR data. This is necessary if the PIT is disabled,
which is the default, for instance, on Coffee Lake CPUs.

This implementation should cover all Intel Core i processors at least.
For older processors, we fall back to the PIT calibration.

Change-Id: Ic6607ee2a8b41c2be9dc1bb4f1e23e652bb33889
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-11-02 06:24:33 +00:00
Nico Huber 5c9d82bd73 libpayload/x86: Add enumeration of Intel family 6 models
The list is incomplete and only contains what we need in the follow-up
commit. It can be extended at will.

Change-Id: Ibf8ddaf510eb513ee74af3e78da46b04802a91b9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-11-02 06:24:10 +00:00
Tim Crawford d0d445564c mb/system76/lemp9: Enable battery charging thresholds
Change-Id: I5131cf350d5b8c2a45f8d8245c0df26742c0d732
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45533
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 06:23:50 +00:00
Tim Crawford a4e75ab0cd ec/system76/ec: Add battery charging thresholds
System76 EC firmware supports setting charging thresholds for a single
battery.

Change-Id: I3d656291c096f320d469274677e9fe6c74819d25
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45532
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-02 06:23:36 +00:00