Commit graph

9 commits

Author SHA1 Message Date
Arthur Heymans
b29078e401 mb/*/*: Remove rtc nvram configurable baud rate
There have been discussions about removing this since it does not seem
to be used much and only creates troubles for boards without defaults,
not to mention that it was configurable on many boards that do not
even feature uart.

It is still possible to configure the baudrate through the Kconfig
option.

Change-Id: I71698d9b188eeac73670b18b757dff5fcea0df41
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-23 11:06:25 +00:00
Nicola Corna
8f39f1f097 mb/sapphire/pureplatinumh61: Disable the SuperIO serial
There is no serial port on this platform.
In addition, put the LPC serial IRQ into quiet mode.

Change-Id: I4b2c93c51e8ddb8b510f0d7f7e3072befeba5d95
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/21226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-06 04:47:59 +00:00
Patrick Rudolph
b9959e279c cpu/intel/model_206ax: Use tsc monotonic timer
Switch from lapic to tsc.

Allows timestamps to be used in coreboot, as there's a reference
clock available to calculate correct time units.

Clean Kconfig, remove duplicated lapic code and include tsc dir for
LGA1155 boards.

Tested on Lenovo T430.

Change-Id: I849ca2b3908116d9d22907039cd6e4464444b1d1
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-09 16:27:19 +02:00
Nico Huber
d4ebeaf475 device/Kconfig: Put gfx init methods into a choice
Provide all gfx init methods as a Kconfig `choice`. This elimates the
option to select native gfx init along with running a Video BIOS. It's
been only theoretically useful in one corner case: Hybrid graphics
where only one controller is supported by native gfx init. Though I
suppose in that case it's fair to assume that one would use SeaBIOS to
run the VBIOS.

For the case that we want the payload to initialize graphics or no
pre-boot graphics at all, the new symbol NO_GFX_INIT was added to the
choice. If multiple options are available, the default is chosen as
follows:

  * NO_GFX_INIT, if we add a Video BIOS and the payload is SeaBIOS,
  * VGA_ROM_RUN, if we add a Video BIOS and the payload is not SeaBIOS,
  * NATIVE_VGA_INIT, if we don't add a Video BIOS.

As a side effect, libgfxinit is now an independent choice.

Change-Id: I06bc65ecf3724f299f59888a97219fdbd3d2d08b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-08 14:58:15 +02:00
Nico Huber
5f9fe7232a mb/sapphire/pureplatinumh61: Sanitize Kconfig
Remove overrides that set platform defaults or insane values.

Change-Id: I11d1c7155bf1c7f9298f60638a6c2f3b128f3fe8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/19354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicola Corna <nicola@corna.info>
2017-05-11 16:47:20 +02:00
Patrick Rudolph
0a4a4f7ae4 mb/*/mainboard.c: Get rid of SPI AFC register
The AFC—Additional Flash Control Register is set by
southbridge code.

Remove redundant calls and get rid of it in autoport.

Change-Id: I627082e09dd055e3b3c4dd8e0b90965a9fcb4342
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19493
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-05-01 14:02:19 +02:00
Nico Huber
b7f28700f4 mb/sapphire/pureplatinumh61: Update GMA config
This board was added while the latest libgfxinit changes were in review.
Update to make it compile again and sanitize the port list.

Change-Id: I81b96e225945a8f8e47b64cefea91eb2747675ca
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/19353
Tested-by: build bot (Jenkins)
Reviewed-by: Nicola Corna <nicola@corna.info>
2017-04-24 19:15:12 +02:00
Nicola Corna
5ad939679f mainboard/sapphire/pureplatinumh61: Enable EuP and PME
With EuP and PME enabled the USB power turns off during S5.

Change-Id: I8b9fd7bb308f544401f90f8aa5ffaec61251b2b3
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/19073
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2017-04-13 21:38:16 +02:00
Nicola Corna
1bea5b7df2 mainboard: Add Sapphire Pure Platinum H61
This board has a socketed SOIC-8 4 MB flash chip. All the flash
regions are unlocked by default but unfortunately flashrom
doesn't work with the original firmware and the stock UEFI flash
tool refuses to flash the coreboot image (different image ID).
For now, the external programmer seems to be the only option for
the first coreboot flashing.

Tested and working:
 * Debian GNU/Linux Stretch (with Linux kernel 4.9, SeaBIOS)
 * Microsoft Windows 7 installer with VGA blob (SeaBIOS)
 * Internal GPU, both with VGA blob and libgfxinit (VGA and DVI)
 * External GPU
 * RAM (tested 8 + 8 GB)
 * S3
 * USB, both the 2.0 and 3.0 ports
 * Sata
 * Thermal management
 * Sound
 * LAN
 * Bluetooth
 * VT-x and VT-d
 * me_cleaner

Not working:
 * Microsoft Windows 7 installer with libgfxinit

Untested:
 * Backside Mini PCI-E port
 * DisplayPort and HDMI ports

Issues:
 * The USB is always powered, even is S3 and S5 (like in the
    original firmware).
 * Internal flashing with flashrom doesn't work after resuming
    from S3.
 * The raminit is unreliable, as the RAM training sometimes fails
    and sometimes succeeds, with the same couple of RAMs. Once
    a MRC cache has been created, the raminit works fine.
 * If an external card is inserted and the option
    ONBOARD_VGA_IS_PRIMARY is not enabled, the internal GPU
    disappears completely from the PCI bus.

Change-Id: I76aca2cfc4708c1728ae03ee4f6bc59d976c28a0
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/18564
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2017-03-27 19:54:41 +02:00