Any board that uses the AST driver will have support for native graphics
init. So, select the option in the driver instead of every board.
Change-Id: I2bf42c168d1ffdda11857854889b74953abd7e40
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Updates to current master.
This includes:
- A fix for textmode scaling on G45
- Refactor things to rely less on inline proving
- Increased width of modeline fields to 32 bits
Change-Id: Iab2915b747f6e4fa4e78eb28fea29bb3a9b3b687
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/30311
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add mechanism to configure GPE wake event which in turn can be used as ACPI
Power Resources for Wake
BRANCH=octopus
BUG=b:117953118
TEST=Ensure that the wake GPE event is added to ACPI Power Resource for
Wake.
Change-Id: Iacc12b8636aaac98a8689a211cbe1dcfe306f342
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/30106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add an entry to the soc_clock table for a 216MHz clock so that
the I2C controller clock is calculated correctly when the I2C
bus is used in coreboot.
This was tested by measuring the I2C clock speed on H1 I2C bus
on a sarien board in coreboot and ensuring it is ~400KHz.
Change-Id: I6c3cacdad318a5ce41bc41e3ac81385c2d4f396c
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use a raw fmap region SMMSTORE for the SMMSTORE mechanism, while
keeping the initial option to use a cbfsfile.
TESTED on Asus P5QC, (although it looks like the tianocore patches
using it might need some love as they can't seem to save properly).
Change-Id: I8c2b9b3a0ed16b2d37e6a97e33c671fb54df8de0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The Linux kernel can use the ACPI _PLD group information to
determine peer ports. Currently to define the group information
the devicetree must provide a complete _PLD structure. This
change pulls the group information into a separate structure that
can be defined in devicetree. This makes it easier to set for
USB devices in devicetree that do not need a full custom PLD.
This was tested on a sarien board with the USB devices defined
by verifying that the USB 2/3 ports are correctly identified
with their peer in sysfs.
Change-Id: Ifd4cadf0f6c901eb3832ad4e1395904f99c2f5a0
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The TB has to be inverted to actually protected the correct region.
Tested on elgon using I67eb4ee8e0ad297a8d1984d55102146688c291fc.
Change-Id: I715791b8ae5d1db1ef587321ae5c9daa10eb7dbc
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Backlight control of internal panels likely won't work as configuration
for that seems absent in coreboot. Also, libgfxinit doesn't support any
MIPI/DSI connections, yet, and neither Gemini Lake.
TEST=Booted work-in-progress port kontron/mal10 with VGA text and
linear framebuffer modes. DP display came up.
Change-Id: I7b111f1cdac4d18f2fc3089f57aebf3ad1739e5d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/29903
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for updating microcodes on FSP 1.0 platforms
before memory is initialized. This is a requirement to
fill other FIT entries except for microcode updates.
Change-Id: Ie31acaf0fc41c51b9edf65b981d43d7732661770
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29819
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Huang Jin <huang.jin@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Missing hob 7.3 FSP_NON_VOLATILE_STORAGE_HOB is reported always.
This hob is only generated by FSP during non-S3 and MRC data is changed.
Now display missing FSP_NON_VOLATILE_STORAGE_HOB only when this hob is
required.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: Ice8220149c2e44bb2da010d5a7d8bc4dbeca11e0
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang Jin <huang.jin@intel.com>
It's not implemented for Skylake, all combinations that try to enable it
either result in Kconfig or linker errors.
Move `config SKIP_FSP_CAR` into drivers/intel/fsp1_1 where it's
effective.
TEST=Built Intel/Kunimitsu (FSP1.1) and Intel/KBLRVP8 (FSP2.0) default
configs with and without this patch: binaries stay the same.
Change-Id: Iae0a2d2c7fd7a71ed24118564e6080c4789cda28
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/29533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Initially, I wanted to move only the Kconfig DISPLAY_MTRRS into the
"Debug" menu. It turned out, though, that the code looks rather generic.
No need to hide it in soc/intel/.
To not bloat src/Kconfig up any further, start a new `Kconfig.debug`
hierarchy just for debug options.
If somebody wants to review the code if it's 100% generic, we could
even get rid of HAVE_DISPLAY_MTRRS.
Change-Id: Ibd0a64121bd6e4ab5d7fd835f3ac25d3f5011f24
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29684
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
soc/car_setup.S is included when SKIP_FSP_CAR is enabled,
but no chipset/SoC have car_setup.S available.
Remove include and post_code() call always solving build errors.
BUG=NA
TEST=NA
Change-Id: Iebae2940eb10c9ca9054437be4740c79137bcc61
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang Jin <huang.jin@intel.com>
CONFIG_FSP_USES_UPD is not used by FSP 1.1.
Remove this config from this file.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: If922b6cb2d39b10f6657b4d80e54b226d1386c76
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Huang Jin <huang.jin@intel.com>
Returned status code FspTempRamInit() is not displayed when error occurs.
Move the printk() call before the check for status.
BUG=NA
TEST=Portwell PQ7-M107
Change-Id: Id87e5c765d09f4ab199db9eba07a949b031a709a
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29695
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Huang Jin <huang.jin@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add ability to define a reset gpio in acpi for a USB device.
BUG=b:119275094
Change-Id: Ife3ea43a1eadf2548aa52b8fbd792e691d7cc7f2
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/29615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rajat Jain <rajatja@google.com>
The dependencies of CONSOLE_SERIAL and DRIVERS_UART were somehow
backwards. Fix that. Now, CONSOLE_SERIAL depends on DRIVERS_UART,
because it's using its interface. The individual UART drivers
select DRIVERS_UART, because they implement the interface and
depend on the common UART code.
Some guards had to be fixed (using CONSOLE_SERIAL now instead of
DRIVERS_UART). Some other guards that were only about compilation
of units were removed. We want to build test as much as possible,
right?
Change-Id: I0ea73a8909f07202b23c88db93df74cf9dc8abf9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
It defaults to y to avoid having to select it per mainboard. But that
makes a mess because it results in linker conflicts unless other UART
drivers disable it explicitly.
We try to be smarter about the default value for now. The real solu-
tion would be to hardcode it per mainboard. But who knows which boards
actually have it?
Change-Id: I7e755fe0e4f6d1c31ef2854603a5510c3cdc4967
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29571
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a helper function specific to ramstage to add the boot count
information into event log at ramstage.
BUG=b:117884485
BRANCH=None
TEST=Add an event log from romstage, boot to ChromeOS
Change-Id: Ic79f1a702548d8a2cd5c13175a9b2d718527953f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/29542
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Group event log state information together to manage them better during
different stages of coreboot.
BUG=b:117884485
BRANCH=None
TEST=Add an event log from romstage, boot to ChromeOS
Change-Id: I62792c0f5063c89ad11b512f1777c7ab8a2c13e5
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/29541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Now postcar is a standalone stage, add
it as target to all TPM bus drivers.
This is a required for a measured boot.
Change-Id: I758185daf3941a29883c2256b900360e112275e1
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/29546
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In case the function pointer isn't set return an error.
Change-Id: I9de300f651ac93889dafa7377c876bf5ae2c50cc
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/29531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
port is allocated in ACPI, without checking for value.
Don't use port value when zero.
BUG=N/A
TEST=Portwell PQ-M107
Change-Id: Ia44281b82d003b29bffbf985b774ddd661b65c4e
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/29331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Make use of the common CF9 reset in SOC_INTEL_COMMON_RESET. Also
implement board_reset() as a "full reset" (aka. cold reset) as that
is what was used here for hard_reset().
Drop soc_reset_prepare() thereby, as it was only used for APL. Also,
move the global-reset logic.
We leave some comments to remind us that a system_reset() should
be enough, where a full_reset() is called now (to retain current
behaviour) and looks suspicious.
Note, as no global_reset() is implemented for Denverton-NS, we halt
there now instead of issuing a non-global reset. This seems safer;
a non-global reset might result in a reset loop.
Change-Id: I5e7025c3c9ea6ded18e72037412b60a1df31bd53
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change replaces use of post codes 0x34 and 0x36 in fsp drivers to
instead use POST_MEM_PREINIT_PREP_{START,END} to make it easy to
search from where these post codes are generated during boot flow.
Additionally, it adds POST_MEM_PREINIT_PREP_END to fsp2_0 memory_init
to make it consistent with fsp1_1 memory init.
Change-Id: I307ada1679f212c424e9f7ad2c9d254e24f41fd3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
CPU_MICROCODE_CBFS_LEN and CPU_MICROCODE_CBFS_LOC configs pass the CPU
microcode length and base address in CBFS to FSPT binary as init parameters.
Add new config FSP_T_XIP in Kconfig, which is selected by platform config.
If FSP_T_XIP is selected, then relocate FSPT binary while adding it in CBFS
so that it can be executed in place.
BUG= None
TEST= Build for both CFL RVP11 & RVP8 and verified for successfull CAR setup.
Change-Id: Ic46e0bb9ee13c38ff322979119c4813653c61029
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/28985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
A shortcoming of this driver is that if multiple devices with the same PCI ID
are present and don't have an eeprom, they would all get the same macadress set.
The r8168 driver deals with such cases so it should be easy to implement if
needed.
Change-Id: I5c32df00e25453c350a45e7f1ee6834b89c4289f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
With https://github.com/IntelFsp/FSP/pull/4 merged, this allows using
Intel's FSP repo (that we mirror) to build a complete BIOS ifd region
with a simple coreboot build, automatically drawing in headers and
binaries.
This commit covers Apollolake, Coffeelake, Skylake, and Kabylake.
Skylake is using Kabylake's FSP since its own is FSP 1.1 and Kabylake's
also supports Skylake.
Another candidate (given 3rdparty/fsp's content) is Denverton NS, but
it requires changes to coreboot's FSP bindings to become compatible.
Cannonlake, Whiskeylake require an FSP release.
Change-Id: I8d838ca6555348ce877f54e95907e9fdf6b9f2e7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28593
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Its spreading copies got out of sync. And as it is not a standard header
but used in commonlib code, it belongs into commonlib. While we are at
it, always include it via GCC's `-include` switch.
Some Windows and BSD quirk handling went into the util copies. We always
guard from redefinitions now to prevent further issues.
Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It exposes an interface that is as generic as possible, so payloads
and/or kernels can use it for their data.
Change-Id: I9553922f9dfa60b9d4b3576973ad4b84d3fe2fb5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/25182
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds support in generic device driver to add properties to
DSD table. This driver can be used by all generic devices that do not
need any special handling other than simply adding device properties
to be used by OS.
BUG=b:112888584
Change-Id: I0ca6614f1ef322397618676bbf6da898bef18990
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28796
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The W25Q128J is a QSPI flash chip, without ~HOLD and ~WP.
Add the device id to make coreboot boot from it.
Change-Id: I623fdf7d7e30eb28259bec6294785ad873f1f503
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/28861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
As per internal discussion, there's no "ChromiumOS Authors" that's
meaningful outside the Chromium OS project, so change everything to the
contemporary "Google LLC."
While at it, also ensure consistency in the LLC variants (exactly one
trailing period).
"Google Inc" does not need to be touched, so leave them alone.
Change-Id: Ia0780e31cdab879d2aaef62a2f0403e3db0a4ac8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
Extend the generic flash interface to probe for write protected regions.
Add Winbond custom code to return flash protection.
Tested on Cavium EVB CN81xx using W25Q128.
Change-Id: I933a8abdc28174ec32acf323c102d606b58c1ea5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25082
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make XBCM `Serialized` (obvious), and check for the callee clearing the
request bit (we checked only the status for 0 which we potentially wrote
ourselves).
Change-Id: Ic92d525eda8d0a159fa5ddaacf230658d71c1578
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The device tree now supports 'hidden' and the status can be found in
`struct device.hidden`. A new acpi_device_status() will return the
expected setting of STA from a `struct device`.
BUG=b:72200466
BRANCH=eve
TEST=Builds and boots properly on device eve
Change-Id: I6dc62aff63cc3cb950739398a4dcac21836c9766
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/28567
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CBLV is not kept up to date by Linux' i915. We should fix that too,
but it will likely take some years until we can always expect it to
work.
For now read the register values directly. To accomodate that we
are not the only one writing those, revise XBQC() to search for
the closest value in BRIG (instead of a lower equal one) and round
more accurately for better matches.
Change-Id: I4e2d8fa34e75463d4cf7242af3e2c67577cfa2a5
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The SiFive UART on the HiFive Unleashed uses the tlclk as input clock
which runs at coreclk / 2.
The input frequency is configured in the board code depending on the
current stage. (bootblock + romstage run at 33.33Mhz, ramstage at 1Ghz)
Change-Id: Iaf66723dba3d308f809fde5b05dfc3e43f43bd42
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/27440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Add a __noreturn macro that wraps __attribute__((noreturn)) and replace
current users with the macro.
Change-Id: Iddd0728cf79678c3d1c1f7e7946c27375a644a7d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/28505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
VPD reference: https://chromium.googlesource.com/chromiumos/platform/vpd/+/master/README.md
Copy ChromeOS VPD driver to add support for VPD without CROMEOS.
Possible use case:
* Storing calibration data
* Storing MAC address
* Storing serial
* Storing boot options
+ Now it's possible to define the VPD space by choosing
one of the following enums: VPD_ANY, VPD_RW, VPD_RO.
+ CHROMEOS selects now VPD as part of it.
+ VPD is implemented as driver.
Change-Id: Id9263bd39bf25d024e93daa57053fefcb1adc53a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25046
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
FSP 2.1 implementation is adding features on top of fsp2_0.
One such feature is a shared stack implementation that requires
coreboot to allocate stack for fspm and then fsp uses the same
stack as coreboot. This implementation adds support for shared
stack feature.
Change-Id: I6581111dbaddfa403eca14100577ccc8a05c4ec7
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/28358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add CMOS option that allows to use both integrated and discrete GPU.
Tested on ThinkPad W530.
Change-Id: I8842fef0fa1235eb91abf6b7e655ed4d8598adc7
Signed-off-by: Evgeny Zinoviev <me@ch1p.com>
Reviewed-on: https://review.coreboot.org/28393
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We should always update BCLP, no matter if the driver is ready yet to
process the request. This way it will hold the current value when the
driver initializes.
Change-Id: I4b091d744f95da39abe542966f0a8589a187573b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The _BCM function requires a percentage value. While the
brightness in mailbox3 requires a value in uint8_t. Meaning 255 = 100%.
Previous implementation stored the percentage brightness value resulting
in limiting the brightness to ~40% of it's maximum power.
Only affects brightness control using mailbox3.
Fixes: 6838aaebf9 ("drvs/intel/gma/acpi: Add methods to use MBOX3")
Change-Id: I290b5f5b2a8ee406e39e86d3e0de9997798d890d
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/28345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Bayhub eMMC controller default runs SD base 50MHz at the first power on.
After boot into OS, mmc kernel driver will config controller to HS200/208MHz
and send MMC CMD21 (tuning block).
But Bayhub PCR register 0x3E4[22] (eMMC MODE select) is not clear
after system warm reset.
So eMMC will still run 208Mhz but there is no block tuning cmd in depthcharge.
It will cause two Sandisk eMMC (SDINBDA4-64G-V/SDINBDA4-32G-V) to fail to
load kernel and trap in 0x5B error (No bootable kernel found on disk).
BUG=b:111964336
BRANCH=master
TEST=emerge-grunt coreboot
Change-Id: Ic080682e67323577c7f0ba4ed08f8adafca620cc
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/28353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This change makes WIFI_SAR_CBFS user selectable option so that it can
be enabled/disabled from menuconfig along with the SAR filepath.
BUG=b:112425861
Change-Id: Idf6feaefe68e7ebf6786c2c36e92a054fba4483c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This reverts commit c5ee35ff86.
Reason for revert: breaks boards, uncertain if it _really_ works.
Change-Id: I9ba2ba877b9a391306f89295c0c1d0e2d011c5ea
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28338
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jean Lucas <jean@4ray.co>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This open-codes flash_cmd, but until the API is fixed for real, it uses
xfer's existing scatter-gather ability to write command and data in one
go.
BUG=chromium:446201
TEST=emerge-coral coreboot succeeds
Change-Id: Ic81b7c9f7e0f2647e59b81d61abd68d36051e578
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
For debug reasons, sometimes you not only want to log an event, but also
some extra information that would help debugging. Create an extended event
reporting event type with a dword complement, and define extended events
for failing to enter S3 due to pending wake event (one for pm1 and one for
gpe0).
BUG=b:111100312
TEST=Add a fake pending wake event, build and boot grunt, see the event in
eventlog.txt.
Change-Id: I3e8df0953db09197d6d8145b0fc1e583379deaa5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
* Fix ACPI resume path compilation for TPM ramstage
driver
* Move enabling of the TPM prior activation and remove
reboot return status from TPM enable.
More information can be found via the TCG
specification v1.2
Tested=Elgon
Change-Id: Ided110e0c1889b302e29acac6d8d2341f97eb10b
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/28085
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Callers should have a default ready and get noticed by the return
value of get_option(). No need to scare log readers at this location.
Change-Id: Ied373d8a02afdc8d1017c9f41d9004e3797dfbb3
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/28215
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The help text is already very clear but some users (first and
foremost the author of this patch ;) are still selecting
USBDEBUG_DONGLE_BEAGLEBONE when using a BeagleBone Black and
waste hours on analyzing the debug output of EHCI debug driver.
Change-Id: Ibf002db7d81ed44878f3ce0324170e4b99e780a5
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/28184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Under some conditions, cr50_i2c_read() can return without actually reading
the TPM, which will leave access uninitialized. Set an initial value for
access, and if TPM fails to respond in time check if at least TPM was read.
This way avoids printing an uninitialized value.
BUG=b:112253891
TEST=Build and boot grunt.
Change-Id: I5ec7a99396db32971dc8485b77158d735ab1d788
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Unfortunately stmicro.c does not distinguish the 1.8V version from
the 3.3V versions (yet) although they have distinct RDIDs.
I have at least ordered the ID macros accordingly and used a proper name
in this patch.
Change-Id: Id4fd8d46dcc9e51c1ae5504a32c2f8c5cfd863a1
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/27861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This change gets rid of unused wrdd.asl in intel wifi driver. This
file became redundant when all boards moved to using SSDT for wifi
device.
Change-Id: I8b5b3816d77c90e75052c58a3120ab62185873a7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27963
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SLB9665 are not initialized correctly. It looks like SLB9665 and SLB9660
return the same DEV ID. Initialize these devices according to TPM Kconfig
selections.
Tested on apu2 with following change:
https://review.coreboot.org/#/c/coreboot/+/28000/
Change-Id: Ic20b9a65ef6a4ee392a9352f7c9bf01b2496f482
Signed-off-by: Kamil Wcislo <kamil.wcislo@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/21983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Careena EVT SanDisk EMMC sku has high fail rate of 0x5B reboot failure.
It'll need to increase 1.8V EMMC CLK/CMD, Data driving strength for
this issue.
CLK[6:4]
CMD,DATA[3:1]
original register value: 0x6B
enhanced: 0x7F
BUG=b:111964336
BRANCH=master
TEST=emerge-grunt coreboot
Change-Id: I3db38ff12c566c258895c6643008a0472ca528bb
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/27816
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In procedure spi_flash_cmd_erase(), parameter "len" is not validated and
could lead to the return of an invalid (non-initialized) value. Validate
the parameter early on.
BUG=b:112253891
TEST=Build and boot grunt.
Change-Id: I0b5129a15c9e0ea45f4dba4ab0729196cb64699b
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Use bitfields to pack the struct more tightly.
Change-Id: If1e7a5a3a9504327f987403ec0a7b79b2383792a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27815
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add Mailbox 3 driver
* Request brightness change through Mailbox 3
* Return Ones on error or if unsupported
* Mark existing code as legacy
(still required if no GMA driver is running)
* Call legacy code if Mailbox 3 is unsupported, on error or
if gma driver isn't running
Tested on Lenovo T430:
* Brightness control still works
* Brightness is the same on S3 resume
Change-Id: I51554c819148336b204d28972cbf775a10c3fb8a
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/27711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nathaniel Roach <nroach44@gmail.com>
Reviewed-by: Nicola Corna <nicola@corna.info>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* Make tcpa_log_init static and move init code into
the tcpa_log_add_table_entry routine.
* Add more checks for log initialization.
* Fix minor issues
Change-Id: I215d79eed7ad17c6ab87f0c4b14a282e519ef07d
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/27769
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These two da7219_aad properties are optional:
- dlg,micbias-pulse-lvl : Mic bias higher voltage pulse level (mV).
[<2800>, <2900>]
- dlg,micbias-pulse-time : Mic bias higher voltage pulse duration (ms)
When the Mic Bias Higher Voltage feature is not required, firmware should
just not provide the dlg,micbias-pulse-lvl and dlg,micbias-pulse-time
properties.
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
BUG=b:111700809
TEST=On grunt:
No "Invalid micbias pulse level" in dmesg
Change-Id: Ie99a8962e78c68b3f6927d0de34168f265d4efa9
Reviewed-on: https://review.coreboot.org/27613
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Akshu Agrawal <akshu.agrawal@amd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Logic: If vboot is not used and the tpm is not initialized in the
romstage makes use of the ramstage driver to initialize the TPM
globally without having setup calls in lower SoC level implementations.
* Add TPM driver in ramstage chip init which calls the tpm_setup
function.
* Purge all occurrences of TPM init code and headers.
* Only compile TIS drivers into ramstage except for vboot usage.
* Remove Google Urara/Rotor TPM support because of missing i2c driver
in ramstage.
Change-Id: I7536c9734732aeaa85ccc7916c12eecb9ca26b2e
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/24905
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Devices using NORTHBRIDGE_INTEL_NEHALEM have an ironlake IGD which does not
support eDP, therefore default to LVDS.
Change-Id: I669c7793a6f78d72899df21b74b9314ef39a29af
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27512
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Move vboot/tpm specific implementation to vboot.
* Only call functions if CONFIG_FSP2_0_USES_TPM_MRC_HASH is set.
* Preparation for software hash function support, no logic changed.
Change-Id: I41a458186c7981adaf3fea8974adec2ca8668f14
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/24904
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To comply with all relevant bodies throughout the world, SAR settings
take into account the lowest common denominator Tx power settings. This
setup may lead to non-optimal performance when the user location is in a
country that may allow higher power setting. The purpose of Wireless Geo
Delta Settings (WGDS) is to provide offset settings for FCC, Europe,
Japan and Rest of the world. These offsets would be added (by Intel wifi
driver) to the base SAR Tx Power as defined in WRDS and EWRD
BUG=b:65155728
BRANCH=none
TEST=WGDS ACPI table gets created as expected.
Change-Id: I4f602e3f95ff3545db6cc6e428beb9a36abd9296
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix a linking problem with VBOOT and USE_OPTION_TABLE enabled.
Make use of cbfs_locate_file_in_region() and always search the
cmos_layout.bin in the 'COREBOOT' region.
With this change applied there's no need to include the vboot_locator
in SMM any more, we can't break NVRAM with different CMOS layouts,
and we keep VBOOT and non VBOOT behaviour the same.
Only include cmos_layout.bin and cmos.default in RO region.
Add notes explaining the decisions.
Tested on Intel Sandybridge, builds and boots with vboot enabled.
Change-Id: I10ae94d7936581bbb5ea49384122062bd4934ea5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Type of vbt_len should be size_t, change to fix compiler error
Change-Id: I22798fa0edb98fcb9acc1b2dd52f34a61bc511e9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Put the PCIe clock pins in power-saving mode for the BayHub eMMC bridge to
save power. This requires use of an additional register (Misc control
register 2) and another bit in the existing 'protect' register. The naming
of bit 0 of that register is incorrect, based on the latest datasheet
(14 June 2018) so fix that too.
BUG=b:73726008
BRANCH=none
TEST=boot without this patch:
iotools mem_read32 0xfed80e00
0x0046ffff
With this patch:
$ iotools mem_read32 0xfed80e00
0x00463fff
Also see that the PCIe clock stops when eMMC is idle and can be started by
starting disk activity.
Change-Id: I5ad1467b2e2e151215d2dfd2ce48cd4a451fe480
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/26515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
i2c/alps driver implementation is an exact copy of the i2c/hid driver
with only the addition of ALPS0001_HID. This can be supported by the
i2c/hid driver using the hid field in devicetree which is what glkrvp
mainboard does. So, this change removes the i2c/alps driver which is
anyways unused.
Change-Id: I60761c384f3d800532b2b346272da7be28b77acd
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This change fixes the issue reported by Coverity CID 1393576 to ensure
that config is checked for NULL before it is actually used.
Change-Id: I5f0cd2bf2437fc640f4cf8d8203a971daf1f8d17
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Enrico Granata <egranata@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Commit 77034fa [intel/common: compress VBT] compressed vbt.bin in
CBFS, but only changed the loader in soc/intel/common, forgetting
the separate one used by FSP 1.1.
As the soc/intel/common loader has now been rolled into the one in
drivers/intel/gma, replace the VBT loader used by FSP 1.1 with the GMA one.
Also, remove 2 now-unused header files.
Test: build/boot google/chell, observe display initialized prior
to OS load, no FSP warning in cbmem console due to invalid VBT signature.
Change-Id: Iba882ee4d9e83dcd88bdf7dd2f5591f66005a3fe
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This adds a new driver for the SX9310 proximity detector device.
The purpose of this is to enable the device's calibration information
to be stored in firmware, and then transferred over to the kernel
via ACPI.
This device has more than 10 individual configuration parameters,
so they would not fit in the generic driver's properties table.
Change-Id: Id8c434eec9fe2da731e142442503a12e88db2236
Signed-off-by: Enrico Granata <egranata@chromium.org>
Reviewed-on: https://review.coreboot.org/27173
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Is unused in the tree.
Change-Id: I8a5308b6c7773d791d47832e620558394f1d727e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22132
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Shuffle words and drop the _DATA_FILE suffix.
Change-Id: I0b0d50ea729e5580c0bc7b43f250ff387ce59cfc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This change checks to ensure that config is not NULL before it is
accessed for the first time.
Reported by: Coverity CID #1393312
Change-Id: Ic248c79783da9c2bfdf3b7f737e5963feff7558c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Why would that be a user visible option? Drop the prompt and the
`default n` and select it automatically when needed. I hope I
caught all its users.
TEST=Confirmed that systems with ELOG_GSMI or DEBUG_SMI compile
and link.
Change-Id: I44aeec530cc333f4ed4c8cfe67c7b5c9d8fb0049
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Clean it up and add all flash chip drivers to postcar stage thereby.
There seem to be SPI controllers that don't need the individual
flash chip drivers. For those postcar support was added in b6b1b23
(console/flashconsole: Enable support for postcar). However for
SPI controllers that need the individual drivers (i.e. those with
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y), linking of the postcar
stage was broken.
For all other stages, the set of compilation units stays the same.
Change-Id: Ib8bdb824bfcf2d31ac696e39f797c4355b765756
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26871
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Let the linker take care of it.
Change-Id: I67d2636ceb042f833c1b44888b98135d728940e0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This change adds PCI ID for Intel TP2 Wi-Fi and adds that to
pci_device_ids in Intel wifi driver.
Change-Id: I51abf615fca6001d564e7cd672cc16f3a0fb8dd6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When the i210 MACPHY is operated in the SERDES Backplane mode (which
depends on the programmed firmware image), its PCI-ID will be 0x1537.
This does however not change the programming interface for the MAC
address.
Therefore add this new PCI-ID to the driver so that the MAC address can
be programmed in this operation mode as well.
Change-Id: I608535202c49e40690381c2b2ab26322d62cfb37
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/26683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
As far as I can see this Kconfig option was used wrong ever since it
was added. According to the commit message of 107f72e (Re-declare
CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR), it was only necessary
to prevent overlapping with CAR.
Let's handle the potential overlap in C macros instead and get rid
of that option. Currently, it was only used by most FSP1.0 boards,
and only because the `fsp1_0/Kconfig` set it to CBFS_SIZE (WTF?).
Change-Id: I4d0096f14a9d343c2e646e48175fe2127198a822
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It doesn't make sense to log post codes from a previous (failed) boot
if we are resuming from S3, since the previous boot has to have been
successful in order to enter S3 in the first place.
While we are at it, use a helper function to combine conditionals and
improve readability.
BUG=none
TEST=boot, suspend & resume grunt
Change-Id: I4f3bb8526a0c8c0ea1efd924628b33c147543b88
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/26528
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Previously, we were unconditionally adding a TYPE_BOOT message to the ELOG
on every boot (even S3 resume) if CONFIG_ELOG_BOOT_COUNT was disabled.
Now that boot_count_read() returns 0 for the !CONFIG_ELOG_BOOT_COUNT
case, the code becomes a bit simpler.
BUG=b:79865267
TEST=firmware_EventLog
Change-Id: I803fa4c3e03b6cc94751cf0ce34b78021ae2124e
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/26527
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a support for generating USB port descriptors for ACPI based
on their definition by the board in devicetree.cb. This will
generate a _UPC and _PLD for each port, using a generic _PLD by
default. The _PLD can also be customized for more accurate
descriptions if necessary.
This sample devictree.cb shows a USB 2.0 type-A port behind a root
hub connected to an xHCI controller:
device pci 14.0 on
chip drivers/usb/acpi
register "desc" = ""Root Hub""
register "type" = "UPC_TYPE_HUB"
device usb 0.0 on
chip drivers/usb/acpi
register "desc" = ""USB 2.0 Type-A""
register "type" = "UPC_TYPE_A"
device usb 2.0 on end
end
end
end
end
It will generate the following ACPI code in the SSDT:
Scope (\_SB.PCI0.XHCI.RHUB.HS01)
{
Name (_DDN, "USB 2.0 Type-A")
Name (_UPC, Package (0x04)
{
0xFF,
0x00,
Zero,
Zero
})
Name (_PLD, ToPLD (
PLD_Revision = 0x2,
PLD_IgnoreColor = 0x1,
PLD_Red = 0x0,
PLD_Green = 0x0,
PLD_Blue = 0x0,
PLD_Width = 0x0,
PLD_Height = 0x0,
PLD_UserVisible = 0x1,
PLD_Dock = 0x0,
PLD_Lid = 0x0,
PLD_Panel = "UNKNOWN",
PLD_VerticalPosition = "CENTER",
PLD_HorizontalPosition = "CENTER",
PLD_Shape = "RECTANGLE",
PLD_GroupOrientation = 0x0,
PLD_GroupToken = 0x0,
PLD_GroupPosition = 0x0,
PLD_Bay = 0x0,
PLD_Ejectable = 0x0,
PLD_EjectRequired = 0x0,
PLD_CabinetNumber = 0x0,
PLD_CardCageNumber = 0x0,
PLD_Reference = 0x0,
PLD_Rotation = 0x0,
PLD_Order = 0x0,
PLD_VerticalOffset = 0x0,
PLD_HorizontalOffset = 0x0)
)
}
Change-Id: I7024390e407fda4b195211bd4755bb5ca53b2b37
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26173
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These methods had unused arguments and could be corrected by
setting the correct number in the method initializer.
Change-Id: I86606cfa1c391e2221cee31994e83667fa9ead61
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
It is a special case for the Fizz firmware branch, when the device index
is 1, it will check "ethernet_mac" first and then "ethernet_mac0".
For single NIC: config.device_index = "1", maps to "ethernet_mac"
For multiple NICs: config.device_index = "1", maps to "ethernet_mac0"
BUG=b:77836343
BRANCH=Fizz
TEST=Add device index in device tree &&
Program the mac address to VPD in shell
vpd -s ethernet_mac=<mac address> or
vpd -s ethernet-mac[0-9]=<mac address> && reboot the system.
Ensure the MAC address was fetched correctly by ifconfig command.
Change-Id: I67fd2e999c8f9d8782f294fcafa84b8da970a3a6
Signed-off-by: David Wu <david_wu@quantatw.com>
Reviewed-on: https://review.coreboot.org/26051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Had 0x2e hardcoded, which is often the SuperIO chip. Instead,
pull the port from the PNP tree generated from devicetree.cb,
where either 0x4e or 0x2e will be specified.
Change-Id: I4a92693f8acd3a1618cefcdf6b25eb22a727e20f
Signed-off-by: Kevin Cody-Little <kcodyjr@gmail.com>
Reviewed-on: https://review.coreboot.org/26203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
In 4a3956d7 (drivers/intel/gma, soc/intel/common: improve
cooperation) the vbt_size parameter was not honored leading to
the use of unitialized variables from the caller. Instead, keep
track of if the vbt is already loaded by using the size returned
from the load. If it's non-zero the vbt has been loaded.
BUG=b:79562868
Change-Id: Ia1c47f0d982fae74e0223922f83943c68a846aa9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/26236
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of both featuring their own VBT loaders, use a single one.
It's the compression-enabled one from soc/intel/common, but moved to
drivers/intel/gma.
The rationale (besides making all the Kconfig fluff easier) is that
drivers/intel/gma is used in some capacity on all platforms that load a
VBT, while soc/intel/common's VBT code is for use with FSP.
BUG=b:79365806
TEST=GOOGLE_FALCO and GOOGLE_CHELL both build, exercising both affected
code paths.
Change-Id: I8d149c8b480e457a4f3e947f46d49ab45c65ccdc
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/26039
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use of device_t has been abandoned in ramstage.
Change-Id: I31f53f5f0e3f1fd6bd9bdbb47ea67c12b3840850
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Use of device_t has been abandoned in ramstage.
Change-Id: Ia9c705d34b90ad44272a06790fbb1041029ef77d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26069
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use of `device_t` has been abandoned in ramstage.
Change-Id: I6f6c4330ad88e013b24761a3aa1c29bc869da39d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of `device_t` has been abandoned in ramstage.
Change-Id: If2b9cbf130f963bc1bedef16b7951e9546054743
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of `device_t` has been abandoned in ramstage.
Change-Id: Idb139d5cb2ac10f4051407137242ccee1a09b785
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of `device_t` has been abandoned in ramstage.
Change-Id: If9c122efbb7dbab7d834372da3c1c70463be7a77
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of `device_t` has been abandoned in ramstage.
Change-Id: Idff2ec30f0b8c9a49f4369e231be92cbc8070dc0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Non-dts based systems can pass mclk to da7219 driver by
this property.
BUG=b:74570989
TEST=Enabled clock in kernel driver using the property
Change-Id: I2e10769e5b3c6b3aa30f340fe0e88c29b87430cb
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/25919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Some touchscreens need to adhere to certain timings during the power
off sequence as well as during the power on sequence. Adding
reset_off_delay_ms, enable_off_delay_ms, and stop_off_delay_ms to
accommodate these devices.
BUG=b:78311818
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/poppy -x -a
Change-Id: Idb4a5dbe56eee4749d2f2b514e92c28fb2c6078f
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/25882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
It's pretty well compressible which helps when space is tight.
The code encodes the assumption that the VBT is 8kb or less. Haven't
seen a larger one yet.
BUG=b:77971803,b:78541692
TEST=build, see that vbt.bin is compressed, boot, check log that the
reported VBT size is correct.
Change-Id: Ie25bca21d9edc408f441a292bbe2ab0459948ec4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/25927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use acpigen method to return _STA instead of hardcoding unreadable
bytecode.
Change-Id: I290fb918675857e8ef798e3ab820bcfbdc6f5bdc
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
To be selected by mainboard Kconfig if the board hosts an ASMedia chip
that spuriously advertises ASPM features.
Change-Id: I05f9789bc14db56d2ac085f4f14047d80c3aefb5
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/25619
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The driver relies on I/O space access functions (inb, etc.), which are
only available on x86.
Rather than explicitly disallowing it on ARM, allow it only on x86.
TEST=Configure for RISC-V, and see that "Serial port on SuperIO" is not
available in the "Generic Drivers" menu anymore.
Change-Id: Ib8e8c402264afeba6dc098683c5464af6edb3ba3
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
In some cases it may be useful to be able to bitbang a UART, such as
during early bring-up when a driver for the actual controller isn't
available yet. On some platforms we may even want to use this
permanently, such as on the SDM845 where the hardware UART controller
needs to have firmware loaded and is thus unavailable for most of the
bootblock.
This patch adds some helper code that makes it easy to implement this on
a platform, you just have to pass it a function to control the Tx pin
state and it will do the rest. It relies on the mono_time API and is
thus bound to microsecond timing granularity, but that seems to be
barely good enough for 115200 baud if the bit times are calculated
carefully.
Change-Id: If7dcecc7b8a95ec15f456efd2ec1f1e0dde239b4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/25812
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This UART is used in the SiFive FU540 SoC, and will probably be used in
other SoCs in the future.
Change-Id: I915edf39666b7a5f9550e3b7e743e97fe3cacfd3
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Julius brought up confusion about the current spi api in [1]. In order
alleviate the confusion stemming from supporting x86 spi flash
controllers:
- Remove spi_xfer_two_vectors() which was fusing transactions to
accomodate the limitations of the spi controllers themselves.
- Add spi_flash_vector_helper() for the x86 spi flash controllers to
utilize in validating driver/controller current assumptions.
- Remove the xfer() callback in the x86 spi flash drivers which
will trigger an error as these controllers can't support the api.
[1] https://mail.coreboot.org/pipermail/coreboot/2018-April/086561.html
Change-Id: Id88adc6ad5234c29a739d43521c5f344bb7d3217
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Certain TPMs (observed on Infineon SLB9635 installed on revolve 810 g1)
seem to need some delay between tis_wait_valid() and
tis_has_valid_data(), or tis_has_valid_data() may invalidly return 0,
ending the loop immaturely with some bytes left unread, and fail to
pass the check below, causing the current command not finalized by
tis_command_ready(), and blocking any later tis_wait_ready().
This time the added delay is controlled by a Kconfig option
TPM_RDRESP_NEED_DELAY.
Change-Id: Ic2a2f252e72a0bbce51e2863f8e46647b1570ba5
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/25322
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update libgfxinit to current master. Changes include:
* a fix to decode the size stolen memory correctly on pre-SandyBridge
hardware,
* a PCI id based generation check, obsoleting the old check based
on PCH audio ids,
* some minor improvements around rarely used DDI ports (D and E), and
* added support for tiled and rotated framebuffers on Skylake+ hardware
(less interesting for coreboot, I guess?).
TEST=Booted kontron/ktqm77 (Ivy Bridge) and pending kontron/bsl6
(Skylake) both with text and linear framebuffers and observed
FILO's prompt showing up.
Change-Id: I9a3c35c60b9edf8775f3a489df7577092910e127
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/25453
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The term MTRR has been misspelled in a few places.
Change-Id: I3e3c11f80de331fa45ae89779f2b8a74a0097c74
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This allows VGA output in SeaBIOS to be enabled using the
SEABIOS_VGA_COREBOOT Kconfig option. Currently, it’s impossible to select
the VGA text frame buffer in the Kconfig menu.
I'm not sure why this wasn't enabled in the first place, but
SeaVGABIOS seems to work just fine with this patch.
Tested on KCMA-D8.
Change-Id: Ic924a12fbe89940b5f26d211eb8de6cab0be767a
Signed-off-by: Daniel Gröber <dxld@darkboxed.org>
Reviewed-on: https://review.coreboot.org/25554
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change EN/DISABLED to INT_EN/DISABLED to avoid collision with other
EN/DISABLE definition.
Change-Id: I85b1c544d0f31340a09e18f4b36c1942ea0fa6ef
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/25540
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of hard-coding a lot of default values of the framebuffer config,
we use the values provided by Display_Probing.Scan_Ports() and only
overwrite what is necessary. This way we are more independent from
changes inside libgfxinit.
Change-Id: I121bbd926532c27321446282aa334cc45cdbeef1
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/25452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Aligning the stride up to a multiple of 64 pixels was flawed: We want
to actually align up to one cacheline (64 bytes) as that's the mini-
mum what the hardware supports.
Change-Id: I3f824ffd7d12835935e4e4bde29fe82dc3e16f9d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/25451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Build pl011 to support building vboot on arm platforms.
Change-Id: I1ddc372d558b380065ff944fccb0d84eb37d4213
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Sometimes when bringing up a new board it can take a while until you
have all the peripheral drivers ready. For those cases it is nice to be
able to bitbang certain protocols so that you can already get further in
the boot flow while those drivers are still being worked on. We already
have this support for I2C, but it would be nice to have something for
SPI as well, since without SPI you're not going to boot very far.
This patch adds a couple of helper functions that platforms can use to
implement bit-banging SPI with minimal effort. It also adds a proof of
concept implementation using the RK3399.
Change-Id: Ie3551f51cc9a9f8bf3a47fd5cea6d9c064da8a62
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/25394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
A change introduced by commit fe4983e5 [1] in order to prevent
re-initialization of the TPM if already set up in verstage
had the wrong logic in the if statement, causing the TPM
to never be initialized if vboot is disabled.
The RESUME_PATH_SAME_AS_BOOT config is enabled by default for
ARCH_X86, resulting in the if statement to always evaluate to
false. Remove that condition from the if statement to allow it
to function as intended.
This patch also enables TPM initialization for FSP 2.0 with
the same conditions.
[1] intel/fsp1_1: Do not re-init TPM in romstage if already setup in verstage
https://review.coreboot.org/#/c/coreboot/+/14106/
Change-Id: Ic43d1aa31a296386c7eab6d997f9b701e9ea0fe5
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23680
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The following PCI device ID can be included for jefferson peak wifi
devices driver support, and they are:
9df0 for jefferson peak on Cannonlake-LP w/CNVi
A370 for jefferson peak on Cannonlake-H w/CNVi
31dc for jefferson peak on Geminilake w/CNVi
BUG=None
TEST=None
Change-Id: I48886cea5578a302f6ef033cb35df4a38bd64ea8
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Most Intel platforms use separate registers for software-based
SMI (0xe0) and SCI (0xe8), but Atom-based platforms use a single
combined register (0xe0) for both. Adjust opregion implementation
to use the correct register for Atom-based platforms.
Test: Boot Windows on Atom-based ChromeOS device with Tianocore
payload and non-VBIOS graphics init; observe Intel display
driver loaded correctly and internal display not blank.
(requires additional change for Atom platforms to select
CONFIG_INTEL_GMA_SWSMISCI)
Change-Id: I636986226ff951dae637dca5bc3ad0e023d94243
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The rationale is to allow the mainboard to override the default
baudrate for instance by sampling GPIOs at boot.
A new configuration option is available for mainboards to select
this behaviour. It will then have to define the function
get_uart_baudrate to return the computed baudrate.
Change-Id: I970ee788bf90b9e1a8c6ccdc5eee8029d9af0ecc
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/23713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Some assumptions are made with respect to CONFIG_ROM_SIZE being the
actual size of the boot medium, e.g. when automatically creating an
fmap with and RW_MRC_CACHE region. With this patch the user is
warned when this is detected.
Change-Id: Ib5d6cc61ea29214d338d4c52ff799d6620a9cac7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Procedures acpi_device_scope() and acpi_device_name() can under certain
conditions return NULL. Check the return before using them.
This fixes CID 1385944
BUG=b:73331544
TEST=Build kahlee.
Change-Id: Ifcdf905100d22a1d828394f8685641eb432bb836
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23760
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The chip PCA9538 is a 8 bit I/O expander connected to the systems I2C
bus. Add a chip driver to support this chip.
Beside the pure chip driver two interface functions are provided to read
the state of the pins and write output values to the pins.
As the slave address of this chip is hardware configurable the function
pca9538_get_dev() is used to get the right slave address. This function
needs to be implemented in mainboard code if one needs to use the
interface functions to read and write I/O state.
Change-Id: Ic856123b4f4c8b721928ee3a2a4bb37833ea4b20
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/23748
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds a struct for registers along with some bits from ATF to
the generic PL011 driver. It also adds a naive implementation of
uart_tx_flush() which was previously stubbed out.
Change-Id: Iee3fc6308cb92ad784e5ff3ac3a6e995d535be65
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/23031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The ADAU7002 is a family of Stereo PDM-to-I2S/TDM conversion ICs from
Analog Devices. On some boards they are a used to convert a PDM audio
data stream from a DMIC to an I2S signal.
Add a driver for populating ACPI table entries for this part.
BUG=b:72121803
TEST=With grunt audio kernel patches, "aplay -l" shows playback devices:
**** List of PLAYBACK Hardware Devices ****
card 0: acpd7219m98357 [acpd7219m98357], device 0: Playback da7219-hifi-0 []
Subdevices: 1/1
Subdevice #0: subdevice #0
card 0: acpd7219m98357 [acpd7219m98357], device 2: HiFi Playback HiFi-2 []
Subdevices: 1/1
Subdevice #0: subdevice #0
Change-Id: I2b64c8e1cbc0a68984482a7d496f8c4498cb6cbe
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23659
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Martin Roth <martinroth@google.com>
As per FSP 2.0 specification and FSP SOC integration guide, its not expected
that SMBIOS Memory Information GUID will be same for all platform. Hence
fsp_find_smbios_memory_info() function inside common/driver code is not
generic one.
Removing this function and making use of fsp_find_extension_hob_by_guid()
to find SMBIOS Memory Info GUID from platform code as needed.
Change-Id: Ifd5abcd3e0733cedf61fa3dda7230cf3da6b14ce
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The designware i2c controller indicates that the slave address
shouldn't be programmed while the controller is enabled. Therefore,
switch the ordering of the slave target address and the enable.
Additionally, ensure the controller is disabled prior to the
start of the slave programming sequence.
Lastly, chunk up the i2c_msg segments at differing slave address
boundaries. That allows for simpler programming for the controller
by only doing one slave address transaction chunk at a time.
BUG=b:70232394,b:69250772
Change-Id: Iebc08e2db847cb182fad98e0ff3d799b9a64aca7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
To set address on AMD, IC_ENABLE == 0.
BUG=b:69416132
BRANCH=none
TEST=Test communication with i2c TPM on grunt and coral
Change-Id: I7faee8e11439deceab946cc82d30d274b529b90d
Signed-off-by: Chris Ching <chingcodes@chromium.org>
Reviewed-on: https://review.coreboot.org/23293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This patch locates FSP FVI hob in order to extract all firmware
ingredient version information.
So far this feature is only supported for CannonLake SoC onwards.
Change-Id: Ib749e49a9f263d85947b60d4c445faf8c37f5931
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23386
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Users are getting build error due to duplicate macro definitions
of same resource type between fsp driver code and UEFI headers.
Hence this patch ensures to refer a single source location for
macro definitions to avoid compilation error.
Change-Id: If022eb29550a9310b095bff6130b02fb0a25ef7a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Now SOC code can select the require UDK support package for any
platform going forward with FSP2.0 model.
Change-Id: Ie6d1b9133892c59210a659ef0ad4b59ebf9f1e45
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Grunt (a amd-stoneyridge based platform) uses a GPIO to interface with
the tpm. This change allows devicetree entries to use a irq_gpio entry
to describe the interface with the TPM.
BUG=b:72655090
Change-Id: I08289891408d7176f68eb9c67f7a417a2448c2de
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
spi_crop_chunk() currently supports deducting the command length
when determining maximum payload size in a transaction. Add support
for deducting just the opcode part of the command by replacing
deduct_cmd_len field to generic flags field. The two enums supported
drive the logic within spi_crop_chunk():
SPI_CNTRLR_DEDUCT_CMD_LEN
SPI_CNTRLR_DEDUCT_OPCODE_LEN
All existing users of deduct_cmd_len were converted to using the
flags field.
BUG=b:65485690
Change-Id: I771fba684f0ed76ffdc8573aa10f775070edc691
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23491
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The spi_flash_cmd_read_fast() and spi_flash_cmd_read_slow() were just
passing full size buffers to the spi controller ops. However, the
code wasn't honoring what the spi controller can actually perform.
This would cause failures to read on controllers when large requests
were sent in. Fix this by introducing a
spi_flash_cmd_read_array_wrapped() function that calls
spi_flash_cmd_read_array() in a loop once the maximum transfer size is
calculated based on the spi controller's settings.
BUG=b:65485690
Change-Id: I442d6e77a93fda411cb289b606189e490a4e464e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Right now dw_i2c_get_soc_cfg() is expecting the SoC to implement
that callback for obtaining the bus config. However, we're currently
forcing another parameter of struct device so one can do the lookup.
This works for Intel-based systems since the struct device was needed
to program the BAR, etc. However, from an API standpoint, it just
complicates matters by needing to obtain the struct device. The SoC
already has knowlege of its own devices so it can get the config
itself by bus number. Therefore, remove that contraint from the API.
BUG=b:70232394
Change-Id: Id8558f5deedda0963a46a532a7bf984e168fb270
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23420
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
In ramstage the device_operations are needed for the i2c designware
host controller. Move the intel/common/block/i2c implementation
into the generic driver so other platforms can take advantage of it.
BUG=b:72121803
Change-Id: Id249933fadcc016bfba00e7a6d65f56dfc220724
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
If one wants to implement both i2c_bus.h and i2c_simple.h APIs
the compilation unit needs to be guarded or coordinated carefully
with different compilation units. Instead, name the i2c_bus
functions with _dev such that it indicates that they operate on
struct device. One other change to allow i2c_bus.h to be built in
non-ramstage environments is to ensure DEVTREE_CONST is used for
the dev field in struct bus.
BUG=b:72121803
Change-Id: I267e27e62c95013e8ff8b0728dbe9e7b523de453
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
With no boards left using AGESA_LEGACY, wipe out remains
of that everywhere in the tree.
Change-Id: I0ddc1f400e56e42fe8a43b4766195e3a187dcea6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch adds a member device_index to r8168 chip information which
allows driver to identify which NIC card requests MAC address.
In this implementation, only 10 NIC cards are supported, the device
index is in the range of 0 to 10. Regarding to MAC address mapping,
when there is only one NIC on DUT, it is treated as a special case
mapping to "ethernet_mac" in VPD for backward compatibility. When
there are multiple NICs on DUT, they are mapping to "ethernet_macN"
where N is [0-9].
Device tree configuration:
For single NIC: .device_index = "0", maps to "ethernet_mac"
For multiple NICs: .device_index = "[1-10]", maps to
"ethernet_mac[device_index - 1]"
BUG=b:69950854
BRANCH=None
TEST=Added device_index = [0-10] under /drivers/net in device tree &&
Programmed the mac address to VPD in shell
vpd -s ethernet_mac=<mac address> or
vpd -s ethernet-mac[0-9]=<mac address> && reboot the system.
Ensure the MAC address was fetched correctly by ifconfig command.
Change-Id: I108b9bfba39370c8906a2fa4d2b39b106e884e0c
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/22984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This automatically generates an FMAP region for the MRC_CACHE driver
which is easier to handle than a cbfsfile.
Adds some spaces and more comments to Makefile.inc to improve
readability.
Tested on Thinkpad x200 with some proof of concept patches.
Change-Id: Iaaca36b1123b094ec1bbe5df4fb25660919173ca
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The default time for writing MRC data to flash is at the exit of
BS_DEV_ENUMERATE but this is too early for some implementations.
Add an option to Kconfig for allowing a late option to be selected.
The timing of the late option is at the entry of BS_OS_RESUME_CHECK.
TEST=Select option and inspect console log on Kahlee
BUG=b:69614064
Change-Id: Ie7ba9070829d98414ee788e14d1a768145d742ea
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22937
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Ported from commit e6033ce1
soc/amd/common/block/pi: Fix AGESA heap deallocator
The deallocation was always subtracting the header, even when it
shouldn't. This caused problems for the allocator where buffer
sizes were incorrect and freed and used buffers could collide.
Fix the deallocation size.
Clear deallocated concatinated buffer header memory.
Fix the initial calculation of the total buffer size
available to be allocated.
Original-Change-Id: I2789ddf72d662f24709dc5d9873741169cc4ef36
Change-Id: Ibac916fcd964adca97a72617428e3d53012e13a1
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* Move code from src/lib and src/include into src/security/tpm
* Split TPM TSS 1.2 and 2.0
* Fix header includes
* Add a new directory structure with kconfig and makefile includes
Change-Id: Id15a9aa6bd367560318dfcfd450bf5626ea0ec2b
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Currently bootmode default is set to FSP_BOOT_WITH_FULL_CONFIGURATION
and bootmode UPD is updated in fsp_fill_mrc_cache based on mrc cache data
validity. With current implementation in S3 resume path, if mrc cache
data is invalid, the bootmode is not updated further and remains set
at FSP_BOOT_WITH_FULL_CONFIGURATION. This results in fsp-m to get
incorrect boot mode context and reinitialize memory in S3 resume
path. In correct flow fspm should have correct bootmode context
i.e. S3 resume and return error in case mrc cache data is invalid
or not found.
BUG=b:70973961
BRANCH=None
TEST=Verify correct bootmode is set on S3 resume, even when
mrc cache data is invalid.
Change-Id: Idc0da6ffbfe5ce616d852908a9b0074dc8ce7cbe
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/23156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In S3 resume, for cases if valid mrc cache data is not found or
RECOVERY_MRC_CACHE hash verification fails, the S3 data pointer
would be null and bootmode is set to BOOT_WITH_FULL_CONFIGURATION.
This gets memory to be retrained in S3 flow. Data context including
that of imdr root pointer would be lost, invoking a hard reset in
romstage post memory init. Issuing hard reset before memory init,
saves fsp memory initialization and training overhead.
BUG=b:70973961
BRANCH=None
TEST=Verify S3 resume flows on soraka.
Change-Id: Ibd6d66793ed57c2596d9628c826f6ad198aad58b
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/22985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Don't allow the user to select this manually, since it doesn't build
on platforms that don't use it.
Don't set the bool value so that it doesn't show as not selected in
the .config file of platforms that don't use this.
Change-Id: Icf026a297204868d485be270ccee7e0bec0ac73b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
While the older boards use a GPIO that has no state, the newer boards'
PMH7 does have a state, that even remains after reboot.
Don't assume default values in PMH7 and instead always program it.
Fixes dGPU doesn't show up when switching from integrated to discrete
GPU. The workaround of removing all power is no longer necessary.
Change-Id: I30ec19e13269cb254e51ad1fab3b10ad1a49e86e
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
In commit decd0628 (drivers/mrc_cache: move mrc_cache support to
drivers) mrc.cache is always added, but CONFIG_MRC_SETTINGS_CACHE_SIZE
is not used in Sandy Bridge, which makes mrc.cache have zero size and
the machine will fail to boot after the first boot.
Change-Id: Iab3ac87e43408ef51f0158f319eb1c8ccfce8a55
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/22925
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Seeing some instances were cr50 spi driver is starting a new
transaction without getting a ready interrupt from cr50, which means
that there are pending interrupts. Clearing these to be sure there
are not any stale irqs for the next transaction.
BUG=b:69567837
BRANCH=None
TEST=run FAFT and see if any 0x2b recovery boots occur
Change-Id: Ie099da9f2b3c4da417648ae10a5ba356b7a093ff
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/22909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There's nothing intel-specific about the current mrc_cache support.
It's logic manages saving non-volatile areas into the boot media.
Therefore, expose it to the rest of the system for any and all to
use.
BUG=b:69614064
Change-Id: I3b331c82a102f88912a3e10507a70207fb20aecc
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Provide a spi controller specific protection callback to take
advantage of special spi flash controllers that have internal
protection registers built into the implementation. It's an
optional callback for spi controllers.
BUG=b:69614064
Change-Id: Ie50a6ce3bbda32620a25dd26fda1af944940bf28
Signed-off-by: Aaron Durbn <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Enable the flashconsole driver in verstage so it can be used
with VBOOT enabled. This was tested on a VBOOT enabled system
using flashconsole to store the boot log.
Change-Id: Icd8a82dc962ece85b9fb3d2f5654369e821922eb
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/22855
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The opregion and fields are left over from when ACPI ASL code was
reading registers to determine the current setup. Now that the
ACPI device is generated with the correct information already this
code is not used at all and can be removed from the tree.
Change-Id: If89d90cc7105ed21e2134ac99224f6f8214cc8ad
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/22854
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This is required at least on Skylake to be able to configure text mode.
3rdparty/libgfxinit is also updated by the single commit:
42fb2d065d gma: Add procedure to power up legacy VGA block
Change-Id: I2fe144765e2b2acd9f6b76db375cae5b8feb5489
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/21386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Merge the different coreboot table strapping ID structures into one
because they're really just all the same, and I want to add more. Make
the signature of the board_id() function return a uint32_t because
that's also what goes in the coreboot table. Add a printk to the generic
code handling strapping IDs in ramstage so that not every individual
mainboard implementation needs its own print. (In turn, remove one such
print from fsp1_1 code because it's in the way of my next patch.)
Change-Id: Ib9563edf07b623a586a4dc168fe357564c5e68b5
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Cr50 secure chip implementation is guaranteed not to fall asleep
for 1 second after any SPI slave activity.
Let's not waste time on the wake up ping when it is not necessary.
BRANCH=cr50
BUG=b:68012381
TEST=using a protocol analyzer verified that the wake pulses are
generated only when the new coreboot stage or depthcharge start,
not on every SPI slave transaction.
Change-Id: Id8def1470ba3eab533075b9e7180f8a58e0b00b6
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/22321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds SSDT ACPI generator and declares _UID, _HID, _DDN and
also _PRW for WOL feature. Besides, adds a wake variable in chip
information.
BUG=b:69290148
BRANCH=None
TEST=Add register "wake" = "GPE0_PCI_EXP" in devicetree under r8168
chip driver && dump SSDT to make sure _UID, _HID, _DDN and _PRW
are filled correctly && put system into S3 && sudo etherwake -i
eth0 $MAC to make sure the system could be woken up by WOL package.
Change-Id: Ibc9115e8a08ba2bfcb3ee1e34c73cf1976a6ba2d
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/22480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The Cr50 i2c driver provides separate entry points for probing and
initialization, but probing function does not really do much.
It also claims and releases locality on every coreboot stage, but
there is no need for this - locality should be definitely claimed
after reset and then it could be retained through the boot process.
On top of that the driver does not properly account for long time it
could take the Cr50 chip to come around to reset processing if TPM
reset request was posted during a lengthy TPM operation.
This patch addresses the issues as follows:
- tpm_vendor_probe() and tpm_vendor_cleanup() become noops, kept
around to conform to the expected driver API.
- tpm_vendor_init() invokes a function to process TPM reset only in
the first stage using TPM (typically verstage), the function
checks if locality is claimed and if so - waits for it to be
released, which indicates that TPM reset processing is over.
- before claiming locality check if it is already taken, and if so -
just proceed.
BRANCH=none
BUG=b:65867313, b:68729265
TEST=Verified that reef no longer hangs during EC reboot and
firmware_Cr50ClearTPMOwner (not yet merged) tests.
Change-Id: Iba8445caf1342e3a5fefcb2664b0759a1a8e84e3
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/22554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
All coreboot stages using TPM start with the same sequence: check if
locality is claimed, if so, release it by writing 'active locality'
bit, then try claiming it.
This is actually not a proper procedure: section "5.5.2.3.1 Command
Aborts" of "TCG PC Client Platform TPM Profile (PTP) Specification
Level 00 Revision 00.430 Family 2" lists overwriting active locality
status bit as a means of triggering TPM command abort.
On top of that, none of the coreboot stages releases locality, it is
enough to claim it once when device starts booting.
In fact, locality being active when the device is in verstage is most
likely due to delayed TPM reset processing by the Cr50 TPM: reset is
an asynchronous event, and is processed once current command
processing completes.
The proper procedure is to wait if locality is active until it is
released (which will happen when Cr50 processes reset) and then
proceed to claim it. This needs to happen only during verstage, other
stages using TPM are guaranteed has been claimed earlier.
BRANCH=gru
BUG=b:65867313
TEST=the new autotest triggering EC reset during key generation
process does not cause boot failures on Fizz device any more.
Below are times verstage had to wait:
TPM ready after 3132 ms
TPM ready after 22120 ms
TPM ready after 4936 ms
TPM ready after 6445 ms
TPM ready after 11798 ms
TPM ready after 27421 ms
TPM ready after 4582 ms
TPM ready after 7532 ms
TPM ready after 27920 ms
TPM ready after 3539 ms
TPM ready after 12557 ms
TPM ready after 6773 ms
TPM ready after 1631 ms
TPM ready after 197 ms
TPM ready after 24330 ms
TPM ready after 3241 ms
Change-Id: Iaee04f009bcde03712483e5e03de4a3441ea32b1
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/22489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
In case the TPM is doing a long crypto operation the initial probe
could be very delayed. Rather than end up in recovery make the delay
long enough to accommodate the (current) long crypto times. This would
add a maximum of 30 seconds to boot time.
Mirroring changes done on i2c side in CL:756918
BUG=b:65867313, b:68729265
BRANCH=None
TEST=Make sure fizz boots up
Change-Id: Ie944bfb6fe33d6e9ee794439165716ab624be491
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/22370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In case the TPM is doing a long crypto operation the initial probe
could be very delayed. Rather than end up in recovery make the delay
long enough to accommodate the (current) long crypto times.
BUG=b:65867313, b:68729265
TEST=Verified that Soraka no longer hangs during EC reboot test.
Change-Id: I3bccff70e001dfc065c24be8ad34ef239a144db1
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Some Siemens copyright entries incorrectly contain a dot at the end of
the line. This is fixed with this patch.
Change-Id: I8d98f9a7caad65f7d14c3c2a0de67cb636340116
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/22355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Once coreboot is ready and payload has been loaded a bit inside the NC
FPGA needs to be set to notify this event. As there are NC FPGAs with
different PCI device IDs save the BAR0 address in a global variable once
the driver evaluates this address. It can then be used to access the
register from the boot state machine callback without the need of searching
for all possible PCI devices again.
As this driver is only used at ramstage there is no need of using
CAR_GLOBAL for the global variable. Use a Kconfig switch to make this
feature selectable from mainboard as not every mainboard may have a FPGA
with that capability.
Change-Id: I9cd09e7051edde30d144a7e020b84bb549e9e8b9
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/22138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When Cr50 TPM is being reset, it continues replying to the SPI bus
requests, sends wrong register values in response to read requests.
This patch makes sure that the TPM driver does not proceed unless
proper value is read from the TPM device identification register.
If the read value is still wrong after 10 retries taken with 10 ms
intervals, the driver gives up and declares TPM broken/unavailable.
BRANCH=cr50
BUG=b:68012381
TEST=ran a script resetting the Fizz device as soon as the "index
0x1007 return code 0" string shows up in the AP console output.
The script keeps rebooting the Fizz indefinitely, before this
script Fizz would fail to read TPM properly and fall into
recovery after no more than four reboots.
Change-Id: I7e67ec62c2bf31077b9ae558e09214d07eccf96b
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/22231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds a function to program a customized LED setting
for Realtek 81xx family. It reads the settings from devicetree under
target board and programs the setting to offset 0x18 and 0x19.
BUG=b:65437780
TEST=Add customized_leds register in devicetree.cb under target board,
enable RT8168_SET_LED_MODE flag. Make sure the setting is
programmed correctly to offset 0x18 and 0x19. Observed the
LEDs were behaving as expected. Executed suspend/resume and
the LEDs were still working as expected.
Change-Id: Ib3d4f2cd98ac391e1661a891d604bdd1974d07f6
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/21862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Simplifies our C interface function gma_gfxinit(), due to the following
changes:
* *libgfxinit* knows about the underlying PCI device now and can
probe MMIO addresses by itself.
* The framebuffer mapping is now completely handled inside the
library where we validate that we neither overflow
- the stolen memory,
- the GTT address space, the GTT itself nor
- the aperture window (i.e. resource2 of the PCI device)
that we use to access the framebuffer.
Other changes:
* Fixes and a quirk for DP training.
* Fix for DP-VGA adapters that report an analog display in EDID.
* Fixes for Skylake support with coreboot.
* DDI Buffer drive-strength configuration for Haswell, Broadwell and
Skylake.
* `gfx_test` can now be run from X windows (with glitches).
* Compatibility with GCC 7 and SPARK GPL 2017.
TEST=Booted lenovo/t420 and verified that everything works as usual.
Change-Id: I001ba973d864811503410579fd7ad55ab8612759
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The current header `i915.h` is too invasive to be used everywhere where
we want to use *libgfxinit*.
Change-Id: Iba57256d536e301e598d98182448d2daa1bf9a89
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Although Intel's current spec[1] shows the OpRegion structure version
as being the top 16 bits of the field, Intel's Windows drivers
require the OpRegion structure version to be in the top 8 bits of
the field when not using a VGA BIOS (eg, NGI or GOP driver).
As the Linux i915 driver only checks that the version is >= 2,
there is no change in functionality there.
This change effectively matches Intel's implementation in TianoCore,
where the version is set to 0x0200 << 16.
[1] https://01.org/sites/default/files/documentation/skl_opregion_rev0p5.pdf
TEST: Boot Windows [8.1,10] in UEFI mode w/GOP graphics init and
Legacy mode with libgfxinit, observe Intel GPU driver functional.
Change-Id: Ic2903ee4829689ec4117aec93dce0b87cec6f313
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit just moves the vboot sources into
the security directory and fixes kconfig/makefile paths.
Fix vboot2 headers
Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
There are still Ethernet drivers out there in the wild which expect
that the master enable bit was set by firmware. A missing master
enable bit will lead to a non-functional driver. Though it is clear the
task of the driver to set this bit it is too late now. So work around
this issue on firmware level...again!
Change-Id: I677b22c643b73634b1a2129d948b991446e1f8fd
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/22036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
1. Add support for new GSMI commands to log S0ix entry/exit
information in elog.
2. In case of resume, provide callbacks to allow platform and
mainboard to log any wake source information.
BUG=b:67874513
Change-Id: I593e8a9e31cad720ac1f77aab447a0dbdbe9a28b
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add hexdump.c to Makefile.inc and change an elog_debug format to
use %z for size_t arguments. This corrects build errors when ELOG_DEBUG
is used.
Change-Id: I3d5547eed8ada7c4bdcbbb8bb9d6965ade73beda
Signed-off-by: John E. Kabat Jr <john.kabat@scarletltd.com>
Reviewed-on: https://review.coreboot.org/21769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If FSP 2.0 is used, then postcar stage is used and the flashconsole
as well as spi drivers needed to be added.
Change-Id: I46d720a9d1fe18a95c9407d08dae1eb70ae6720e
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/21959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Before adding a new UART to the coreboot/lb table, verify that it
has a non-zero base address. This is consistent with all other
functions that use the uart_platform_base() function.
This was tested on google/kahlee by using an invalid UART number
and forcing the base address to 0. Execution was able to complete
through depthcharge and into the OS.
Change-Id: I6d8183a461f0fedc254bf88de5ec96629a2a80ef
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21996
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a new common method to initialize ACPI OpRegion.
* Try to locate vbt.bin in CBFS.
* Try to locate VBIOS in CBFS.
* Keep existing code to probe at 0xc0000.
Tested on Lenovo T430 (sandybridge) using vbt.bin, tested using buggy
VBIOS with wrong vbt_offset, tested with fake vbt written by NGI at
0xc0000.
Tested with https://review.coreboot.org/#/c/21766/ on i945 (using fake
vbt at 0xc0000), x4x (using vbt.bin) and gm45 (using vendor VBIOS).
In all cases linux was successfully provided with VBT from ACPI
opregion.
Change-Id: I8ee50ea9900537bd9e3ca5ab0cd3f48d2acec970
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Instead of having all callers provide a region_device just for the
purpose of reading vbt.bin, let locate_vbt handle its entire life cycle,
simplifying the VBT access API.
Change-Id: Ib85e55164e217050b67674d020d17b2edf5ad14d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21897
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All callers of locate_vbt just care about the file content and
immediately map the rdev for its content.
Instead of repeating this in all call sites, move that code to
locate_vbt.
Change-Id: I5b518e6c959437bd8f393269db7955358a786719
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
No need for having two of everything in the coreboot codebase.
Change-Id: Ie1cdd1783dd5dababd1e97436a4ce1a4f068d5b3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/21723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch removes checks that ensure EC to be in RO for recovery
boot. We do not need these checks because when recovery is requested
automatically (as opposed to manually), we show 'broken' screen where
users can only reboot the device or request recovery manually.
If recovery is requested, Depthcharge will check whether EC is in RO
or not and recovery switch was pressed or not. If it's a legitimate
manual recovery, EC should be in RO. Thus, we can trust the recovery
button state it reports.
This patch removes all calls to google_chromeec_check_ec_image,
which is called to avoid duplicate memory training when recovery
is requested but EC is in RW.
BUG=b:66516882
BRANCH=none
CQ-DEPEND=CL:693008
TEST=Boot Fizz.
Change-Id: I45a874b73c46ea88cb831485757d194faa9f4c99
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/21711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
For general use of this driver it is necessary to move some parameters
from init_fan_ctrl() to init_temp_mon(). This shift does not lead to any
functional change.
Change-Id: I6b8f770c768f3dacf96087eb0194cc99f0d11e17
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/21694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Remove the USBDEBUG_DONGLE_BEAGLEBONE_BLACK option that does the same as
USBDEBUG_DONGLE_STD and update the description of USBDEBUG_DONGLE_STD that it
also should be selected for the BeagleBone Black.
Change-Id: I3093a6d2c39e7b5e81785028e436109090d9e6dd
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/21486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
New AGESA support files will be used for binaryPI
platforms as well. Furthermore, some of those should
move from split nb/ sb/ directories to soc/, so move
support files for the API under drivers/.
Change-Id: I549788091de91f61de8b9adc223d52ffb5732235
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There have been discussions about removing this since it does not seem
to be used much and only creates troubles for boards without defaults,
not to mention that it was configurable on many boards that do not
even feature uart.
It is still possible to configure the baudrate through the Kconfig
option.
Change-Id: I71698d9b188eeac73670b18b757dff5fcea0df41
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Instead of having each potential caller deal with the differences
of cmos_init() and init_vbnv_cmos() when VBOOT is enabled put the
correct logic within the callee, cmos_init(), for handling the
vbnv in CMOS. The internal __cmos_init() routine returns when the
CMOS area was cleared.
BUG=b:63054105
Change-Id: Ia124bcd61d3ac03e899a4ecf3645fc4b7a558f03
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21549
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's no reason to mutate the struct device when determining
the ACPI name for a device. Adjust the function pointer
signature and the respective implementations to use const
struct device.
Change-Id: If5e1f4de36a53646616581b01f47c4e86822c42e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
It was originally designed such that if usbdebug_init() was called
before cbmem_initialize(), it would fetch the already-initialized
state from CBMEM. This changed when cbmem_find() behaviour changed
to require cbmem_initialize() to be called first. As a result,
ramstage had to reinitialize all of the EHCI controller and USB
endpoints on entry. This was slow, specially with AMD hardware
where one can scan USB ports to probe for the debug dongle.
For postcar and ramstage, move usbdebug entry such that it is
triggered from CBMEM_INIT_HOOK instead of console_init().
Side-effect of this is usbdebug console shows 'coreboot-xxx ...
starting...' line only for romstage.
Initialisation for usbdebug is never done in postcar. If you have
USBDEBUG_IN_ROMSTAGE=n, postcar will not have console output on
usb either.
While at it, fix also some other __PRE_RAM__ cases to ENV_ROMSTAGE
and alike.
Change-Id: If8ab973321a801abc5529f3ff68c5dccae9512ad
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
To avoid error with symbol redefinition (using clang):
src/drivers/intel/fsp1_0/fsp_util.c:111:22: error: invalid symbol redefinition
".global find_fsp\n\t"
Rename the asm global symbol to find_fsp_bypass_prologue and fix jmp.
Change-Id: I84c152f9a580fdfc40e9f6e998d2d6484b7f47df
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/21353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
With FSP 1.1, all FSP blobs are forward-compatible with newer FSP 1.1
header files, so adjust the header revision check to ensure that the
FSP blob isn't newer than the header, rather than an exact version match.
This resolves a version mismatch issue with Braswell ChromeOS devices,
which ship with FSP blobs newer than the publicly-released blob (1.1.2.0),
but older than the current Braswell FSP 1.1 header (1.1.7.0).
TEST: build/boot google/cyan and edgar boards, observe no adverse
effects from using current FSP header (1.1.7.0) with the factory-
shipped FSP blobs (1.1.4.0/1.1.4.2).
Change-Id: I8934675a2deed260886a83fa34512904c40af8e1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21369
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change list adds imon and vmon slot numbers as params for
Maxim 98927 driver. These values are looked up in the kernel driver
to confiure IV feedback for audio playback on speakers.
BUG=b:36724448
TEST=After boot, the register dump for Max98927 codecs should have
imon and vmon slots numbers set in 0x1e register.
Change-Id: I21d72ba91af83782587f11018b2d1d1c8d4f676c
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/21195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Move ADD_VBT_DATA_FILE to "Devices" menu and rename it to
INTEL_GMA_ADD_VBT_DATA_FILE.
Depend on Intel platforms to avoid confusing users of non-Intel platforms.
The Intel GMA driver will use the vbt.bin, if present, to fill the
ACPI OpRegion.
Change-Id: I688bac339c32e9c856642a0f4bd5929beef06409
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
There is at least one I2C device (being used by Soraka) that has 3
controls -- enable, reset and stop. If the stop gpio is not put into
the right state when turning off the device in suspend mode, then it
causes leakage. Thus, we need control in power resource to be able to
stop the device when entering suspend state.
BUG=b:64987428
TEST=Verified on soraka that touchscreen stop is correctly configured
on suspend.
Change-Id: Iae5ec7eb3972c5c7f80956d60d0d3c321bbefb0f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21249
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replaces the ics/954309 driver with a more generic version to
accommodate clockgens with a different amount of registers.
It also features a mask to only touch certain bits of the clockgen.
TODO: set appropriate mask for X60/T60 since the datasheets for their
clockgens can be found.
Change-Id: Ie43c4de7891a39f2f443e78213ecd688134e68d7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Add support for providing additional free form device properties via
devicetree in order to make this driver suitable for kernel drivers
that need additional board-specific device properties.
This currently allows adding up to 10 additional properties to a device.
BUG=b:63413023
TEST=manual testing to ensure that newly added properties are in SSDT
Change-Id: I2b8ceb208f4aba01053746547def6d07c8f8f3a2
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/21270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch to ensure that coreboot is able to store memory
training data into SPI and perform platform lockdown after
PCI enumeration is done before handing over control to
NotifyPhase() - Post PCI enumeration.
Modified coreboot bootstate execution order below:
BS_DEV_ENUMERATE - BS_ON_EXIT - Store Memory training data into SPI
BS_DEV_RESOURCES - BS_ON_EXIT - Platform Lock Down after PCI enumeration
BS_DEV_ENABLE - BS_ON_ENTRY - NotifyPhase() post PCI enumeration
TEST=Please find test case and results for Chrome Devices as Apollolake- Reef,
Kabylake-Eve and Poppy and Non Chrome Devices with Yocto OS.
1.
Without patches
Cold Boot
MRC: no data in 'RW_MRC_CACHE'
...
MRC: Checking cached data update for 'RW_MRC_CACHE'.
SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000
MRC: no data in 'RW_MRC_CACHE'
MRC: cache data 'RW_MRC_CACHE' needs update.
MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
Warm Reboot from Chrome CMD Line: $ reboot
MRC cache found, size 18c8 bootmode:2
...
MRC: Checking cached data update for 'RW_MRC_CACHE'.
SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000
MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
Suspend Stress from Chrome CMD Line: $ echo mem > /sys/power/state
MRC cache found, size 18c8 bootmode:17
...
MRC: Checking cached data update for 'RW_MRC_CACHE'.
SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000
MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
2.
With patches
Cold Boot
MRC: no data in 'RW_MRC_CACHE'
...
MRC: Checking cached data update for 'RW_MRC_CACHE'.
SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000
MRC: no data in 'RW_MRC_CACHE'
MRC: cache data 'RW_MRC_CACHE' needs update.
MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
Warm Reboot from Yocto CMD Line: $ reboot
MRC cache found, size 18c8 bootmode:2
...
MRC: Checking cached data update for 'RW_MRC_CACHE'.
SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000
MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
Suspend Stress from Chrome CMD Line: $ echo mem > /sys/power/state
MRC cache found, size 18c8 bootmode:17
...
MRC: Checking cached data update for 'RW_MRC_CACHE'.
SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000
MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
Tested the patches more thoroughly, from the S5->S0, S3->S0 bootlog there
is no noticeable difference.
On a reboot, suspend resume from Chrome console, the mrc cache is found,
and utilized.
Change-Id: I4cb4eac5256c1ce98f51adad0be6e69f7d05d8e1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Split `i2c.h` into three pieces to ease reuse of the generic defi-
nitions. No code is changed.
* `i2c.h` - keeps the generic definitions
* `i2c_simple.h` - holds the current, limited to one controller driver
per board, devicetree independent I2C interface
* `i2c_bus.h` - will become the devicetree compatible interface for
native I2C (e.g. non-SMBus) controllers
Change-Id: I382d45c70f9314588663e1284f264f877469c74d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move the FSP-specific call for tearing down cache-as-RAM out of
postcar.c and replace it with an empty weak function.
This patch omits checking if (IS_ENABLED(CONFIG_FSP_CAR)). The
temp_ram_exit.c file with the real fsp_temp_ram_exit() is only built
when CONFIG_FSP_CAR is true.
Change-Id: I9adbb1f2a7b2ff50d9f36d5a3640f63410c09479
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20965
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Initialize postcar frame once finish FSP memoryinit
This patch was merged too early and reverted.
Originally reviewed on https://review.coreboot.org/#/c/20534
Change-Id: Id36aa44bb7a89303bc22e92e0313cf685351690a
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20688
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Our current struct for I2C segments `i2c_seg` was close to being compa-
tible to the Linux version `i2c_msg`, close to being compatible to SMBus
and close to being readable (e.g. what was `chip` supposed to mean?) but
turned out to be hard to fix.
Instead of extending it in a backwards compatible way (and not touching
current controller drivers), replace it with a Linux source compatible
`struct i2c_msg` and patch all the drivers and users with Coccinelle.
The new `struct i2c_msg` should ease porting drivers from Linux and help
to write SMBus compatible controller drivers.
Beside integer type changes, the field `read` is replaced with a generic
field `flags` and `chip` is renamed to `slave`.
Patched with Coccinelle using the clumsy spatch below and some manual
changes:
* Nested struct initializers and one field access skipped by Coccinelle.
* Removed assumption in the code that I2C_M_RD is 1.
* In `i2c.h`, changed all occurences of `chip` to `slave`.
@@ @@
-struct i2c_seg
+struct i2c_msg
@@ identifier msg; expression e; @@
(
struct i2c_msg msg = {
- .read = 0,
+ .flags = 0,
};
|
struct i2c_msg msg = {
- .read = 1,
+ .flags = I2C_M_RD,
};
|
struct i2c_msg msg = {
- .chip = e,
+ .slave = e,
};
)
@@ struct i2c_msg msg; statement S1, S2; @@
(
-if (msg.read)
+if (msg.flags & I2C_M_RD)
S1 else S2
|
-if (msg.read)
+if (msg.flags & I2C_M_RD)
S1
)
@@ struct i2c_msg *msg; statement S1, S2; @@
(
-if (msg->read)
+if (msg->flags & I2C_M_RD)
S1 else S2
|
-if (msg->read)
+if (msg->flags & I2C_M_RD)
S1
)
@@ struct i2c_msg msg; expression e; @@
(
-msg.read = 0;
+msg.flags = 0;
|
-msg.read = 1;
+msg.flags = I2C_M_RD;
|
-msg.read = e;
+msg.flags = e ? I2C_M_RD : 0;
|
-!!(msg.read)
+(msg.flags & I2C_M_RD)
|
-(msg.read)
+(msg.flags & I2C_M_RD)
)
@@ struct i2c_msg *msg; expression e; @@
(
-msg->read = 0;
+msg->flags = 0;
|
-msg->read = 1;
+msg->flags = I2C_M_RD;
|
-msg->read = e;
+msg->flags = e ? I2C_M_RD : 0;
|
-!!(msg->read)
+(msg->flags & I2C_M_RD)
|
-(msg->read)
+(msg->flags & I2C_M_RD)
)
@@ struct i2c_msg msg; @@
-msg.chip
+msg.slave
@@ struct i2c_msg *msg; expression e; @@
-msg[e].chip
+msg[e].slave
@ slave disable ptr_to_array @ struct i2c_msg *msg; @@
-msg->chip
+msg->slave
Change-Id: Ifd7cabf0a18ffd7a1def25d1d7059b713d0b7ea9
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
These Kconfig options can be reused for the same purpose of selecting
the correct i2c pins for probing the analog output EDID in C native
graphic init. For this purpose this patch makes those options
independent of GFX_GMA and MAINBOARD_HAS_LIBGFXINIT.
Change-Id: If29c541d414e12b95d96ae9c249a7a20e863fe06
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Migrate opregion code from northbridge/intel/common to
drivers/intel/gma in preparation for consolidation with
soc/intel/common opregion code. Rename init_igd_opregion()
for clarity and disambiguation with other implementations.
Change-Id: I2d0bae98f04dbe7e896ca34e15f24d29b6aa2ed6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
EvLoader is FSP module which loads and runs MMA tests.
With Change-Id Id31ddd4595e36c91ba7c888688114c4dbe4db86a, EvLoader
needs to be enabled with UPD param from coreboot.
Change-Id: Ifb860b98d6e6f21c116473a962f647e491e8546f
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/20863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Get rid of old hybrid graphics driver and use the new one.
1. Disable IGD and PEG in early romstage.
The PEG port will get disabled on devices that do not have a
discrete GPU. The power savings are around ~1Watt.
The disabled IGD does no longer waste GFX stolen memory.
2. Get rid of PCI driver
The Nvidia GPU can be handled by the generic PCI driver and allows
to use the ACPI _ROM generator for Switchable graphics.
3. Settings are stored in devicetree.
One driver for all Lenovo hybrid graphics capable devices.
4. Add support for Thinker1 GPU power handling.
Only boards that do use reference design 2012 are known to be
supported. Needs test on boards that do you use reference design 2013.
Should reduce idle power consumption when using IGD by ~5Watt.
Tested on Lenovo T430 without DGPU. PEG port is disabled.
Needs test on all devices.
Change-Id: Ibf18b75e8afe2568de8498b39a608dac8db3ba73
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Introduce a chip_driver that uses devicetree instead of Kconfig.
The new driver has the following advantages:
* No more wasted IGD GFX stolen memory
* Can be used by T500 series
* Is even run on devices that do not have a dGPU installed
* Can disable unused PEG port on devices without dGPU (and save power)
* Use devicetree instead of Kconfig options
* Support for multiple hybrid GPIO active levels
* Support for backlight control GPIO
* Support for _ROM on Optimus capable devices
The driver is split into romstage part and ramstage part.
Every mainboard has to call the driver in romstage to get the requested
GPU state. The mainboard code then has to toggle GPU power or disable
the IGD or PEG port.
The ramstage part does handle the hygrid graphics GPIO, including
optional backlight mux GPIO. Every GPIO can have it's own active level,
as defined in devicetree. Devices are no longer disabled in ramstage.
The existing hybrid graphics driver does the same configuration and
should not interfere with this commit until it has been removed.
Change-Id: Ie467f9a18b35ab3b8a523dbf51c5575db5b374a5
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
If all strings in SMBIOS table are empty, smbios_string_table_len
function should return 2, cause every table must end with "\0\0".
Also replace "eos" field type in smbios structures
from char to u8.
Change-Id: Ia3178b0030aa71e1ff11a3fd3d102942f0027eb1
Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com>
Reviewed-on: https://review.coreboot.org/20840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Ensure that the VLF bit will be cleared after a power loss event even if
the stopwatch has expired before the code to clear the bit is reached.
Change-Id: Ib2cfdabf4cd4df834395d6a102c6ae70568e71db
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
When resuming from ACPI S3 suspend, EHCI controller
may be in D3 power-management state. Bring it to D0
early so it is functional for console.
NOTE: D3hot->D0 transition was observed to reset
previous programming of PCI_COMMAND register.
Change-Id: Id177ce61926beb057fe67ba42a306d8e565d2657
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Always sanity check for EHCI class device and move
PCI function power enablement up.
Change-Id: I1eebe813fbb420738af2d572178213fc660f392a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
There is assumption of static EHCI_BAR_INDEX, try to
clean it up by bringing BAR programming at one spot.
Change-Id: Ie16090536ac5470c24720a54813015250ae2d0dd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
If TTYS0_BAUD is not configured, then by default use baudrate of 115200.
BUG=b:64030366
Change-Id: Ida4c7ae77aba5dfd4ec331e22a54ce43a91bde00
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In S3 resume, wifi is one of the wake sources.
If elog is enabled in config, then log wifi wakes in elog.
BUG=b:36992859
TEST= Build for Soraka. Do WoWlan during S3. Verify elog having update
on wake due to Wifi.
Change-Id: I7d42c5c81e0a3f7a3f94c3f6b7d2ebdf029d1aff
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/20455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This excludes files which are mostly spaces, which I felt should be
handled separately.
Change-Id: I33043a3090e2fc6e9d2fd81e8a5e46fb6cb0aa35
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
The functionality of the FAN controller is extended to provide a
lowest startup speed of the FAN. Add the parameter "fanmin" to
the fan_ctrl_t structure and initialize the value.
Change-Id: Ib2e093ed6f5fc29bbea879779eb4777eb371b937
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This reverts commit 399c022a8c.
This was merged too early. I'll repost it.
Change-Id: Iabac0aaa0a16404c885875137cf34bf64bf956f7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20686
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
New post codes are
POST_FSP_MEMORY_EXIT
POST_FSP_SILICON_EXIT
This patch will make it more consistent to debug FSP hang
and reset issues.
Bug=none
Branch=none
TEST=Build and Boot on eve
Change-Id: I93004a09c2a3a97ac9458a0f686ab42415af19fb
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The function find_fsp() parses the FSP header and returns either a valid
pointer to the FSP_INFO_HEADER or an error code. The caller of
find_fsp() only takes care about a NULL-pointer but not about a possible
error code. This leads to memory access violations in case of error when
FspTempRamInit is called.
To avoid this and to let the user know that there was an error while
parsing the FSP header show an error message and the error code.
Change-Id: I67fef0a53fb04c8ba5d18b5d4ef2fdc1aeba869e
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We don't need another level of indirection for these
hardware accesses.
Change-Id: Ic567d8272e5dd943ce19babbd7ad57ba5d86c354
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
As "var" is not a pointer but a variable there is no need to cast it to
a pointer before using the value.
Change-Id: I7f8e3ceadaa4301c50c5f5480cccab2be904aa9a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The function prototype isn't used any more, remove it.
Change-Id: Ie5bd4e4ec8f28bc0768d5427cf734ef77855a15e
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Including <fsp/gop.h> in util.h causes issues with
redeclarations when using SOC_INTEL_COMMON_GFX_OPREGION
along with FSP 1.1. Separating it out and including
directly in vbt.c has no negative side effects.
Change-Id: I2d82c2da40b067272d876929fc73b97f490146a7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.
Change-Id: Ib3a1cf04482a8f19b159c31cfb16a7b492748d91
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add a new method to restore ASLS on S3 resume.
Use new interface introduced in last commit.
Change-Id: I254683081cbaf3a5938794dcba140ac9ee07f48a
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add and use new interface to set and get GNVS' ASLB register.
To be used by Intel's gma driver to set ASLB at ACPI table
creation and to get ASLB on S3 resume.
Change-Id: If30c6b2270069783b0892774802f47406404da5f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a new method to set ASLS register that holds the
ACPI OpRegion base address.
Change-Id: I4850500ac6d58f80b0eddc81514053c87774405c
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The macro FPGA_SET_PARAM was introduced to make the setting of different
FPGA registers with the appropriate values from hwinfo more
transparent. The hwilib takes care about the size of the provided buffer
where the requested value should be stored in. The fields in hwinfo have
not always the same size as the matching registers in the FPGA. So to
avoid errors resulting in a too small buffer when calling hwilib_get_field()
the buffer is now fixed to 32 bit and will be casted to the destination
type when the value is written into the FPGA register.
Changing the field size in hwilib would be the wrong way as the defined
lengths are specified this way to be expandable in the future.
In addition the number of maximum supported temperature sensors is
increased to 8 as the FPGA now supports more.
Change-Id: I0c697106783158420708a973c3cff2be90fa4fce
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Fix undefined behavior found by clang's -Wshift-sign-overflow, find,
and source inspection. Left shifting an int where the right operand is
>= the width of the type is undefined. Add UL suffix since it's safe
for unsigned types.
Change-Id: I5240a19647c8ad59f64925f3e1c199446a886d2d
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Fix reports found by undefined behavior sanitizer. Left shifting an int
where the right operand is >= the width of the type is undefined. Add
UL suffix since it's safe for unsigned types.
Change-Id: If2d34e4f05494c17bf9b9dec113b8f6863214e56
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.
Change-Id: If80e0c4e1c9911b44853561b03aef1c741255229
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The flag FF_FreezeDis marks if this feature is disabled. For a better
readability rename freeze_mode to freeze_disable and invert the meaning
of this information.
Change-Id: I648b2392d2c8046965479511fde485a9cb934378
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
According to the datasheet the RTC needs a power rising slope of no more
than 100µs/V to ensure a correct power-on reset. If the mainboard that
hosts the RTC cannot guarantee this, a software reset sequence is needed
in the case where the battery was drained completely.
As the rising slope of the power supply depends on so many parameters
and is highly mainboard specific, refactor the initialization code to
perform a software reset every time a power loss event is recognized by
the RTC.
Change-Id: If64d672e51667523058041bd00e1e50ac047143d
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The warning -Wstack-usage= doesn't seem to exist on clang, so trying
to disable it makes the compiler unhappy about non-existent pragmas.
Catching this on gcc is good enough, so let's disable it for the clang
case
Change-Id: Ia3716a83ba41743ac1dbe73e70abd170de30d7ab
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
If RT8168_GET_MAC_FROM_VPD selected, use r8168
driver with some slight mods to check the VPD
for a mac address. Otherwise, check for mac
address in cbfs. Use default mac address if
cannot find one.
BUG=b:62090148, b:35775024
BRANCH=None
TEST=Boot to kernel. Insert mac address into VPD
vpd -s ethernet_mac=<address>
reboot the system.
Ensure we have ip address and corresponding mac
address with ifconfig.
Ensure ethernet controller shows up with lspci.
Change-Id: I7ff29de2c4c3635dc786686cc071c68d51b0f975
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/20008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This driver reinvented MAINBOARD_DO_NATIVE_VGA_INIT in a very special
way: If it wasn't set, perform native gfx init in textmode, if it was
set, perform native gfx init in linear framebuffer mode. Test for
LINEAR_FRAMEBUFFER instead and make the native gfx init optional.
Also, make Kconfig reflect the actual behaviour.
Change-Id: If20fd1f5b0f4127b426e8ff94acc61fcd4eb49af
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Commit 2e7f6cc introduced the 'no graphics init' option for
FSP 1.1 SoCs using a GOP driver to init the display, but selecting
that option while including a VBT breaks compilation for Braswell
and Skylake devices because the VBT and GOP driver are intertwined.
This patch decouples the VBT from the GOP driver execution,
allowing the 'no graphics init' option to compile (and work)
properly when CONFIG_ADD_VBT_DATA_FILE=y.
Change-Id: Ifbcf32805177c290c4781b32bbcca679bcb0c297
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20210
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
The siemens/mc_apl1 mainboard needs more functionality provided by
Siemens NC FPGA. The additional functionality contains backlight
brightness/PWM control and Dsave time for board reset.
Change-Id: I6b65b01f0d67afe598b7c005868f71b00dec56fd
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/20160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The RTC RX6110SA has several configuration options which might be
interesting to set. To make this setup independent of the driver itself
but let it still be configurable on mainboard level, add more
configuration options to the chip driver.
Change-Id: I7f8b2aa7cd001a887f271be36f655e10e60e778b
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
The new config choice is called RUN_FSP_GOP. Some things had to happen
on the road:
* Drop confusing config GOP_SUPPORT,
* Add HAVE_FSP_GOP to chipsets that support it,
* Make running the GOP an option for FSP2.0 by returning 0
in random VBT getters.
Change-Id: I92f88424004a4c0abf1f39cc02e2a146bddbcedf
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix regression introduced by commit 5c026445
(drivers/intel/wifi: Add support for generating SSDT table)
In case the regular PCI path is taken, there're no chip_ops and the code
will segfault. The bug was covered by other bugs that caused this code
to never execute.
Add NULL pointer checks and only fill in device name if one is provided.
Tested on Lenovo T430 and wifi card 8086:0085.
Change-Id: I84e804f033bcd3af1a7f76670275fdf5159d381f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
These Kconfig files had help text that was not indented further than
the 'help' keyword.
Change-Id: Ia9fdb22c0f5f0cec0c9d08aa6603b4ce8d60d9a3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/19850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The word 'coreboot' should always be written in lowercase, even at the
start of a sentence.
Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The coreboot sites support HTTPS, and requests over HTTP with SSL are
also redirected. So use the more secure URLs, which also saves a
request most of the times, as nothing needs to be redirected.
Run the command below to replace all occurences.
```
$ git grep -l -E 'http://(www.|review.|)coreboot.org'
| xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g'
```
Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/20034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
FSP_IMAGE_ID and FSP_IMAGE_REV are defined in `FspUpdVpd.h`. Check
against these to avoid mismatching definitions in coreboot and the
FSP blob.
Change-Id: Ic86229e7f0c2d0525b8a79add292c6c81a349aa6
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This typo existed in code before rewriting for using
defines and it's clearly visible after rewrite.
Previously it was writing to reserved area of GMBUS0 register,
while values are matching those of GMBUS1.
This line probably is a no-op since it's just sending the STOP
again (without an address set this time).
Change-Id: Ic85ef925c41ad01ed469f9d4f4412cbe44ca6d8e
Signed-off-by: Sebastian "Swift Geek" Grzywna <swiftgeek@gmail.com>
Reviewed-on: https://review.coreboot.org/16341
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Rename `FRAMEBUFFER_KEEP_VESA_MODE` to `LINEAR_FRAMEBUFFER` and put
it together with new `VGA_TEXT_FRAMEBUFFER` into a choice. There are
two versions of `LINEAR_FRAMEBUFFER` that differ only in the prompt
and help text (one for `HAVE_VBE_LINEAR_FRAMEBUFFER` and one for
`HAVE_LINEAR_FRAMEBUFFER`). Due to `kconfig_lint` we have to model
that with additional symbols.
Change-Id: I9144351491a14d9bb5e650c14933b646bc83fab0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/19804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If CONSOLE_SPI_FLASH config is enabled, we write the cbmem
messages to the 'CONSOLE' area in FMAP which allows us to grab the
log when we read the flash.
This is useful when you don't have usb debugging, and
UART lines are hard to find. Since a failure to boot would
require a hardware flasher anyways, we can get the log
at the same time.
This feature should only be used when no alternative is
found and only when we can't boot the system, because
excessive writes to the flash is not recommended.
This has been tested on purism/librem13 v2 and librem 15 v3 which
run Intel Skylake hardware. It has not been tested on other archs
or with a driver other than the fast_spi.
Change-Id: I74a297b94f6881d8c27cbe5168f161d8331c3df3
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/19849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Like HAVE_VGA_TEXT_FRAMEBUFFER, these are selected by graphics drivers
that support a linear framebuffer. Some related settings moved to the
drivers (i.e. for rockchip/rk3288 and nvidia/tegra124) since they are
hardcoded.
Change-Id: Iff6dac5a5f61af49456bc6312e7a376def02ab00
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/19800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Rename it to HAVE_VGA_TEXT_FRAMEBUFFER.
* Let drivers select it if they are in charge.
* Don't select it on the mainboard level if a driver handles it.
Change-Id: I2d9d09be9aa6d019e77460e69a245ad2d8cda4ea
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The driver for the RTC RX6110SA is designed to be used with I2C bus.
This patch adds the possibility to use SMBus operations to access the
RTC. For this purpose the Kconfig switch RX6110SA_USE_SMBUS is added. It
is not enabled per default so that I2C will be used. One can set this
switch on board level to use SMBus instead.
Change-Id: I4827ae2c544e8002399d94a1159acacd8176c5e9
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/19978
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Place it into new edid_fill_fb.c, and invert the logic of the Kconfig
guard (NATIVE_VGA_INIT_USE_EDID is now !NO_EDID_FILL_FB). It has to be
selected by all drivers that use MAINBOARD_DO_NATIVE_VGA_INIT but pro-
vide their own fill_lb_framebuffer() implementation.
Change-Id: I90634b835bd8e2d150b1c714328a5b2774d891bd
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
As the comment above the change indicates, and per ACPI spec,
_DSS has one argument.
Change-Id: Ic05832d412cd0c89ed3a275c4db694a9118dac28
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Now that all platforms are updated to provide spi bus map, there is no
need to keep the spi_setup_slave as a weak symbol.
BUG=b:38430839
Change-Id: I59b9bbb5303dad7ce062958a0ab8dee49a4ec1e0
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19781
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Define a new spi_flash_ops structure, move all spi flash operations to
this structure and add a pointer to this structure in struct spi_flash.
BUG=b:38330715
Change-Id: I550cc4556fc4b63ebc174a7e2fde42251fe56052
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
1. Rename __spi_flash_probe to spi_flash_generic_probe and export it
so that drivers can use it outside spi_flash.c.
2. Make southbridge intel spi driver use spi_flash_generic_probe if
spi_is_multichip returns 0.
3. Add spi_flash_probe to spi_ctrlr structure to allow platforms to
provide specialized probe functions. With this change, the specialized
spi flash probe functions are now associated with a particular spi
ctrlr structure and no longer disconnected from the spi controller.
BUG=b:38330715
Change-Id: I35f3bd8ddc5e71515df3ef0c1c4b1a68ee56bf4b
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Pointer to spi_slave structure can be passed in as const to spi flash
probe functions since the probe functions do not need to modify the
slave properties.
BUG=b:38330715
Change-Id: I956ee777c62dbb811fd6ce2aeb6ae090e1892acd
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19707
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of making all SPI drivers allocate space for a spi_flash
structure and fill it in, udpate the API to allow callers to pass in a
spi_flash structure that can be filled by the flash drivers as
required. This also cleans up the interface so that the callers can
maintain and free the space for spi_flash structure as required.
BUG=b:38330715
Change-Id: If6f1b403731466525c4690777d9b32ce778eb563
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a new member page_size to spi_flash structure so that the various
spi flash drivers can store this info in spi_flash along with the
other sizes (sector size and total size) during flash probe. This
removes the need to have {driver}_spi_flash structure in every spi
flash driver.
This is part of patch series to clean up the SPI flash and SPI driver
interface.
BUG=b:38330715
Change-Id: I0f83e52cb1041432b0b575a8ee3bd173cc038d1f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There's no users of vbe_mode_info_valid() aside from the local
compilation units. Remove the declaration and make the function
static to the current global implementers.
Change-Id: I4872ac6ad15ba6a86bba69d51a8348b9921c152d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
For some reason the "interface" for adding framebuffer information
is sitting in src/include/vbe.h while also guarding the call to
fill_lb_framebuffer() with vbe_mode_info_valid() along with some
macro if CONFIG_* for good measure.
Move the fill_lb_framebuffer() declaration to coreboot_tables.h and
provide a comment about how it should be used. Also, now that
there's no need for the notion of a global vbe_mode_info_valid()
remove it from the conditional call path of fill_lb_framebuffer().
Change-Id: Ib3ade6314624091ae70424664527a02b279d0c9b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
We have several different UART implementations of which three support a
timeout when receiving characters. In all of these three implementations
there is a bug where when the timeout is hit the last received character
will be returned instead of the needed 0.
The problem is that the timeout variable i is decremented after it has
been checked in the while-loop. That leads to the fact that when the
while-loop is aborted due to a timeout i will contain 0xffffffff and not
0. Thus in turn will fool the following if-statement leading to wrong
return value to the caller in this case. Therefore the caller will see a
received character event if there is none.
Change-Id: I23ff531a1e729e816764f1a071484c924dcb0f85
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/19731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
And don't link it. It's for ROMCC.
To make code happy that uses the ROMCC interface read_option(),
read_option_lowlevel() is ported to mc146818rtc.c along with
a message to use get_option() instead.
Change-Id: I54ea08de034766c8140b320075d36d5e811582fa
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Move drivers/storage into commonlib/storage to enable access by
libpayload and indirectly by payloads.
* Remove SD/MMC specific include files from include/device
* Remove files from drivers/storage
* Add SD/MMC specific include files to commonlib/include
* Add files to commonlib/storage
* Fix header file references
* Add subdir entry in commonlib/Makefile.inc to build the SD/MMC driver
* Add Kconfig source for commonlib/storage
* Rename *DEVICE* to *COMMONLIB*
* Rename *DRIVERS_STORAGE* to *COMMONLIB_STORAGE*
TEST=Build and run on Galileo Gen2
Change-Id: I4339e4378491db9a0da1f2dc34e1906a5ba31ad6
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/19672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Delay for a while after the switch operations to let the card recover.
TEST=Build and run on Galileo Gen2
Change-Id: I938e227a142e43ed6afda80d56af90df0bae1b05
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/19671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This driver enables the usage of the external RTC chip RX6110 SA
(http://www5.epsondevice.com/en/products/i2c/rx6110sab.html) which is
connected to the I2C bus. The I2C address of this device is fixed. One
can change parameters in the device tree so that the used setup can be
adapted to match the configuration of the device on the mainboard.
Change-Id: I1290a10c2d5ad76a317c99c8b92a013309a605d6
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/19625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Fix bug detected by coverity to handle the zero capacity case. Specific
changes:
* Reduce loop count by one to handle zero capacity case
* Use structure instead of dual arrays
* Move structures into display_capacity routine
Coverity Issues:
* 1374931
* 1374932
* 1374933
* 1374934
TEST=Build and run on Galileo Gen2
Change-Id: Ie5c96e78417b667438a00ee22c70894a00d13291
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/19643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Remove unused field in generic SD/MMC controller data structure.
TEST=Build and run on Galileo Gen2
Change-Id: I7169dca07509a6f2513d62b593742daf764010b2
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/19629
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Provide a failing get_wifi_sar_limits() to allow SAR Kconfig
options to be selected without relying on CHROMEOS which currently
has the only code to provide SAR data.
Change-Id: I1288871769014f4c4168da00952a1c563015de33
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19580
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
spi_crop_chunk is a property of the SPI controller since it depends
upon the maximum transfer size that is supported by the
controller. Also, it is possible to implement this within spi-generic
layer by obtaining following parameters from the controller:
1. max_xfer_size: Maximum transfer size supported by the controller
(Size of 0 indicates invalid size, and unlimited transfer size is
indicated by UINT32_MAX.)
2. deduct_cmd_len: Whether cmd_len needs to be deducted from the
max_xfer_size to determine max data size that can be
transferred. (This is used by the amd boards.)
Change-Id: I81c199413f879c664682088e93bfa3f91c6a46e5
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19386
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested-by: coreboot org <coreboot.org@gmail.com>
tis_close() must be called after tis_open() otherwise the locked
locality isn't released and the sessions hangs.
Tested=PC Engines APU2
Change-Id: I1a06f6a29015708e4bc1de6e6678827c28b84e98
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/19535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
device is run before drivers to generate .config and the first default
takes precedence so this override achieves nothing.
Change-Id: Ib8d333a53a0dadcc94e47ca5460b23d49cf7eb52
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
On Chrome OS systems a memory setting change is needed to be deployed
without updating the FSP blob proper. Under such conditions one needs
to trigger retrain of the memory. For ease of use provide an option,
FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS, which incorproates the SoC
and mainboard memory setting version number into the FSP version
passed to the platform. The lower 8 bits of the FSP version are the
build number which in practice is normally 0. Use those 8 bits to
include the SoC and mainboard memory settings version. When FSP,
SoC, or mainboard memory setting number is bumped a retrain will be
triggered.
BUG=b:37687843
Change-Id: I6a269dcf654be7a409045cedeea3f82eb641f1d6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19452
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The devicetree data structures have been available in more than just
ramstage and romstage. In order to provide clearer and consistent
semantics two new macros are provided:
1. DEVTREE_EARLY which is true when !ENV_RAMSTAGE
2. DEVTREE_CONST as a replacment for ROMSTAGE_CONST
The ROMSTAGE_CONST attribute is used in the source code to mark
the devicetree data structures as const in early stages even though
it's not just romstage. Therefore, rename the attribute to
DEVTREE_CONST as that's the actual usage. The only place where the
usage was not devicetree related is console_loglevel, but the same
name was used for consistency. Any stage that is not ramstage has
the const C attribute applied when DEVTREE_CONST is used.
Change-Id: Ibd51c2628dc8f68e0896974f7e4e7c8588d333ed
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19333
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The SD/MMC support is broken into several pieces. There are three main
data structures:
* sdhci_ctrlr - This is SDHCI controller specific and defined in
include/device/sdhci.h
* sd_mmc_ctrlr - This contains generic controller management data and
defined in include/device/sd_mmc_ctrlr.h
* storage_media - This contains the flash storage device management data
and is defined in include/device/storage.h
The SD/MMC driver consists of several components:
* SDHCI controller code
* bouncebuf.c
* bouncebuf.h
* pci_sdhci.c
* sdhci.c
* sdhci.h
* sdhci_adma.c
* sdhci_display.c
* Flash storage device support
* mmc.c
* mmc.h
* sd.c
* sd_mmc.c
* sd_mmc.h
* storage.c
* storage.h
* storage_erase.c
* storage_write.c
Kconfig values enable various portions of the controller and storage
drivers to be built to reduce the overall size of what is included in
the final image.
Full read/write/erase operations are provided for those platforms which
want to take advantage. It is also possible to build the driver to
perform initialization only. By default, this driver is not included in
any platform, platforms must specifically select DRIVERS_STORAGE to add
the SD/MMC support.
After this patch is reviewed and merged, there are some additional
patches:
* Common CAR storage area - Use a predefined region of CAR to pass data
structures between bootblock through to romstage. This allows early
stages to preform the SD/MMC device initialization and later stages
to use the SD/MMC device without further initialization. The example
code initializes the SD/MMC device in bootblock and uses the SD/MMC
device in romstage without further initialization.
* CBMEM ID - Add a CBMEM ID value for the data structures so that they
may be passed from romstage to ramstage and eventually the payload.
The example uses the SD/MMC device in ramstage without further
initialization.
* Move the SD/MMC driver into commonlib
* Have libpayload build the SD/MMC driver from commonlib. The intent
is to pass the controller state to libpayload so that the SD/MMC
device can be used without further initialization.
* On some platforms, have depthcharge use the commonlib SD/MMC driver
History:
Copy the SD/MMC driver from depthcharge revision eb583fa8 into coreboot
and make the following changes:
* Removed #include "config.h" from mmc.c, allow the lint tests to pass.
* Move include files from drivers/storage into include/device.
* Rename mmc.h to storage.h.
* Add the Kconfig and Makefile and make edits to get the code to build.
* Add support to initialize a PCI controller.
* Fix formatting issues detected by checkpatch.
* Fix data flow issues detected by checkpatch.
* Add the missing voltage (MMC_VDD_35_36) into the voltage mask.
* Rename the macros mmc_debug, mmc_trace and mmc_error to sd_mmc_*.
* Replace printf with sd_mmc_error.
* Add sdhc_debug, sdhc_trace and sd_error macros.
* Add Kconfig values to enable storage device debugging and tracing.
* Add tracing and debug support to the SDHCI driver.
* Allow SOC to override more controller features.
* Split out ADMA support.
* Move 1V8 support into SOC routine.
* Move HS400 support into SOC routine.
* Rework clock handling.
* Change all controller references to use ctrlr.
* Update the voltage handling.
* Update modes of operation.
* Move DMA fields into MmcCtrlr.
* Update bus width support.
* Change MMC_TIMING_* to BUS_TIMING_*.
* Rename MMC_MODE_ to DRVR_CAP.
* Move quirks into ctrlr->caps.
* Associate removeable with the controller.
* Statically allocate MmcMedia.
* Replace the SdhciHost structure with the MmcCtrlr structure.
* Split the code to support other SD/MMC controllers.
* Split out erase and write support.
* Update the code to be more consistent with the coreboot coding style.
* Only expose calling APIs.
* Divide up mmc.c into 4 modules: MMC, SD, storage card, common code.
* Update debug and error messages.
* Add partition support.
* Display clock frequencies once in MHz.
* Remove mmc_send_cmd, use ctrlr->send_cmd instead.
* Handle error from sd_send_op_cond.
* Allow mainboard to control delays around CMD 0.
* Support command logging.
* Mainboard may set delay after SD/MMC command.
* Display serial number with sd_mmc_trace.
* Remove cmd set parameter from mmc_switch.
* Display errors for timeout and comm errors.
* Add LED support.
* Move 64bit DMA flag into ctrlr->caps.
* Rework PIO transfer routine.
* Add HS200 bus tuning.
* Add support for HS400.
* Use same format for HS400, HS200 and HS52.
* Reduce storage_media structure size
* Add routine to update code pointers
* Add display of storage setup
* Display controller setup
TEST=Build and run on Reef and Galileo Gen2
Change-Id: I9b5f9db1e27833e4ce4a97ad4f5ef3a46f64f2a2
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/19208
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The vendor.irq field was originally intended for use as the TPM 1.2
"command complete" interrupt. However, all actual coreboot tpm drivers
and hardware use the vendor.status method of checking command completion
instead, and this irq field is not used.
Let's just remove this unused functionality to simplify the code.
BRANCH=none
BUG=b:36786804
TEST=Boot reef w/ serial enabled firmware, verify verstage sees
"cr50 TPM" and does not complain about lack of tis_plat_irq_status().
TEST=Boot eve w/ serial enabled firmware, verify verstage sees
"cr50 TPM" and does not complain about lack of tis_plat_irq_status().
Change-Id: I994c5bfbd18124af9cb81d9684117af766ab0124
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19396
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
The Cr50 TPM uses an IRQ to provide a "status" signal used for hand-shaking
the reception of commands. Real IRQs are not supported in firmware,
however firmware can still poll interrupt status registers for the same
effect.
Commit 94cc485338 ("drivers/i2c/tpm/cr50: Support interrupts for status")
added support for the Cr50 driver on X86 platforms to use a KConfig file
to supply an IRQ which it would poll using acpi_get_gpe. If the IRQ is
not supplied, the Cr50 driver inserts a 20 ms wait.
Unfortunately this doesn't work so well when using the i2c connected Cr50
on ARM platforms. Luckily, a more generic implementation to allow a
mainboard to supply a Cr50 IRQ status polling function was solved for SPI
connected Cr50s by commit 19e3d335bd ("drivers/spi/tpm: using tpm irq to
sync tpm transaction").
Let's refactor the i2c c50 driver to use this same approach, and change
eve and reef boards to make use of DRIVER_TPM_TIS_ACPI_INTERRUPT for
specifying the TPM flow control interrupt.
This essentially reverts these two commits:
48f708d199 drivers/i2c/tpm/cr50: Initialize IRQ status handler before probe
94cc485338 drivers/i2c/tpm/cr50: Support interrupts for status
And ports this commit to i2c/tpm/cr50:
19e3d335bd drivers/spi/tpm: using tpm irq to sync tpm transaction
As a side effect the tpm_vendor_specific IRQ field goes back to its
original usage as the "TPM 1.2 command complete" interrupt, instead of
being repurposed to hold the flow control IRQ.
BRANCH=none
BUG=b:36786804
TEST=Boot reef w/ serial enabled firmware, verify verstage sees
"cr50 TPM" and does not complain about lack of tis_plat_irq_status().
TEST=Boot eve w/ serial enabled firmware, verify verstage sees
"cr50 TPM" and does not complain about lack of tis_plat_irq_status().
Change-Id: I004329eae1d8aabda51c46b8504bf210484782b4
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/19363
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
MAINBOARD_HAS_SPI_TPM_CR50 describes a capability of the board and SPI_TPM
is only on if we actually want to compile in the TPM code. For example,
in src/drivers/i2c/tpm/Kconfig MAINBOARD_HAS_I2C_TPM_CR50 also doesn't
depend on SPI_TPM.
This problem manifests itself as the following build issue when building
with MAINBOARD_HAS_I2C_TPM_CR50 but without an explict "select TPM2":
src/Kconfig:296:error: recursive dependency detected!
src/Kconfig:296: symbol MAINBOARD_HAS_TPM2 is selected by MAINBOARD_HAS_TPM_CR50
src/Kconfig:408: symbol MAINBOARD_HAS_TPM_CR50 depends on MAINBOARD_HAS_SPI_TPM_CR50
src/drivers/spi/tpm/Kconfig:15: symbol MAINBOARD_HAS_SPI_TPM_CR50 depends on SPI_TPM
src/drivers/spi/tpm/Kconfig:1: symbol SPI_TPM depends on TPM2
src/Kconfig:396: symbol TPM2 is selected by MAINBOARD_HAS_TPM2
MAINBOARD_HAS_SPI_TPM_CR50 shouldn't depend on SPI_TPM.
BRANCH=none
BUG=b:36786804
TEST=Boot rowan w/ serial enabled, verify coreboot and depthcharge are
configured to use IRQ flow control when talking to the Cr50 TPM.
Change-Id: I0cb3f6d3aa4159bad563a6a4b006d7f4825e04b4
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Suggested-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19411
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use spi_setup_slave to fill up the spi_slave structure with
pointer to spi_ctrlr structure which can then be used to perform all
spi operations.
Change-Id: I2804ed1e85402426a654352e1ceaf0993546cd8b
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19385
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Depend on I2C_TPM to prevent showing the menu entry on systems
that do not have an I2C TPM installed.
Change-Id: I7cd647c9c7e9721eab96ab64b844a882f156ee68
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19374
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
TPM ACPI entries are automatically generated, and the old static
TPM ASL file is obsolete. Remove the reference to this obsolete
static and empty ASL file.
Delete src/drivers/pc80/tpm/acpi/tpm.asl.
Change-Id: I6163e6d59c53117ecbbbb0a6838101abb468de36
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19291
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add SSDT generator for MIPI CSI camera to create ACPI objects
used by the Intel kernel drivers.
* SSDB: Sensor specific database for camera sensor.
* PWDB: Power database for all the camera devices.
* CAMD: ACPI object to specify the camera device type.
BUG=b:36580624
BRANCH=none
TEST=Build and boot poppy. Dump and verify that the generated SSDT table
has the required entries.
Change-Id: Ief9e56d12b64081897613bf1c7abcdf915470b99
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/18967
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
We're already reading the RTC whenever we file an event, we might as
well print out the value at that time. Having a few RTC timestamps in
the firmware log makes it easier to correlate that part of the log to a
particular boot once we start having multiple boots in the log.
Change-Id: I750dd18aa2c43c95b8c1fbb8f404c1e3a77bec73
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19305
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
1. Move common TIS macros to include/tpm.h.
2. Use common TIS macros while referring to status and access registers.
3. Add a new function claim_locality to properly check for required
access bits and claim locality 0.
BUG=b:36873582
Change-Id: I11bf3e8b6e1f50b7868c9fe4394a858488367287
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19213
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
There is only one user for spi_get_config i.e. SPI ACPI. Also, the
values provided by spi_get_config are constant for now. Thus, get rid
of the spi_get_config call and fill in these constant values in SPI
ACPI code itself. If there is a need in the future to change these,
appropriate device-tree configs can be added.
BUG=b:36873582
Change-Id: Ied38e2670784ee3317bb12e542666c224bd9e819
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19203
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Some renamings force us to update our code:
* Scan_Ports() moved into a new package Display_Probing.
* Ports Digital[123] are called HDMI[123] now (finally!).
* `Configs_Type` became `Pipe_Configs`, `Config_Index` `Pipe_Index`.
Other noteworthy changes in libgfxinit:
* libgfxinit now knows about ports that share pins (e.g. HDMI1 and
DP1) and refuses to enable any of them if both are connected
(which is physically possible on certain ThinkPad docks).
* Major refactoring of the high-level GMA code.
Change-Id: I0ac376c6a3da997fa4a23054198819ca664b8bf0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/18770
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
In order to be able to use SPI TPM on x86, allow TPM_SPI to be used
with PC80_SYSTEM.
BUG=b:35583330
Change-Id: Ibe626a192d45cf2624368db42d369202a4003123
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19093
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
1. Use proper CAR semantics for global/static variables.
2. Use spi_* functions directly instead of using a global structure to
store pointers to those functions.
BUG=b:36873582
Change-Id: I1fc52ab797ef0cbd3793a387d68198efc5dde58c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19114
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
BUG=b:35647967
TEST=boot from bob
Change-Id: Ib64107b17fb6e93dbe626ce92f3bc9da8b84784e
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/452284
Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19113
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
BUG=b:35775002
TEST=boot from bob
Change-Id: I6324f3c02da55a8527f085ba463cbb1f4fb5dc2e
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/452283
Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19112
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
The tis.c module is needlessly copying data to/from a 1260 byte
buffer on the stack. Each device's transport implementation (cr50.c
or tpm.c) maintains its own buffer, if needed, for framing purposes.
Therefore, remove the duplicated buffer.
BUG=b:36598499
Change-Id: I478fb57cb65509b5d74bdd871f1a231f8080bc2f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19061
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
The spi tis_sendrecv() implementation was always returning success
for all transactions. Correct this by returning -1 on error when
tpm2_process_command() returns 0 since that's its current failure
return code.
BUG=b:36598499
Change-Id: I8bfb5a09198ae4c293330e770271773a185d5061
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19058
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
The tpm_info object is a global, but its symbol does not need to
be exposed to the world as its only used within tpm.c.
BUG=b:36598499
Change-Id: Idded3dad8d0d1c3535bddfb359009210d3439703
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19057
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
In the case of start_transaction() failing the chip select is never
deasserted. Correct that by deasserting the chip select when
start_transaction() fails.
BUG=b:36598499
Change-Id: I2c5200085eb357259edab39c1a0fa7b1d81ba7b2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19056
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
In builds without CONFIG_VBOOT_SEPARATE_VERSTAGE, verstage files are
linked directly into the bootblock or the romstage. However, they're
still compiled with a separate "libverstage" source file class, linked
into an intermediate library and then linked into the final destination
stage.
There is no obvious benefit to doing it this way and it's unclear why it
was chosen in the first place... there are, however, obvious
disadvantages: it can result in code that is used by both libverstage
and the host stage to occur twice in the output binary. It also means
that libverstage files have their separate compiler flags that are not
necessarily aligned with the host stage, which can lead to weird effects
like <rules.h> macros not being set the way you would expect. In fact,
VBOOT_STARTS_IN_ROMSTAGE configurations are currently broken on x86
because their libverstage code that gets compiled into the romstage sets
ENV_VERSTAGE, but CAR migration code expects all ENV_VERSTAGE code to
run pre-migration.
This patch resolves these problems by removing the separate library.
There is no more difference between the 'verstage' and 'libverstage'
classes, and the source files added to them are just treated the same
way a bootblock or romstage source files in configurations where the
verstage is linked into either of these respective stages (allowing for
the normal object code deduplication and causing those files to be
compiled with the same flags as the host stage's files).
Tested this whole series by booting a Kevin, an Elm (both with and
without SEPARATE_VERSTAGE) and a Falco in normal and recovery mode.
Change-Id: I6bb84a9bf1cd54f2e02ca1f665740a9c88d88df4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18302
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Create sample model for common car init and teardown programming.
TEST=Booted Reef, KCRD/EVE, GLKRVP with CAR_CQOS, CAR_NEM_ENHANCED
and CAR_NEM configs till post code 0x2a.
Change-Id: Iffd0c3e3ca81a3d283d5f1da115222a222e6b157
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18381
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This reuses some of gm45 code to set up the panel.
Panel start and stop delays and pwm frequency can now be set in
devicetree.
Linux does not make the difference between 945gm and gm45
for panel delays, so it is safe to assume the semantics of those
registers are the same.
The core display clock is computed according to "Mobile Intel® 945
Express Chipset Family" Datasheet.
This selects Legacy backlight mode since most targets have some smm
code that rely on this.
This sets the same backlight frequency as vendor bios on Thinkpad X60
and T60.
A default of 180Hz is selected for the PWM frequency if it is not
defined in the devicetree, this might be annoying for displays that
are LED backlit, but is a safe value for CCFL backlit displays.
Change-Id: I1c47b68eecc19624ee534598c22da183bc89425d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18141
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Fix the following error and warnings detected by checkpatch.pl:
ERROR: "foo * bar" should be "foo *bar"
WARNING: line over 80 characters
WARNING: else is not generally useful after a break or return
WARNING: braces {} are not necessary for single statement blocks
WARNING: suspect code indent for conditional statements (16, 32)
WARNING: Comparisons should place the constant on the right side of the test
TEST=Build and run on Galileo Gen2
Change-Id: I9f56c0b0e3baf84989411e4a4b98f935725c013f
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18886
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Tristan Corrick