GNUBoot/coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
18306 commits 1 branch 29 tags 216 MiB
Commit graph

13 commits

Author SHA1 Message Date
Shaunak Saha
cd9e1e423f intel/apollolake: Update gnvs for dptf 
This patch updates dptf variable in gnvs based on device
configuration by reading the device tree structure.

BUG=chrome-os-partner:53096
TEST=Verify that the thermal zones are enumerated
       under /sys/class/thermal in Amenia and Reef board.
       Navigate to /sys/class/thermal, and verify that a
       thermal zone of type TCPU exists there.

Change-Id: I8ab34cdc94d8cdc840b02347569a9f07688e92cd
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15620
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2016-07-28 20:13:34 +02:00
Hannah Williams
6516422034 soc/apollolake: Populate fields in FADT to enable\disable SCI 
This will allow kernel to trigger a APM SMI to enable\disable SCI

Change-Id: I1be79b7a3082c23fbaf204eff55360c46458e325
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/15347
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
 2016-06-28 15:56:47 +02:00
Furquan Shaikh
d01f5a01e6 intel/apollolake: Add CBMEM console to GNVS 
CBMEM console stores all the console logs in CBMEM. Address of this
location in CBMEM where console logs are stored needs to be passed up to
OS using GNVS.

1. Add CBMC to GNVS fields in globalnvs.asl
2. Add cbmc member to global_nvs_t structure in nvs.h
3. Initialize gnvs->cbmc to address of cbmem console

BUG=chrome-os-partner:54342

Change-Id: Idcd4573e626fa433c1623bdcbe29921de64539b2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15177
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
 2016-06-15 17:56:52 +02:00
Aaron Durbin
1ee6f0bdc8 soc/intel/apollolake: save GNVS pointer to SMM handler 
Like other boards there will likely be information needed from
GNVS in the SMM handler. Therefore, it's important that the point
is stashed accordingly.

BUG=chrome-os-partner:54275
TEST=Noted GNVS messages from SMM console on reef.

Change-Id: If12b69731330a1e0af7f8fe880635e5ffd02d715
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15152
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2016-06-12 12:55:04 +02:00
Hannah Williams
0f61da8582 soc/apollolake: Add SOC specific c-state table 
Please refer Apollolake BIOS Writers Guide

Change-Id: I5f82cdc4b34a53b5184ef1e918cae15a1df6cc5e
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/15051
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
 2016-06-08 22:31:27 +02:00
Aaron Durbin
c3ee3f6d7e soc/intel/apollolake: use common FADT infrastructure 
Instead of having the mainboards duplicate the same boilerplate
code utilize the common FADT infrastructure to reduce duplication.

Change-Id: If824619fd619433974e588050a933d2c19b97ec8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14779
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2016-05-12 20:06:06 +02:00
Lance Zhao
1bd0c0c497 soc/intel/apollolake: Add handling of GNVS ACPI entry for CHROMEOS builds 
Add chromeos required GNVS feature. The GNVS table stays in both CBMEM
and ACPI DSDT tables.

Change-Id: I4db0eb18d2de62917a94704318a7896c04e4777f
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14471
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2016-04-28 05:47:30 +02:00
Martin Roth
ebabfadcec soc/intel: Update license headers 
Update all of the license headers to make sure they are compliant
with coreboot's license header policy.

Change-Id: I151d058615290e528d9d1738c17804f6b9cc8dce
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14321
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
 2016-04-14 16:54:33 +02:00
Zhao, Lijian
30461a9197 soc/apollolake/acpi: Fill ACPI HPET table 
HPET table is required to report integrated HPET timer to kernel.
Without HPET table added,Linux kernel will panic when loading timer
driver.

Change-Id: I7368bc29f4e03d5882dcfc4a770fa7bfbc6c26a0
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/13374
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
 2016-04-11 18:22:30 +02:00
Lance Zhao
2fc82d699d soc/apollolake/acpi: Fill in ACPI MADT table 
ACPI MADT tables required to describe the multiprocessor interrupt 
routing. Apollolake SOC also have the interrupt override table like
other x86 silicons.

Change-Id: I85976e227963c950aad4476d68581b96e1090559
Signed-off-by: Lance Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/13373
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2016-04-11 18:19:34 +02:00
Lance Zhao
2c34e3155c soc/apollolake/acpi: Fill ACPI MCFG table 
ACPI MCFG table is required for OS to support Enhanced
Configuration Space Access.Apollolake will only support
1 PCI Segment Group, so all the pci bus number from 0
to 0xff will belong to that group.

Change-Id: I3a680eb9c83290cd531159d7e796382a132cd283
Signed-off-by: Lance Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/13375
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2016-04-11 16:28:50 +02:00
Lance Zhao
e904c7cdea soc/intel/apollolake: Fill ACPI FADT table 
Fill the ACPI FADT table base on apollolake SOC definition.

Change-Id: Ib7226a3b130f14810dc2af5ca484cef58f477063
Signed-off-by: Lance Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/13352
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
 2016-04-05 23:00:17 +02:00
Lance Zhao
f51b12735d soc/apollolake: Add skeleton ACPI entry 
Change-Id: Ib127af5392ca2b349480f5b21fad2186b444d7e6
Signed-off-by: Lance Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/13348
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2016-03-21 23:14:09 +01:00