Commit graph

18 commits

Author SHA1 Message Date
Angel Pons
408d1dac9e mb/**/dsdt.asl: Remove outdated sleepstates.asl comment
Previously, each Intel chipset had its own sleepstates.asl file.
However, this is no longer the case, so drop these comments.

Change-Id: I50aba6e74f41e2fa498375b5eb6b7e993d06bcac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-12-31 15:16:57 +00:00
Angel Pons
0142d441c6 mb/**/dsdt.asl: Remove "Some generic macros" comment
It provides no useful information, so it might as well vanish.

Change-Id: I0df6f4639a16058486c2e2d40fe4067d65670731
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-12-21 11:38:16 +00:00
Frans Hendriks
e2291f5ad4 mb/{facebook/portwell}: Remove empty onboard.h
Defines in onboard.h are moved to other files.
Remove this empty and unused file.

BUG=N/A
TEST=build

Change-Id: Ide10b352eadcffad2d4221865124f64466af5a1c
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37615
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-11 11:44:11 +00:00
Frans Hendriks
a7ddf4cdb0 mb/portwell/m107/fadt.c Use get_apic_table_revision
Fixed value of ACPI_FADT_REV_ACPI_2_0 is replaced by
get_acpi_table_revision().

BUG=N/A
TEST=build

Change-Id: I95b0d886b73f94bc880c0e3e7d512211d2d33e21
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-12-11 11:36:58 +00:00
Frans Hendriks
106abb82fe mb/portwell/m107/acpi/superio.asl: Correct indent
Remove the additional tabs on all lines.

BUG=N/A
TEST=build

Change-Id: I02b1314fe2ae89da3659b198c12df9c30c8a039d
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-12-11 11:36:24 +00:00
Frans Hendriks
c1c5354e45 mb/{facebook/portwell}: Define SDCARD_CD in dsdt.asl
SDCARD_CD is defined in onboard.h but required in ASL only, move this
define to dsdt.asl.
Removed the onboard.h file from the ASL files that don use it.

BUG=N/A
TEST=build

Change-Id: I35b75e0ae2e2bc4ce143aaec6df6016774676095
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-12-11 11:36:08 +00:00
Frans Hendriks
8d98d80e53 mb/portwell/m107/devicetree.cb: Use IGD_MEMSIZE_32MB
Make code more readable.
Replace 1 by IGD_MEMSIZE_32MB for PcdIgdDvmtS0PreAlloc.

BUG=N/A
TEST=build

Change-Id: I5d84e575935e9e60610e1805e1402f290672b114
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-12-11 11:35:21 +00:00
Frans Hendriks
18aa6fe261 mb/{facebook/portwell}: Remove ITE8258_CMD_PORT
ITE8258_CMD_PORT is used in com_init.c only.
Replace ITE8258_CMD_PORT by fixed value in the c file.
ITE8258_DATA_PORT is removed as this isn't used.

BUG=N/A
TEST=build

Change-Id: I401da3f127db9e65763fd8d115eb274fbadbefbe
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-12-10 11:19:30 +00:00
Arthur Heymans
68b6eb78d2 soc/intel/braswell: Use common sb code for SPI lockdown configuration
This removes the weakly linked function to configure the SPI lockdown.

Change-Id: I1e7be41a9470b37ad954d3120a67fc4d93633113
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36007
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-05 17:59:29 +00:00
Arthur Heymans
689256797e Drop superfluous C_ENVIRONMENT_BOOTBLOCK checks
Some guarding is not needed because the linker drops the code,
other guarding is not needed because all platforms using the code now
have C_ENVIRONMENT_BOOTBLOCK.

Change-Id: I3b1a94e709aa291e1156c854874d7bf461981f32
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-11-25 09:17:14 +00:00
Patrick Georgi
0bb83469ed Kconfig: comply to Linux 5.3's Kconfig language rules
Kconfig became stricter on what it accepts, so accomodate before
updating to a new release.

Change-Id: I92a9e9bf0d557a7532ba533cd7776c48f2488f91
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-11-23 20:09:56 +00:00
Arthur Heymans
12440ce63e drivers/intel/fsp1_1: Fake microcode update to make FSP happy
The FSP loops through microcode updates and at the end checks if
the microcode revision is not zero. Since we update the microcode
before loading FSP, this is the case and a fake microcode can be
passed to the FSP.

The advantage is that the Kconfig symbols to specify the location and
the size of the microcode blob can be dropped.

Change-Id: I63cfb7b19e9795da85566733fb4c1ff989e85d03
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36255
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-10 22:57:55 +00:00
Wim Vervoorn
44874482fe mb/portwell/m107: Remove Intel wifi disable
The Intel wifi drivers were disabled by default. This should not
be done here as the baseboard defines if this present or not.

BUG=N/A
TEST=build

Change-Id: I364a821f8387d580b1fbfb7cf77b32a3a6dceebb
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36503
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-01 11:43:27 +00:00
Wim Vervoorn
f6671a89c5 mb/portwell/m107: Add Kingston memory support
Add support for board revision 1.3 containing Kingston memory.

BUG=N/A
TEST=tested on portwell m107 module

Change-Id: I436698ee079952580c764e840ee0ad2e18ea8d3b
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-11-01 11:43:05 +00:00
Elyes HAOUAS
d624e3997a (acpi) superio.asl: Drop wrong _ADR objects
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID
object or an _ADR object, but should not contain both."

Found-by: ACPICA 20191018
Change-Id: Ic0bcaa37ac017ab61e1fb4e78d3c7dfbbcc0899d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-10-24 15:52:05 +00:00
Arthur Heymans
2d7aa11308 mb/portwell/m107: Clean up unused Kconfig symbols
Change-Id: I9714b197ff0d1af834aa29f96b33809396f0b203
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36196
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-22 12:56:54 +00:00
Himanshu Sahdev
15062533fc acpi_table_header: Replace hard-coded revision via macro and function
Minimize use of hard-coded value for acpi_table_header->revision to soft
code. Replace with macro defined in arch/acpi.h for FADT and with the
get_acpi_table_revision function for SSDT.

Change-Id: I99e59afc1a87203499d2da6dedaedfa643ca7eac
Signed-off-by: Sourabh Kashyap <Sourabhka@hcl.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35539
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-04 19:45:06 +00:00
Frans Hendriks
ed52e3dd9c mainboard/portwell/m107: Do initial mainboard commit
Initial support for Portwell PQ7-M107 (Q7) module.
Code based on Intel Strago mainboard.

BUG=N/A
TEST=booting SeaBIOS and Linux 4.20 kernel on PQ7-M107

Change-Id: I7d3173fdcf881f894a75cd9798ba173b425d4e62
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-07-17 14:21:52 +00:00