Commit Graph

39466 Commits

Author SHA1 Message Date
Matt DeVillier d0e1db835a mb/google/lindar: Fix building with CONFIG_CHROMEOS unset
Make CHROMEOS_DSM_CALIB depend on CHROMEOS, rather than force-select it.

Change-Id: I4c3fd04ec00e0787381c58810938dd48f414635c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-07 08:16:27 +00:00
Matt DeVillier f3419b29b7 soc/intel/common/cse: Drop dependency on CHROMEOS for SOC_INTEL_CSE_LITE_SKU
The CSE lite SKU has 2 CSE firmware boot partitions vs 3 for the "normal"
SKU; this has nothing to do with building for ChromeOS or not, and by
having this dependency, boards with select the CSE lite SKU are unable to
build with CONFIG_CHROMEOS unset due to Kconfig dependency issues.

Test: build google/wyvern with CONFIG_CHROMEOS not set.

Change-Id: I6959f35e1285b2fab7ea1f83a5ccfcb065c12397
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-07 08:16:12 +00:00
Tony Huang 8a1e2e1765 mb/google/puff/var/dooly: Config I2C0 SerialIoDevMode
I2C0 has amplifier connection, thus set it to PchSerialIoPci.

BUG=b:170273526
BRANCH=puff
TEST=Build and check PCH serial IO config is set I2C0 to Mode 1

Change-Id: I9540f7b5538d37de53bcf43531488d714874a565
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
2021-01-07 08:15:28 +00:00
Michael Niewöhner 6b284569a8 cpu/intel: add PC10 residency counter MSR
This MSR will be used in the follow-up changes.

Change-Id: Ia6f74861502d4a9f872b2bbbab2e5f1925a14c4d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49044
Reviewed-by: Lance Zhao
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-07 08:15:04 +00:00
Maxim Polyakov 41a36a3d3e mb/razer/blade_stealth_kbl: Remove comments with pad functions
Remove these comments, because it does not contain useful information
that helps to understand the circuit, which we do not have.

Tested with BUILD_TIMELESS=1, Razer Blade Stealth, remains identical.

Change-Id: I8a8450493ceebe97ac03b4134adc46b01328a1b6
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-07 08:13:48 +00:00
Ren Kuo 64ab189a65 mb/google/dedede/var/magolor: modify raydium touch screen
modify raydium touch screen power on timing to meet requirement

BUG=b:174280232
TEST=build firmware and measured the timing

Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: I3ecc9d8e21f8c76e9e96cf050dcde83c3c4f4ea7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48971
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-07 08:13:12 +00:00
Tim Chen ed47332ff6 mb/google/dedede/var/metaknight: Configure I2C high and low times
Configure the I2C bus high and low times for port0,2 and 4 I2C buses.

BUG=b:176519792
TEST=Measured the I2C bus frequency lower than 400 KHz.

Change-Id: Ieed038c93f0972c06cb3fa311742dd22ac2e875d
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-07 08:12:43 +00:00
Dtrain Hsu cd6998b810 mb/google/dedede/var/madoo: Update Goodix touchscreen power sequence
Follow Goodix datasheet (GT7375 Programming Guide_Rev.0.1.pdf and
GT7375P Programming Guide_Rev.0.6.pdf) to tune touchscreen power sequence.
Increase reset_delay_ms from 120ms to 180ms.

BUG=b:176511605
BRANCH=dedede
TEST=Build and boot Madoo to OS

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Iae35e4da31a3c3afd24c7daf81a5a3e762acd3b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-01-07 08:12:30 +00:00
Stanley Wu 2f8df88ced mb/google/dedede/var/boten: Configure I2C high and low time
Configure the I2C bus high and low time for all enabled I2C buses.

BUG=b:168783630
TEST=Measured the I2C bus frequency reduce to 387 KHz.

Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I37403dd3ac3c9320398207d2111e1ddb73d6a130
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-07 08:12:06 +00:00
Tony Huang 50dc0633db mb/google/dedede/var/lantis: Config I2C high and low time for touchscreen/audio
Config I2C high / low time in device tree to ensure I2C
CLK runs accurately at I2C_SPEED_FAST (400 kHz).

These tuning value is applied from touchpad as a base line,
and EE measured touchscreen/audio runs at 399/396.7kHz after tuning.

BUG=b:173709409
BRANCH=dedede
TEST=Build and check after tuning I2C clock is under 400kHz

Change-Id: I970d69e6361d7cf6fcfc4e5b0b3c5fbfa885367c
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-07 05:32:56 +00:00
Tony Huang 3564c739a2 mb/google/dedede/var/lantis: Config I2C high and low time for touchpad
BUG=b:173709409
BRANCH=dedede
TEST=EE measured result is 390.8kHZ

Change-Id: I7a6475fd29d4c9f8efa78a42a112b5565511b939
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-01-07 05:31:57 +00:00
Frank Wu f8d7374bab mb/google/zork/var/vilboz: Fix Goodix touchscreen power sequence
According Goodix GT7375P Programming Guide_Rev.0.6, increase the stop
delay time from 100 ms to 160 ms.
The power sequence is not met with the latest guide_rev.0.6.

BUG=b:176270381
BRANCH=zork
TEST=Confirm the measured waveform complies with Goodix touchscreen spec.

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I687ffa2eb13a9ddecb3045c5e1540b94417329ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48907
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-07 03:57:29 +00:00
Yidi Lin 54f8b9ee74 soc/mediatek: rtc: Use `bool` as return type
BUG=b:176307061
TEST=emerge-asurada coreboot; emerge-kukui coreboot emerge-oak coreboot
     boot to shell on Asurada

Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Id31fa04edc2920c1767d9f08ab7af0ab4a15bc24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-01-07 02:02:51 +00:00
Felix Singer 9990a17200 soc/intel/broadwell: Move MAX_CPUS from mb to SoC
All Broadwell boards use 8 for MAX_CPUS, so this option can be factored
out into SoC Kconfig.

Change-Id: I311b95ea75a7c6b76b32c7197a0cec86db644234
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49122
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-06 19:34:51 +00:00
Felix Singer 9a6a18e33b soc/intel/skylake: Move MAX_CPUS from mb to SoC
Configure MAX_CPUS in SoC Kconfig with 8 as default value and remove it
from every mainboard where 8 is used.

Change-Id: I825625bf842e8cd22dada9a508a7176e5cc2ea57
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49105
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-06 19:34:20 +00:00
Angel Pons b9e77f6d6b mb/intel/wtm2/Kconfig: Limit MAX_CPUS to 8
Haswell and Broadwell have at most 8 threads.

Change-Id: Idcccf22addb6e15d7c55b9816141af47d6186cca
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46952
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-06 19:34:04 +00:00
David Wu 6df0c67c09 mb/google/volteer/var/voema: Update Aux settings for Port 0
On Voema port 0 (MB PORT) does not have a retimer so the port needs
to be configured for the SOC to handle Aux orientation flipping.

BUG=b:176462544
TEST=tested on voema

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I3d31a5b848f56126f8ffe2babb29085471e8224f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2021-01-06 18:31:55 +00:00
Raul E Rangel 3b55a8d676 mb/amd/mandolin/mainboard: Remove unused pirq_data
This table was wrong. It's also produced by the SoC code now.

BUG=b:170595019
TEST=None

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifcc406591abf88ebdb5ed972614c3a6901721bac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-06 17:36:20 +00:00
Raul E Rangel ead253a366 mb/google/zork/mainboard: Remove unused pirq_data
This table was wrong. It's also produced by the SoC code now.

BUG=b:170595019
TEST=Verify PCI IRQ: log messages

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I008b6896064672f9d45a8e12f6cfc62c0cc41536
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-06 17:33:16 +00:00
Raul E Rangel 4e80fae236 soc/amd/picasso: Correctly populate the PCI interrupt line register
The PCI interrupt line registers are used as a last resort if routing
can't be fetched from either ACPI or the MPTable. This change correctly
sets the registers. It overrides the pirq_data set by the mainboards
since the routing is fixed in AGESA.

BUG=b:170595019
TEST=Boot ezkinil with `pci=nomsi,noacpi amd_iommu=off noapic`
Verified all PCI peripherals are still functional.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If5d4d8f613c8d0fa9b43cefa804824681c3410d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-01-06 17:26:46 +00:00
Raul E Rangel 2f5fd11474 soc/amd/picasso: Fix ACPI PCI routing table
The original routing table did not handle all 8 INTx interrupts.
Additionally it also didn't take the swizzling into account.

Now that we know how AGESA programs the routing table we can correctly
generate it.

We still route the PCI interrupts through the FCH IOAPIC. A follow up
will have the GNB IOAPIC handle the PCI interrupts.

There is still work to be done to fix the legacy PCI_IRQ register for
each PCI device. We can then remove the mainboard_pirq_data from each
mainboard.

BUG=b:170595019
TEST=Used ezkinil
Boot kernel with `pci=nomsi amd_iommu=off noapic` and
`pci=nomsi amd_iommu=off` then verified system
was usable and verified /proc/interrupts looked correct.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I2b2cce9913081d5cd456043ba619a79c1dfd4a8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-06 17:26:30 +00:00
Felix Held 9541d1792a soc/amd/picasso/root_complex: add missing set_resources
The set_resources field in the root_complex_operations struct shouldn't
be NULL, but a pointer to noop_set_resources instead. This fixes the
error "PCI: 00:00.0 missing set_resources".

Change-Id: I2d9f3850b3051c92cd9c0f52f8570f4fd6133070
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-06 17:21:13 +00:00
Felix Held 15dd9b8996 soc/amd/common/block/gpio_banks: fix sequence in gpio_output
When configuring a GPIO pin as output the value should be written before
it gets configures as an output to avoid a possible glitch on the output
when the GPIO pin was an input before and the output value was different
from the one that got written afterwards.

Change-Id: I2bb5e629ef0ed2daadc903ecc1852200fe3a5cb9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-01-06 17:20:58 +00:00
Felix Held a1f254b91b soc/amd/common/block/gpio_banks: clear output enable in gpio_input_*
The functions to configure a GPIO as input with pull-up/down need to
clear the output enable bit, so that the direction will be input. If the
pin was configured as output before, the pin direction was still output
after this call which is at least unexpected.

Change-Id: Id1fa1669195080b34fd62324616825415728b0b4
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-01-06 17:20:50 +00:00
Felix Held dec00dd010 soc/amd/common/block/gpio_banks: clear pull-up/down bits in gpio_input
If the pin was configured as pull-up/down before this wouldn't get
cleared when calling gpio_input before.

Change-Id: I17d5eccb7492138e64abaecbd7cb853adb8c4d2d
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-01-06 17:20:40 +00:00
Angel Pons ef458dafc0 cpu/intel/model_206ax: Simplify C-state acpigen
Since there's only one set of values, the if-clause is unnecessary.

Change-Id: I2fb4582377fe2f204d2cee0dc513a4d5d24feabe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-06 16:51:52 +00:00
Angel Pons 6f56a23136 cpu/intel/model_206ax: Rename `cX_acpower` options
They aren't specific to AC power operation anymore. Also adapt autoport.

Change-Id: Ib04d0a08674b7d2773d440d39bd6dfbd4359e0fb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49089
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-06 16:51:30 +00:00
Angel Pons 0d5ef95fc3 cpu/intel/model_206ax: Unify ACPI C-state options
All mainboards use the same values for AC and battery, even desktop
boards without a battery. Use the AC values everywhere and drop the
battery values. Subsequent commits will rename the AC power options
accordingly, and will also clean up the corresponding acpigen code.
This is intentional so as to ease reviewing the devicetree changes.

Also update util/autoport accordingly.

Change-Id: I581dc9b733d1f3006a4dc81d8a2fec255d2a0a0f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-06 16:51:14 +00:00
Angel Pons 65cb6468da cpu/intel/x/chip.h: Drop unused `disable_acpi` setting
It is not used anywhere. Drop it.

Change-Id: I92a72a46db237cf855491a664cdfadca34306f6c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49087
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-06 16:50:52 +00:00
Angel Pons c728e257e4 nb/intel/sandybridge: Use consistent comment style
Change-Id: Iacb1fb0a1309c3c23e670fee540514b6f546314a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-01-06 16:50:43 +00:00
Angel Pons 42d033aeef nb/intel/sandybridge: Define and use `QCLK_PI` constant
To allow adjusting the phase shift of the various I/O signals, the
memory controller contains several PIs (Phase Interpolators). These
devices subdivide a QCLK (quarter of a clock cycle) in 64 `ticks`,
and the desired phase shift is specified in a register. For shifts
larger than one QCLK, there are `logic delay` registers, which allow
shifting a whole number of QCLKs in addition to the PI phase shift.

The number of PI ticks in a QCLK is often used in raminit calculations.
Define the `QCLK_PI` macro and use it in place of magic numbers. In
addition, add macros for other commonly-used values that use `QCLK_PI`
to avoid unnecessarily repeating `2 * QCLK_PI`, such as `CCC_MAX_PI`.

Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.

Change-Id: Id6ba32eb1278ef71cecb7e63bd8a95d17430ae54
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-01-06 16:50:33 +00:00
Patrick Georgi c9a9f839cb util/testing: Build test more of our tools
https://qa.coreboot.org/job/untested-coreboot-files reports a bunch of
untouched Makefiles, so we never even attempt to build those tools.

Change-Id: I70ca658d9642b84fa8388c72ecb83327a6a74291
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2021-01-06 16:27:59 +00:00
Subrata Banik 99289a89a3 soc/intel/alderlake: Update CPU microcode patch base address/size
This patch updates CPU microcode patch base address/size to FSP-S
UPD to have second microcode patch loaded successfully to enable
Mcheck flow.

This is new feature requirement for ADL as per new Mcheck initialization
flow.

BUG=b:176551651
TEST=Able to reach beyond PC6 without any MCE.

Change-Id: I936816e3173dbcdf82b2b16b465f6b4ed5d90335
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48847
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-06 02:46:43 +00:00
Peter Marheine 12defa9ee7 mb/google/zork: enable wake on MKBP events
The EC generates EC_MKBP_EVENT_DP_ALT_MODE_ENTERED when USB-C
connections enter DP alt mode, which should wake the system from S3.
Configure S3 wake events to include MKBP so this actually wakes
the system.

BUG=b:174121852
BRANCH=zork
TEST=Generating DP event on MKBP via EC console wakes morphius

Change-Id: I8100c6253e8e5cae91586c4f2f45d66c15fecc6d
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-01-05 23:33:34 +00:00
Angel Pons 8eca669fc0 nb/intel/haswell/memmap.h: Clean up
Drop unused definition and remove outdated comments.

Change-Id: I16033b558fe4c01a9394382dc0c9d0bdc66193d9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2021-01-05 20:33:24 +00:00
Raul E Rangel a553600e18 mb/google/zork: Add INT[E-H] to FCH PIR
INT[E-H] are required because the GNB IO-APIC maps the 32 interrupts
onto the 8 INT[A-H] that feed into the FCH PIC/IO-APIC.

BUG=b:170595019
TEST=Verify ezkinil still boots

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9c6689e212b136f6f3c64152803ed161b2284275
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-05 19:53:41 +00:00
David Wu 7ace66e094 mb/google/volteer/var/voema: Enable IPU for voema
Enable IPU for voema for MIPI camera.

BUG=b:169551066
TEST=IPU is enabled and shows in lspci.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I34736bffd4dc61a840003afe5afd6a9c8dc32e62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49002
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-05 18:28:23 +00:00
Felix Singer 44c9c1cec4 mb/clevo/cml-u: Rework Kconfig
Rework Kconfig file so that each variant has its own config option with
their specific selects / configuration and move common selects to a
seperate config option, which is used as base for each variant.

Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains the same.

Change-Id: I1f5b6f535597149f28dd8c8322acc2e988f11505
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-05 01:58:48 +00:00
Felix Singer 483c4fe5bc mb/clevo/kbl-u: Rework Kconfig
Rework Kconfig file so that each variant has its own config option with
their specific selects / configuration and move common selects to a
seperate config option, which is used as base for each variant.

Built clevo/n130wu with BUILD_TIMELESS=1, coreboot.rom remains the same.

Change-Id: I1f07b5851ece6d0943faa9c90fc518805880a27d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49060
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Daniel Maslowski <info@orangecms.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-05 01:50:50 +00:00
Felix Singer 0ab6f0bd4c mb/siemens/chili: Rework Kconfig
Rework Kconfig file so that each variant has its own config option with
their specific selects / configuration and move common selects to a
seperate config option, which is used as base for each variant.

Built chili/base with BUILD_TIMELESS=1, coreboot.rom remains the same.

Change-Id: I5e2a09db80232457b2f78ad9b100c468d281f753
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-05 00:20:15 +00:00
Felix Singer 086f2f6860 mb/kontron/bsl6: Rework Kconfig
Rework Kconfig file so that each variant has its own config option with
their specific selects / configuration and move common selects to a
seperate config option, which is used as base for each variant.

Built kontron/boxer26 with BUILD_TIMELESS=1, coreboot.rom remains the
same.

Change-Id: I08bd68aa2f98f93b8c5daf1ab2f3c1bbce521c53
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-01-05 00:20:08 +00:00
Felix Singer b9ba0d10a2 mb/kontron/mal10: Remove unnecessary includes
Built with BUILD_TIMELESS=1, coreboot.rom remains the same.

Signed-off-by: Felix Singer <felixsinger@posteo.net>
Change-Id: Ibc6833d9256800d0e50651cac18a4e81ddbe6895
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48144
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-05 00:02:43 +00:00
Felix Singer 1e4c1590fb mb/kontron/mal10: Move include directories to mb level
Move include directories from carriers and variants to mainboard level
being able to reuse them later. Also, rename guards so that they fit
their usage.

Built with BUILD_TIMELESS=1, coreboot.rom remains the same.

Signed-off-by: Felix Singer <felixsinger@posteo.net>
Change-Id: I55af05cb84b97d567ce1fc3b6151c34d1eda183f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48142
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-04 23:35:55 +00:00
Matt DeVillier f14e663cc4 mb/purism/librem_cnl: Fix HDA verb NID count for Librem Mini
Fix off-by-1 count of NID entries.

Change-Id: I65f70d084022c99233144b460542a793eae2acf3
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49106
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-04 23:32:04 +00:00
Kyösti Mälkki b8cf0394fb ACPI: Final APM_CNT_GNVS_UPDATE cleanup
All platforms moved to initialise GNVS at the time
of SMM module loading.

Change-Id: I31b5652a946b0d9bd1909ff8bde53b43e06e2cd9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48699
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-04 23:16:03 +00:00
Kyösti Mälkki 8c2cc68b1a arch/x86: Pass GNVS as parameter to SMM module
Change-Id: I9d7417462830443f9c96273d2cc326cbcc3b17dd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48698
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-04 23:15:46 +00:00
Matt DeVillier c5a3a4a602 mb/google/hatch (baseboard): add ACPI backlight support
Add ACPI backlight support for boards selecting BOARD_GOOGLE_BASEBOARD_HATCH.

PUFF-based variants do not have an internal panel, so do not need this.

Test: build/boot Windows 10 20H2 on google/akemi, verify
display backlight controls functional.

Change-Id: I5ce4c6e1c78299e89760a1356da452d56ba0aee6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49058
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-04 23:15:19 +00:00
Matt DeVillier 2ece21244e mb/google/reef (and variants): add ACPI backlight support
Enables backlight control under Windows 10.

Test: build/boot Windows 10 20H2 on google/reef, verify
display backlight controls functional.

Change-Id: I4ce613badbdcfb9c843f52408df26c6cbb4b82a2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-04 23:14:47 +00:00
Maxim Polyakov 4f980425b1 mb/razer/blade_stealth_kbl: 3/3 Convert field macros to PAD_CFG
Converts bit field macros to target PAD_CFG_*() macros. To do this,
the following command was used:

./intelp2m -n -t 1 -file ../../src/mainboard/razer/blade_stealth_kbl/
gpio.h

This is part of the patch set
"mb/razer/blade_stealth_kbl/gpio: Rewrite pad config using intelp2m":

CB:43857 - 1/3 Decode raw register values
CB:43858 - 2/3 Exclude fields for PAD_CFG
CB:43411 - 3/3 Convert field macros to PAD_CFG

Tested with BUILD_TIMELESS=1, Razer Blade Stealth, remains identical.

Change-Id: Ie9da1246b784578c1e29acc5c61a918841de7468
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-01-04 23:13:38 +00:00
Lijian Zhao 5bd9b7f0c1 MAINTAINERS: Add maintainer for ACPI
Change-Id: I65fdee350273c58e027a002dba1f97a56115e195
Signed-off-by: Lance Zhao <lance.zhao@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48970
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-01-04 23:13:18 +00:00