Commit Graph

35911 Commits

Author SHA1 Message Date
V Sowmya 3915627615 mb/google/dedede: Skip the CPU replacement check for dedede
This patches enables the SkipCpuReplacementCheck config for
the dedede baseboard to avoid the forced MRC training for all
its variants with the soldered down SOC.

BUG=b:160201335
TEST=Build and verify CSE Lite SKU on Waddledoo.
Cq-Depend: chrome-internal:3142530

Change-Id: I611e66f74a3b9b090ab5e0d836231643d3f919dc
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-07-23 04:54:14 +00:00
V Sowmya e8156ad981 soc/intel/jasperlake: Add the SkipCpuReplacementCheck configuration
Add SkipCpuReplacementCheck config to control the FSPM UPD used
for skipping the CPU replacementment check to avoid the forced
MRC training for the platforms with soldered down SOC.

BUG=b:160201335
TEST=Build and verify CSE Lite SKU on Waddleddo.
Cq-Depend: chrome-internal:3142530

Change-Id: I63fcdab3686322406cf7c24fc26cbb535cc58c8d
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-07-23 04:54:01 +00:00
Angel Pons df96d4db84 sb/intel/i82801jx/hdaudio.c: Rename to `azalia.c`
Other Intel southbridges use this name for the HD audio codec.

Change-Id: Ic96797e6c2028f082130211bb5f4270391f866c5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-22 22:21:13 +00:00
Angel Pons 0cd80270d1 sb/intel/i82801ix/hdaudio.c: Rename to `azalia.c`
Other Intel southbridges use this name for the HD audio codec.

Change-Id: I50dbf0a079944b7fa6cfd6622c0626bc9139af85
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-22 22:20:50 +00:00
Angel Pons 25a0b0ac5e sb/intel/i82801ix/sata.c: Use `probe_resource`
It is impossible for `find_resource` to return NULL, it dies instead.

Change-Id: If8e26f768383e741100e3690322db3dabeec1922
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-22 22:20:05 +00:00
Tim Wawrzynczak 7777e1c30b ec/google/chromeec: Fix Coverity Scan error (BAD_SHIFT)
A recent Coverity scan found an issue with the way the
EC_HOST_EVENT_MASK macro was being used. It was being passed values
between 0 and 63, but since it is doing basically (1ULL << (value - 1)),
this caused a shift of -1 when `i` is 0 and also doesn't reach the 63rd
bit of the mask. This is fixed by incrementing the start and end
conditions of the loop by 1, so the event mask ranges from bits 0 to 63,
instead of -1 to 62.

Found-by: Coverity CID 1430218
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I6a7cfa64545f3d313de24407f0a91b48368f2a8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-07-22 21:06:56 +00:00
Tim Wawrzynczak 60c619f6a3 soc/intel/jasperlake: Move tco_configure to bootblock
Similar to CB:43313 (SHA bb50c67227), it seems possible for the same
problem to come up on jasperlake. Again, it should be harmless to
configure the TCO device earlier in the boot flow.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: If95e46124660b4ed457434f727c9f9f7b02b0327
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43539
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-22 21:06:34 +00:00
Tim Wawrzynczak 03ed5bff5c soc/intel/cannonlake: Move tco_configure to bootblock
Similar to CB:43313 (SHA bb50c67227), it seems possible for the same
problem to come up on cannonlake. Again, it should be harmless to
configure the TCO device earlier in the boot flow.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ib8883d27b2a0994a67ec5e044a692a2e853fd680
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43538
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-22 21:06:29 +00:00
Kane Chen bfd6521ce7 mb/google/zork: Modify Woomax variant
Update Woomax configuration including GPIO, memory SPD table, I2C devices
and USB type C.

BUG=b:158343602
BRANCH=None
TEST=emerge-zork coreboot

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I55ba995d9438551d45cb9e17f92b5089ccf4a5fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-22 15:20:28 +00:00
Angel Pons 3580d816e6 nb/intel/i945: Put names to northbridge PCI devices
Tested with BUILD_TIMELESS=1, Getac P470 does not change.

Change-Id: I0d51f48f0c1e37c41322a0eda49806925d9d194d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42285
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-22 14:51:39 +00:00
Felix Held ce55b36c99 mainboard/amd/mandolin: describe where the two HDA codecs reside
Change-Id: I99b062e4ce1cf862ea03b0edb6ea843df5f8f2b2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-22 14:43:13 +00:00
Tim Chu 0ecb7857ce mb/ocp/deltalake: Unset POWER_STATE_DEFAULT_ON_AFTER_FAILURE
Change PCH power policy. Set default of
POWER_STATE_DEFAULT_ON_AFTER_FAILURE to n in order to change power
state to S5 when power is reapplied after power failure.

TEST=Base on CB:42289, CB:43338 and build for Deltalake.
The following Kconfig options must be selected:
	select SOC_INTEL_COMMON_BLOCK_PMC
	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
	select CPU_INTEL_COMMON_SMM

Boot the system and check the last bit of GEN_PMCON_B is set to 1
through ITP with command: pch.pm_dump

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I4d4f14bdfc18740976171fd5d369b2d79a916dc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42976
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-22 12:20:49 +00:00
Johnny Lin 2b3a500fed mb/ocp/deltalake: Set FSP log level and add default values if VPD variables are not found
1. Read VPD variable 'fsp_log_level' to decide FSP log level.
2. Define the default values when the VPD variables cannot be found,
   put all the values to vpd.h for better documentation and maintenance.

Tested=On OCP DeltaLake, the fsp_log_level can be changed from the VPD variable.

Change-Id: I44cd59ed0c942c31aaf95ed0c8ac78eb7d661123
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-22 12:19:53 +00:00
Felix Held 973b2aaa24 vc/amd/fsp/picasso: mark remaining UPD header structs as __packed
Change-Id: I5a97de69bfda201e039587c67037bfb93ca16c15
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43658
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-22 11:53:12 +00:00
Angel Pons 8d5cedf046 sb/intel/i82801jx: Drop `docking_supported`
The three mainboards using this southbridge are desktop boards, which
are not dockable. The Dell Precision M6400 laptop is dockable, but even
though it has an Eaglelake MCH, it uses an i82801ix southbridge instead.
So, one could still port that laptop to coreboot after this change! :P

Also, drop the now-unnecessary `chip` and `dev` variables.

Change-Id: Ic9ab497c91d66032929190cde22d59a208887f50
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-22 08:27:33 +00:00
Angel Pons 27387c3cf5 sb/intel/i82801jx: Drop `c3_latency`
The three mainboards using this southbridge do not define it. Note that
the default value of zero might be wrong, so add a FIXME comment.

Change-Id: Id16bb12a4628daf311bddf7e4701fc480d6b18e5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-22 08:27:23 +00:00
David Hendricks 4cdc698707 Doc/tutorial/part1.md: Show how to list toolchain targets
Change-Id: I276ea0a6b52b55b8772c76f48f7a0fb149af6e78
Signed-off-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43518
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-22 04:56:25 +00:00
Hung-Te Lin bc792af28e mb/google/kukui: revise config structure for Jacuzzi followers
There are more Jacuzzi followers coming and we want to have a simplified
way of adding new boards. Now, detachable and tablets should select
BOARD_GOOGLE_KUKUI_COMMON and clamshells should select
BOARD_GOOGLE_JACUZZI_COMMON.

BUG=None
TEST=make menuconfig; make -j # for kukui, krane, jacuzzi, juniper
BRANCH=kukui

Change-Id: Ifc1eb6a3792f46c5db6b5346902f1114955b28ae
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-07-22 00:27:43 +00:00
Ian Feng b0b7c351d7 mb/google/dedede: Create madoo variant
Create the madoo variant of the waddledoo reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.1.1).

BUG=b:161191394
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_MADOO

Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I6d3f611606f86036d67be9c8b0fda833ab61ecc1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-07-21 23:57:43 +00:00
Subrata Banik b622d4b27b soc/intel/tigerlake: Select PLATFORM_USES_FSP2_2
This patch performs below operations
1. Add support for FSP 2.2
2. Set EnableMultiPhaseSiliconInit to ensure bootloader can call
FspMultiPhaseSiInit() API.
3. Provide placeholder to perform require chipset programming (example TCSS)
before calling FspMultiPhaseSiInit() API.

Change-Id: I15252d2db3f8e75d430b84e86cc5141225a3f981
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-07-21 22:57:49 +00:00
Furquan Shaikh f6b2e6f836 mb/googlz/zork: Drop unnecessary PULL_UPs in variant overrides
This change drops the pulls configured on override GPIOs as they
already have external pull-ups. Also, pads which are unused are
configured as PAD_NC.

BUG=b:154351731

Change-Id: I8da5d51af25bbe2694c21ecb0868c9cc387243cb
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-07-21 22:42:57 +00:00
Angel Pons b4b4e32e4c sb/intel/lynxpoint/me_9.x.c: Add spaces around `=`
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I1baa731335a9c543c7d31b9aadc8758806750c64
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42629
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21 22:12:59 +00:00
Michael Niewöhner 48833363da mb/system76/lemp9: drop FSP_M_XIP
Drop FSP_M_XIP since it's selected by the soc already.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I999d369be395de08d4ab7f115fedf4b7fa10eb34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
2020-07-21 22:11:56 +00:00
Michael Niewöhner f662020a4d mb/system76/lemp9: drop ONBOARD_VGA_IS_PRIMARY
Drop config ONBOARD_VGA_IS_PRIMARY as it's only needed for mainboards
with multiple graphics devices.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I6525c65af3dcfc96ea3d68a1388432179e9ac43d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43636
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21 22:11:41 +00:00
Angel Pons 5ad4dabfa1 configs/config.stm: Correct config file name
Otherwise, Jenkins doesn't pick up the file, and STM doesn't get
build-tested.

Change-Id: I7cf23c8352f82b2672c7ff25efba0057b8e059cd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eugene Myers <cedarhouse1@comcast.net>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-07-21 22:08:04 +00:00
Peter Lemenkov d4fb407158 mb/lenovo/t430/gma-mainboard.ads: Replace with GPLv2+ equivalent
Replace it with t430s/gma-mainboard.ads which is licensed under more
flexible terms (GPL-2.0-only vs. GPL-2.0-or-later). Apart from licensing
terms these files are identical.

This makes diff between boards smaller.

Change-Id: I633702d363134654e71e35404237d75b499f089a
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-07-21 21:53:03 +00:00
Peter Lemenkov a1dcb994d7 mb/lenovo/t420/gma-mainboard.ads: Replace with GPLv2+ equivalent
Replace it with t420s/gma-mainboard.ads which is licensed under more
flexible terms (GPL-2.0-only vs. GPL-2.0-or-later). Apart from licensing
terms these files are identical.

This makes diff between boards smaller.

Change-Id: I5393a603b5a4cd353149c1fa9e3e29020946b962
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-07-21 21:52:53 +00:00
Angel Pons 002e5e057c security/intel/stm: Add missing <stdbool.h>
Jenkins does not build `config.stm` because the file name lacks the
mainboard name. So, the code was not being build-tested, and it does not
build because several files lacked the definition for `bool`.

Add the missing #include directives. Renaming the config file so that
Jenkins build-tests it is done in a follow-up.

Change-Id: Idf012b7ace0648027ef6e901d821ca6682cee198
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43622
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Eugene Myers <cedarhouse1@comcast.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21 20:04:12 +00:00
Elyes HAOUAS 04071f43bc src: Use ACPI macros
Change-Id: I2cf11b784299708f02fd749dcb887b6d25f86f5b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-21 18:26:47 +00:00
Mate Kukri f2c13bd905 soc/intel/baytrail: Add new CPUID 0x30679
This ID is reported by newer mfg date SOCs. Needed for newer GBYT4 boards.

Change-Id: I6af746d66a15f67553de1dc1c925e5cb0b181898
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-21 18:26:15 +00:00
Mate Kukri 9c4f97ac28 mb/biostar: Add TH61-ITX port
- CPU: only tested with a Xeon E3-1220 (Sandy Bridge)
- RAM: native raminit tested (4G+4G, 8G+8G)
- USB: both chipset and ASMedia USB3 work, tested in SeaBIOS and Linux (5.4)
- LAN: tested in Linux
- SATA: all 4 ports work, tested in SeaBIOS and Linux
- iGPU: I can't test it as I only have a Xeon for this socket
- PEG: tested with an nVidia GT210, initialized by SeaBIOS
- PS2 keyboard and mouse combo port: no devices to test with
- Front panel header: tested, works
- Audio: tested, works
- Diagnostic LEDs: TBD

Change-Id: I9fd3c0b148b694fcb8e728cc17f0bd45eb5af9f2
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43165
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21 18:25:51 +00:00
Angel Pons 1659724375 e7505/i82801dx: Use common code for early SMBus
While it looks different, the early SMBus code for this southbridge is
still the same. In addition, this code was not checking the vendor ID
before. It is assumed that adding this check does not pose a problem.

Change-Id: I95ae4db399ce5592cefca82fa75f349220023b8c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42006
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21 18:24:07 +00:00
Angel Pons 7a2cb35262 i945/pineview/x4x/i82801gx: Use common code for early SMBus
The early SMBus code for this southbridge checked if the PCI device ID
is valid. However, we can't easily do that in common code, and we should
not attempt to do so either: if a SMBus device behaves differently, then
it should not be using the common code anyway.

Since this southbridge is used with two different northbridges, we need
to update both of them. Plus, x4x raminit no longer needs to know which
southbridge it is paired with, since both i82801gx and i82801jx use the
common early SMBus code, so we drop some preprocessor around includes.

Change-Id: Ic60a3f89bda6000fbe646461f05240c1b09db6e9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42005
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21 18:23:54 +00:00
Angel Pons 53a343e65b gm45/i82801ix: Use common code for early SMBus
The early SMBus code for this southbridge checked if the PCI device ID
is valid. However, we can't easily do that in common code, and we should
not attempt to do so either: if a SMBus device behaves differently, then
it should not be using the common code anyway.

Change-Id: I5c21e091e437d23a173ddcf35d4f1efada6194cb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42004
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21 18:23:25 +00:00
Angel Pons c274be5fc4 x4x/i82801jx: Use common code for early SMBus
The early SMBus code for this chipset was not checking the vendor ID
before. It is assumed that adding this check does not pose a problem.

Change-Id: I0c36c8cd8aca8db860b1edafd29d4f2dbaa2c822
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42003
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21 18:23:15 +00:00
Angel Pons 64285775a0 sb/intel/lynxpoint: Use common code for early SMBus
Looks like no one uses early SMBus for now, but that may change someday.

Change-Id: I42971662a279860a8c2e058fcb194fe5eba7c740
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42001
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21 18:23:07 +00:00
Angel Pons d39e6b6d81 sandybridge/bd82x6x: Use common code for early SMBus
Change-Id: I95b82f3d733db2a46096205f23ed85aaff021e28
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42000
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21 18:22:59 +00:00
Angel Pons 90e9f54726 ironlake/ibexpeak: Move early_smbus.c to common code
We will update the other platforms to use this common code in
susbsequent commits. While we are at it, reflow a broken line,
define the SMBus PCI device in the header and fix whitespace.

Change-Id: I1fdff2feead4165f02b24cb948d8c03318969014
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41999
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21 18:22:52 +00:00
Angel Pons 492d801aab device/cardbus_device.c: Drop `cardbus_size_bridge_resource`
It does nothing useful anymore. Drop it before it grows moss.

Change-Id: I5f95376fe2a38eda5d819c53edb85ef11ab7a0f1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43591
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21 18:22:09 +00:00
Maxim Polyakov 1eb095402e soc/intel/xeon_sp/cpx: remove unused gpio.h
This file does not contain useful information and is not used to build
the image. The common GPIO driver from soc/intel/common uses layout in
lewisburg_pch_gpio_defs.h [1,2] file, which is correct for all chipsets
from the Lewisburg family: C621, C621A, C622, C624, C625, C626, C627,
C627A, C628, C629, C629A [3]

[1] src/soc/intel/xeon_sp/include/soc/lewisburg_pch_gpio_defs.h
[2] https://review.coreboot.org/c/coreboot/+/39425
[3] Intel document #547817

Change-Id: I1f3ac4afff9e628890df8cec075fd3e42a590172
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43535
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Reviewed-by: Bryant Ou <bryant.ou.q@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21 16:41:47 +00:00
Maxim Polyakov de7092b8a3 inteltool/gpio: Add support for new Lewisburg chipsets
- Add SKUs and Super SKUs of new Lewisburg series chipsets:
  C621A, C627A, C629A [1].
- These changes allow the utility to generate the GPIO config
  registers dump.

[1] https://review.coreboot.org/c/coreboot/+/40395

Change-Id: I9b63c0a3860a901e58af0c0d5184361661bab5e3
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43534
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21 16:40:48 +00:00
Maxim Polyakov ec0551c6b0 util/inteltool: add missing L0 and L1 pads for Lewisburg
The description for L0 and L1 was missed in the datasheet, however,
configuration registers for these pads are present. In addition, the
chipset contains the "GPP_L0/CSME_INTR_IN" and "GPP_L1/CSME_INTR_OUT"
pads in a circuit diagram. Use all available information to add a
description for the missed pads.

Change-Id: I7a0488c26b3df9de1adc037d94ae290837d65dd8
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40044
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-21 16:39:14 +00:00
Nico Huber 3c7888bf29 libpayload/xhci: Try harder to read 32-bit caps at once
With commit 287cf6c7d1 (lp/drivers/usb: Work around QEMU XHCI
register issue) we restructured our capability register accesses
because the compiler used the wrong access size. While we do use
only 32-bit types now, a compiler may still try to be clever and
optimize things in unexpected ways. So we add an explicit read32()
now.

For instance for the 8-bit MaxPorts field, in the most significant
bits of `capreg + 4`, our read + mask + shift

    ((cap)->hciparams1 & 0xff000000) >> 24

was turned into a single 8-bit read instruction by GCC on x86:

      31:   0f b6 52 07             movzbl 0x7(%edx),%edx

Change-Id: I76accd0ef718e70ca46807eb06a9177c3afd99f1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-07-21 15:14:48 +00:00
Eric Lai 767467dc67 google/trogdor: Remove write_protect_state
This is no longer used for chromeos.c.

BUG=b:160752610

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I9a716a88ff9811fff46abca229be15522733bfef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-07-20 20:53:21 +00:00
Angel Pons 51e138c25b drivers/intel/gma/Kconfig: Avoid dependency hell when ignoring straps
Unconditionally selecting `GFX_GMA_IGNORE_PRESENCE_STRAPS` creates a
hard dependency on `MAINBOARD_USE_LIBGFXINIT`, which is undesired. Move
it out of the `if GFX_GMA` block to break this unwanted dependency.

TEST=Build for Librem 13v4 with no graphics init successfully.

Change-Id: I53e132c209c065068f20959fa1a6f5195f5fe766
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-20 17:13:22 +00:00
Angel Pons b21bffae0c sb/intel: Define CONFIG_FIXED_SMBUS_IO_BASE
Make it default to 0x400, which is what the touched southbridges use.

Change-Id: I95cb1730d5bf6f596ed1ca8e7dba40b6a9e882fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-20 17:04:46 +00:00
Pandya, Varshit B 65e5b100e2 mb/google/dedede: Update link frequency and end point structure for OV9734
1. Update Link frequency to 180 Mhz
2. Set data-lanes to 1 and
3. Update the clock-lane used by sensor

BUG=b:155285666
BRANCH=None
TEST=Build and able to capture image using user facing camera.

Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com>
Change-Id: I164cb6af1003de561be8ce640e7653b7bcb3a22f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-07-20 15:18:23 +00:00
Raul E Rangel 500eb450b5 mb/amd/mandolin: Delete sleep.asl
These methods are empty and the kernel treats these as optional.

BUG=b:153001807, b:154756391
TEST=none

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic8ee8fb6b6bcd04c653ab77cdc5e746a8cbd0c4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43466
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20 14:01:24 +00:00
Raul E Rangel 030bace562 mb/google/zork: Delete sleep.asl
These methods are empty and the kernel treats these as optional.

BUG=b:153001807, b:154756391
TEST=Suspend and resume trembyle

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5f2b375c1186951f95b7ac44dc7158a0299013a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43465
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20 14:01:09 +00:00
Furquan Shaikh dce0ce954f mb/google/zork: Drop unnecessary PULL_UPs for dalboz reference
This change drops internal pulls for dalboz reference configured on pads
which already have external pull-ups in hardware.

GPIO_0(PWR_BTN_L): Pulled up to PP3300_A
GPIO_2(WAKE_L): Pulled up to PP3300_A
GPIO_10: Unused. Changed to PAD_NC.
GPIO_11(EC_IN_RW_OD): Pulled up to PP3300_A
GPIO_12(USI_INT_ODL): Pulled up to PP3300_A
GPIO_16(USB_OC0_L): Pulled up to PP3300_A
GPIO_17(USB_OC1_L): Pulled up to PP3300_A
GPIO_21(EMMC_CMD): Pulled up to PP1800_S0
GPIO_22(EC_FCH_SCI_ODL): Pulled up to PP3300_A
GPIO_31(EC_AP_INT_ODL): Pulled up to PP1800_A
GPIO_32: Unused. Changed to PAD_NC.
GPIO_113(I2C2_SCL): Pulled up to PP3300_S0
GPIO_114(I2C2_SDA): Pulled up to PP3300_S0
GPIO_129(KBRST_L): Pulled up to PP1800_S0
GPIO_92(CLK_REQ0_L): Pulled up to PP3300_S0
GPIO_115(CLK_REQ1_L): Pulled up to PP3300_S0
GPIO_116(CLK_REQ2_L): Pulled up to PP3300_S0

BUG=b:154351731

Change-Id: I62e9dbac7a55efa1e055983a7c126168ee516151
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-20 13:54:31 +00:00