Commit Graph

38735 Commits

Author SHA1 Message Date
Felix Held dc2d3566ff soc/amd/cezanne: add skeleton for new SoC
This is based on the minimal example code in soc/example/min86 and was
adapted to use the AMD non-CAR boot block and the common AMD PCI MMCONF
support.

In its current state this won't even reach the boot block, but will pass
the build bot. The missing parts for that will be added in future
patches. This is an attempt to not go the usual route to create a copy
of a previous SoC generation and the make changes to the code to work
for the new SoC, but to start from a nearly empty directory and then add
the actual code stage by stage and component by component.

Change-Id: I70aeb9ae010e943abfa667a0ea95c6fa9f15b7f5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-05 09:43:00 +00:00
David Wu b7801d58d7 mb/google/volteer/var/voema: Add MIPI camera support
1. Add VARIANT_HAS_MIPI_CAMERA to Kconfig.name
2. Add mipi_camera.asl

BUG=b:169356808,b:169551066
TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I63d133246dbdc6aff7bf97d98f95052edf53bac9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47668
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-05 08:23:04 +00:00
Tony Huang c34c15be63 mb/google/puff/var/dooly: Update DPTF parameters
DPTF paramerters form thermal team.
Set PL1 Min/Max 15/25W, PL2 Min/Max 40/49W.

BUG=b:174514010
BRANCH=puff
TEST=build image and verified by thermal team.

Change-Id: I9e6c4bae181e87f87f2e92337bb9d989f5b7d955
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2020-12-05 08:22:25 +00:00
Chris Wang ad481c475f mb/google/zork: set APU_EDP_BL_DISABLE to low as default
set APU_EDP_BL_DISABLE(GPIO_85) to low to avoid the VARY_BL fast than
APU_DP_BLON.

BUG=b:171954512
BRANCH=zork
TEST=validate the panel sequence with scope.

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ia6d3f4335583bb2d91a6bce96d89cff84247d0ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2020-12-05 08:20:58 +00:00
FrankChu 86a241e90c mb/google/volteer: Create copano variant
Create the copano variant of the volteer reference board by
copying the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.3.1).

BUG=b:174413884
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_COPANO

Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Ib06625f492f68a6a6f5c6b382772b68f1eb681ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
2020-12-05 08:20:15 +00:00
Patrick Rudolph 40beb36f07 drivers/intel/fsp2_0/memory_init: Wrap calls into FSP
Use a wrapper code that does nothing on x86_32, but drops to protected
mode to call into FSP when running on x86_64.

Tested on Intel Skylake when running in long mode. Successfully run the
FSP-M which is compiled for x86_32 and then continued booting in
long mode.

Change-Id: I9fb37019fb0d04f74d00733ce2e365f484d97d66
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48202
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-05 08:19:34 +00:00
Patrick Rudolph 7a359497cd cpu/x86/64bit: Add code to call function in protected mode
This adds a helper function for long mode to call some code in protected
mode and return back to long mode.

The primary use case is to run binaries that have been compiled for
protected mode, like the FSP or MRC binaries.

Tested on Intel Skylake. The FSP-M runs and returns without error while
coreboot runs in long mode.

Change-Id: I22af2d224b546c0be9e7295330b4b6602df106d6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-05 08:19:17 +00:00
Kevin Chang 22b42a87de mb/google/volteer/variant/lindar: Correct SD card reader power sequence
According to the spec provided by Bayhub, the 3.3V power rail must be enabled at least 100ms before reset is released.
To ensure this, set the power enable signal in the bootblock GPIO table.

BUG=b:173676531
BRANCH=firmware-volteer-13521.B
TEST=Built and booted into OS, test USB function normally.

Change-Id: I0c536f36c138ace93766f3024f6ec5d47b38269f
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47799
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-05 08:16:19 +00:00
Eric Lai bb3b314807 mb/google/zork: Replace generic driver with sx9324 driver
Use a new driver for the SX9324 proximity detector device.
This is first draft settings, will modify it after fine tuning.

BUG=b:172397658
BRANCH=zork
TEST=run "i2cdump -y -f 0 0x28" and checked all registers are expected.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I869d0b6640247099ca489e96ed94e03811a04bf4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47867
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-05 08:15:46 +00:00
Eric Lai f24450af68 drivers/i2c/sx9324: Add more registers and reorder
Export all registers that driver is looking for. And put in alphabetic order.
The missing registers for kernel v5.4 sx93xx are:
reg_irq_msk
reg_irq_cfg0
reg_irq_cfg2
reg_afe_ph0/1/2/3

BUG=b:172397658
BRANCH=zork
TEST=Build passed

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ic9d7a959b1769b6846bba302e3aeab9a3a1cedac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47866
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-05 08:15:26 +00:00
Eric Lai 1a3ae36c6a mb/google/zork/var/vliboz: Add LTE_RST power sequence
Latest HW schematic add LTE_RST pin to control module power sequence.

BUG=b:173490220
BRANCH=zork
TEST=measure the waveform is meet the LTE module spec.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I0f0a35a905d711dd8d17dea2ae82a8dfa1fa05ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-05 08:14:54 +00:00
Maulik V Vaghela 6c38f35da3 mb/google/dedede/var/drawcia: Configure Acoustic noise mitigation UPDs
Enable Acoustic noise mitigation for drawcia and set slew rate to 1/4
which is calibrated value for the board. Other values like PreWake,
Rampup and RampDown are 0 by default.

BUG=b:162192346
BRANCH=dedede
TEST=Correct value is passed to UPD and Acoustic noise test passes.

Change-Id: Iadcf332d59dac2ba191b82742a18a1ab326940d1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-12-05 08:14:41 +00:00
Maulik V Vaghela a4bef79522 soc/intel/jasperlake: Add Acoustic noise mitigation configuration
This patch exposes acoustic noise mitigation related UPDs/configuration
to be filled from devicetree.
For each variant, we might have different values for various parameters.
Filling it from devicetree will allow us to fill separate values for
each board/variant.

Note that since JasperLake only has one VR, we're only filling index 0
for slew rate and FastPkgCRampDisable.

BUG=b:162192346
BRANCH=dedede
TEST=code compilation is successful and values from devicetree are
getting reflected in UPDs

Change-Id: Id022f32acc3fd3fe62f78e3053bacdeb33727c02
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-12-05 08:11:16 +00:00
Marc Jones c987e65eb4 soc/intel/xeon_sp: Don't use common block acpi.h
Don't use the common block acpi.h when we aren't using the
COMMON_ACPI config. Fixes a dependency build issue in an upcoming
commit.

Change-Id: I3b80f7bbdf81e594fdde5b750c666edd8ca7268d
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2020-12-05 08:10:33 +00:00
V Sowmya 2c9d65b51b soc/intel/common/block/usb4: Add the PCI ID for ADL
This patch adds the PCI device ID for Alderlake
CPU xHCI.

Change-Id: I4074a81aa9be2ef3a0956da08bece32a613415ab
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-12-05 05:36:41 +00:00
V Sowmya 5fc798f40e device/pci_id: Add TCSS PCI IDs for Alderlake
Add the PCI IDs for Alderlake TCSS,
* USB xHCI
* USB xDCI
* TBT DMA
* TBT PCIe

Change-Id: I28bb310c7b031d2766c9e03dbcbe1c79901a7d87
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48242
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-05 05:36:29 +00:00
Julius Werner 0247fcf87b cbfs: Add more error messages for lookup
The new CBFS stack will log messages for found files but leaves error
messages up to the caller. This patch adds appropriate generic error
messages to cbfs_lookup(), matching the behavior of the old CBFS stack
for not found files.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I8cf44026accc03c466105d06683027caf1693ff0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-04 22:35:40 +00:00
Felix Held 88d8e2b74e soc/amd/picassso/acpi: increase MMIO region size of GPIO controller
The GPIO controller on Picasso has 4 banks of GPIOs with a size of 256
bytes each, so increase the reserved size to match the hardware.

Also replace the base GPIO address with the corresponding define.

Change-Id: I453f1c531d612a0e82ee0d91762fec6cdb2b8556
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-04 21:46:17 +00:00
Eric Lai ce66f34372 mb/google/brya: Initiate device tree
Initiate device tree based on latest schematic.

BUG=b:174266035
TEST=Build Test

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia94119cb6d7eff6ea13c7d6a7dfd6ce891f706fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-04 21:10:31 +00:00
Eric Lai ff6a1e5149 soc/intel/alderlake: Align chipset.cb with pci_devs.h
Refer pci_devs.h naming to align chipset.cb.
Correct thc0, thc1 and add cnvi_bt.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Iac33983dc12ed4e5b9257c50d82adc8e4e728ad6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48153
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04 21:10:19 +00:00
Eric Lai 99af54e66d mb/google/brya: Add EC smihandler
Add implementation of EC smihandler

BUG=b:174266035
TEST=Build Test

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I211f5755ff44514ab7ab4083f684ddd88c23fe48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48115
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04 21:10:04 +00:00
Eric Lai 78b6a1bbcd mb/google/brya: Enable EC
Perform EC initialization in bootblock and ramstages. Add associated
ACPI configuration.

BUG=b:174266035
TEST=Build Test

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ie1305706134ca7cc58b8a9941231d1ee14f80949
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-04 21:09:56 +00:00
Eric Lai b052c4b368 mb/google/brya: Enable building for Chrome OS
Enable building for Chrome OS and add associated ACPI configuration.

BUG=b:174266035
TEST=Build Test

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I5311879a127a2c8da1bbb086449019d932d57b72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-04 21:09:37 +00:00
Eric Lai 812f36425e mb/google/brya: Set UART console
Follow latest schematic UART_PCH_DBG is UART 0.

BUG=b:174266035
TEST=Build Test

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I8e334fee1adcd79d058b7ab07127f8ecf1735202
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48070
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04 21:09:20 +00:00
Eric Lai bca5bdb056 mb/google/brya: Enable ACPI and add ACPI table
Enable ACPI configuration and add DSDT ACPI table.

BUG=b:174266035
TEST=Build Test

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I08513ec159b69535f742a1fd70cdec9ec845d414
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-04 21:09:07 +00:00
yuanliding e1d7d8464c Coachz: change EN_PP3300_DX_EDP from gpio52 to gpio67
Coachz rev1 has changed EN_PP3300_DX_EDP from gpio52 to gpio67.

BRANCH=none
BUG=b:174123578
TEST=emerge-strongbad coreboot chromeos-bootimage.
flash coreboot and boot up normally.

Signed-off-by: yuanliding <yuanliding@huaqin.corp-partner.google.com>

Change-Id: I32a721d0d725bf217debe35a5cdc01aa8f5d5daf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2020-12-04 20:53:57 +00:00
Arthur Heymans 9ddd9002cc cpu/x86/smm_module_loaderv2: Fix compiling for x86_64
Change-Id: I9288ede88f822ff78dd9cb91020451dc935203a0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-12-04 17:20:30 +00:00
Felix Held 161d809bc6 soc/amd: move smi_util to common block
The functionality in smi_util applies for all 3 AMD SoCs in tree. This
patch additionally drops the HAVE_SMI_HANDLER guards in the common
block's Makefile.inc, since all 3 SoCs unconditionally select
HAVE_SMI_HANDLER in their Kconfig and smi_util doesn't use any
functionality that is only present when that option is selected.

Change-Id: I2f930287840bf7aa958f19786c7f1146c683c93e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-04 13:42:29 +00:00
Paul Menzel 1f03f1ed1f mb/amd/mandolin: Unify devicetree formatting for 00:14 devices
To accommodate also `off`, two spaces are used after `on` to align
comments.

This unifies the devicetree files of the two variants.

Change-Id: I7908fe2313ddccb6a4448a6338d6cd4938264f62
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-04 13:41:40 +00:00
Paul Menzel 0d53e75d85 mb/amd/mandolin: mandolin: Fix typo in *Coprocessor* in comment
This reduces the difference with Cereme’s devicetree file.

Change-Id: I1e6ba5891245562d5132307eab224623031e11c8
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-04 13:41:02 +00:00
Felix Held 5b2405a308 mb/amd/mandolin: use more readable size formats in FMAP files
Since the FMD file isn't parsed any more by a shell script in the SoC's
Makefile.inc, we can use better human-readable numbers for the section
sizes.

TEST=Timeless build results in identical image.

Change-Id: I2117064a694f67767284f6fd4ac3604b254a2734
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-04 13:39:34 +00:00
Felix Held a4819cd0b3 mb/amd/mandolin: removed unused MANDOLIN_MICROCHIP_FW_OFFSET
TEST=Timeless build results in identical image.

Change-Id: Ifa5c14add555b382f74ba1165131b1569bbef123
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-04 13:38:58 +00:00
Arthur Heymans a75a2fa1d6 mb/emulation/x86: Add optional parallel_mp init support
This makes it possible to select both the legacy LAPIC AP init or the
newer parallel MP init.

Tested on i440fx with -smp 32.

Change-Id: I007b052ccd3c34648cd172344d55768232acfd88
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-04 11:12:13 +00:00
Arthur Heymans 5e31a1939b cpu/qemu-x86: Increase MAX_CPUS to have actual AP init
CONFIG_MAX_CPUS=4 is the maximum supported with SMM_ASEG.

TESTED: on q35 and i440fx -smp 4/32.

Change-Id: I696856870e34e7a7ad580bc83c6b38f1dfb4511d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-04 11:11:45 +00:00
Arthur Heymans 91d5a6cc47 cpu/x86/lapic/secondary.S: Adapt for x86_64
Adapt the old lapic init code for x86_64.

Change-Id: I5128ed574323025e927137870fb10b23d06bc01d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-04 11:11:26 +00:00
Arthur Heymans d79e48570c cpu/qemu-x86: Add the option to have no SMM
Qemu i440fx does not support an smihandler at the moment.

Change-Id: I5526b19b8294042a49e5bca61036e47db01fd28a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-04 11:11:17 +00:00
Arthur Heymans d0e9538f88 drivers/intel/fsp2_0: FSP-T requires NO_CBFS_MCACHE
When FSP-T is used, the first thing done in postcar is to call FSP-M
to tear down CAR. This is done before cbmem is initialized, which
means CBFS_MCACHE is not accessible, which results in FSP-M not being
found, failing the boot.

TESTED: ocp/deltalake boots again.

Change-Id: Icb41b802c636d42b0ebeb3e3850551813accda91
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48282
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04 11:00:45 +00:00
V Sowmya 407488edaa src/soc/intel/alderlake: Enable the PCH HDA
This patch enables the PCH HDA device based on the devicetree
configuration.

Change-Id: I1791b769f4ab41cf89d82cf59049a2980c6c1eb0
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48272
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04 07:05:43 +00:00
Felix Held fef413e4be MAINTAINERS: add maintainers for soc/amd/cezanne and soc/amd/common
Change-Id: Ib661fdf27d5cdb6c2b989c7f2acfc8a6e061657c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48239
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04 02:04:17 +00:00
Michael Niewöhner 9b57022ab4 mb/supermicro/x11ssm-f: correct trigger for SMI/NMI interrupt inputs
All four SMI/NMI interrupt inputs have an external pull-up resistor and
get triggered by pulling the line low. Thus, correct the trigger to
active-low.

Also document the signals by adding appropriate comments.

The pads' connections have been determined by dissecting a dead board.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Id1a8c1e0b9fe723a15d04a88d565a53eeba9b085
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48093
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04 00:11:17 +00:00
Michael Niewöhner d328934c9b mb/supermicro/x11ssm-f: drop NMI overrides
Drop the NMI overrides, since NMI now gets configured in gpio common
code. Also remove the variant init mechanism, which is unused now.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I02e0c679f9aafe33108320a8dfc62dcb278202ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48092
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04 00:10:52 +00:00
Michael Niewöhner 51f5ff6d27 soc/intel/{skl,cnl}: add NMI_{EN,STS} registers
Add NMI_EN and NMI_STS registers, so they can be configured for using
NMI gpios.

References:
- CMP-LP: Intel doc# 615146-1.2
- CMP-H:  Intel doc# 620855-002
- SPT-H:  Intel doc# 332691-003
- SPT-LP: Intel doc# 334659-005
- CNP-H:  Intel doc# 337868-002

Test: trigger NMI via gpio on Supermicro X11SSM-F did not work before
but now makes the Linux kernel complain about a NMI.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I4d57ae89423bdaacf84f0bb0282bbb1c9df94598
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48091
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04 00:10:38 +00:00
Michael Niewöhner 14512f9a9b soc/intel/common/block/gpio: add code for NMI enabling
Especially server boards, like the Supermicro X11SSM-F, often have a NMI
button and NMI functionality that can be triggered via IPMI. The purpose
of this is to cause the OS to create a system crashdump from a hang
system or for debugging.

Add code for enabling NMI interrupts on GPIOs configured with
PAD_CFG_GPI_NMI. The enabling mechanism is the same as SMI, so the SMI
function was copied and adapted. The `pad_community` struct gained two
variables for the registers.

Also register the NMI for LINT1 in the MADT in accordance to ACPI spec.

Test: Linux detects the NMI correctly in dmesg:
[    0.053734] ACPI: LAPIC_NMI (acpi_id[0xff] high edge lint[0x1])

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I4fc1a35c99c6a28b20e08a80b97bb4b8624935c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48090
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04 00:10:24 +00:00
Michael Niewöhner c3ab442cc1 intel/common/block/gpio: only reset configured SMI instead of all
Currently, when a SMI GPIO gets configured, the whole status register is
get written back and thus, all SMIs get reset.

Do it right and reset only the correspondig status bit of the GPIO to be
configured.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Iecf789d3009011381835959cb1c166f703f1c0cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48089
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04 00:09:59 +00:00
Martin Roth 6a62cc85e6 mb/google/zork: Set S0IX_SLP_L high in S0, low in S3
This is used as a signal to show the system state.  It hadn't been used
up to this point as we're not currently using S0i3, but the fingerprint
sensor will use it to go into a low power mode, so set it appropriately
on Trembyle.  Dalboz devices don't use the FPMCU, but set there as well
so that the state matches.

BUG=b:174695987
TEST=Verify GPIO state in S0 and S3 with the EC
BRANCH=Zork

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ibc725905909830d44f77c2498a26edf6d7a3dc05
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48255
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Vincent Palatin <vpalatin@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 23:44:28 +00:00
Nico Huber 361a5c0952 spi/flashconsole: Fix internal buffer overflow
Once the console's FMAP region is full, we stop clearing the line
buffer and `line_offset` is not reset anymore. Hence, sanity check
`line_offset` everytime before writing to the buffer.

The issue resulted in boot hangs and potentially a brick if the
log was very verbose.

Change-Id: I36e9037d7baf8c1ed8b2d0c120bfffa58c089c95
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48074
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 23:26:43 +00:00
Ao Zhong 20426858c5 mb/hp/z220_sff_workstation/Kconfig: Select MAINBOARD_USES_IFD_GBE_REGION
Select MAINBOARD_USES_IFD_GBE_REGION to make CONFIG_HAVE_GBE_BIN
(Add gigabit ethernet configuration) selection available. Without that
onboard Ethernet won't work.

Signed-off-by: Ao Zhong <hacc1225@gmail.com>
Change-Id: I9fe138363fc47254285ebaa4a7dbe5b94a0a8784
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48007
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03 23:20:43 +00:00
Felix Singer 424467c2a3 soc/intel/skylake: Add chipset devicetree
Set most of the devices to off to keep current behaviour.

Change-Id: Ic4dbd965c84c3679e42a181dea0e7e618c12fb97
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-03 21:55:42 +00:00
Julius Werner 20f5dcec63 cbfs: mcache: Fix end-of-cache check
After the mcache is copied into CBMEM, it has *just* the right size to
fit the final tag with no room to spare. That means the test to check if
we walked over the end must be `current + sizeof(tag) <= end`, not
`current + sizeof(tag) < end`.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I25a0d774fb3294bb4d15f31f432940bfccc84af0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-03 21:21:11 +00:00
Julius Werner fdabf3fcd7 cbfs: Add verification for RO CBFS metadata hash
This patch adds the first stage of the new CONFIG_CBFS_VERIFICATION
feature. It's not useful to end-users in this stage so it cannot be
selected in menuconfig (and should not be used other than for
development) yet. With this patch coreboot can verify the metadata hash
of the RO CBFS when it starts booting, but it does not verify individual
files yet. Likewise, verifying RW CBFSes with vboot is not yet
supported.

Verification is bootstrapped from a "metadata hash anchor" structure
that is embedded in the bootblock code and marked by a unique magic
number.  This anchor contains both the CBFS metadata hash and a separate
hash for the FMAP which is required to find the primary CBFS. Both are
verified on first use in the bootblock (and halt the system on failure).

The CONFIG_TOCTOU_SAFETY option is also added for illustrative purposes
to show some paths that need to be different when full protection
against TOCTOU (time-of-check vs. time-of-use) attacks is desired. For
normal verification it is sufficient to check the FMAP and the CBFS
metadata hash only once in the bootblock -- for TOCTOU verification we
do the same, but we need to be extra careful that we do not re-read the
FMAP or any CBFS metadata in later stages. This is mostly achieved by
depending on the CBFS metadata cache and FMAP cache features, but we
allow for one edge case in case the RW CBFS metadata cache overflows
(which may happen during an RW update and could otherwise no longer be
fixed because mcache size is defined by RO code). This code is added to
demonstrate design intent but won't really matter until RW CBFS
verification can be supported.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I8930434de55eb938b042fdada9aa90218c0b5a34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-12-03 00:11:08 +00:00