Commit Graph

37673 Commits

Author SHA1 Message Date
Angel Pons dbe8415245 mb/asrock/b85m_pro4/Kconfig: Default to 2 MiB CBFS
I often find myself having to increase the CBFS size so that TianoCore
fits. Raise the default CBFS size to 2 MiB to alleviate this issue.

Change-Id: I871bb95dee55cc5bad68bb6e71f89ddfa4823497
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46488
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-20 11:04:59 +00:00
Bill XIE 14ee0f94f3 mb/supermicro/x11-lga1151-series: add x11ssh-f board as a variant
This adds another X11 series board, the X11SSH-F, which is similiar to
X11SSH-TF but differs in PCIe interfaces/devices, ethernet interfaces.

Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I92c32bff861f0b5697aea52ff282fae76b3b78ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-20 09:00:18 +00:00
Huayang Duan 075ad63a4f mb/google/asurada: Init dram in romstage
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Ied350570a695cca1424a6562e41120bcaf467797
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44568
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-20 06:59:34 +00:00
Huayang Duan c90a9e68b7 soc/mediatek/mt8192: Do dram fast calibration
Load params from flash and use those params to do dram fast calibration.

Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: I45a4fedc623aecfd000c5860e0e85175f45b8ded
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-10-20 06:58:48 +00:00
Yidi Lin 79a812e536 ec/google/chromeec: Add wrappers to get/set the voltage
Add APIs to get and set the voltage for the target regulator.

BUG=b:147789962
BRANCH=none
TEST=emerge-asurada coreboot

Change-Id: I0e56df45fc3309c387b9949534334eadefb616b2
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-10-20 06:58:11 +00:00
Michael Niewöhner 5611cfd55f soc/intel/cnl: lock AES-NI feature if selected
Lock AES-NI (MSR_FEATURE_CONFIG) to prevent unintended changes of
AES-NI enablement as precaution, as suggested in Intel document
325384-070US.

Locking is enabled by default (as already done in SKL and Arrandale) and
may be disabled by the newly introduced Kconfig in the parent change.

Tested by checking the MSR.

Change-Id: I79495bfbd3ebf3b712ce9ecf2040cecfd954178d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-19 21:02:59 +00:00
Michael Niewöhner 2ffd219886 cpu/intel/common: add a Kconfig to control AES-NI locking
Add a Kconfig to be able to disable locking of AES-NI for e.g debugging,
testing, ...

Change-Id: I4eaf8d7d187188ee6e78741b1ceb837c40c2c402
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-19 21:02:51 +00:00
Michael Niewöhner 469a99b5c8 cpu/intel/common: only lock AES-NI when supported
Add a check to only lock AES-NI when AES is supported.

Change-Id: Ia7ffd5393a3e972f461ff7991b9c5bd363712361
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-19 21:02:04 +00:00
Michael Niewöhner 13b9149bab cpu/intel/common: rework AES-NI locking
Simplify the AES-NI code by using msr_set and correct the comment.

Change-Id: Ib2cda433bbec0192277839c02a1862b8f41340cb
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-19 21:01:53 +00:00
Michael Niewöhner 8b4a9380b5 soc/intel/skl,cpu/intel: copy AES-NI locking to common cpu code
Copy the AES-NI locking function to common cpu code to be able to reuse
it.

This change only copies the code and adds the MSR header file. Any
further rework and later deduplication on the platforms code is done in
the follow-up changes.

Change-Id: I81ad5c0d4797b139435c57d3af0a95db94a5c15e
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-10-19 21:01:04 +00:00
Felix Singer e92c84050b libpayload/storage: Enable STORAGE_64BIT_LBA
32-bit LBA limits drives, that have or emulate 512B sectors, to 2TiB
capacity. Therefore, enable the 64-bit support.

Change-Id: I663029a2137c5af3c77d576fe27db0b8fa7488a9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-19 16:07:49 +00:00
Felix Singer 70d73a85bf libpayload/storage: Enable all AHCI controllers by default
Since the list of tested controllers is not actively maintained, enable
all AHCI controllers by default. Also, improve the readability of its
help text by adding a comma to it.

Change-Id: If30f58f8380ab599f8985e85c64510dc88e96268
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-19 16:07:13 +00:00
Marshall Dawson 5dbe45e0f5 soc/amd/picasso: Skip SmmInfo to PSP on S3 resume
The PSP does not accept the SmmInfo command during a resume so
remove the call.

BUG=b:163017485
TEST=Run SST on trembyle, verify error message goes away
BRANCH=Zork

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ib75a20c9594bc331aa7abf77be95196085a3dbc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44398
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19 15:37:12 +00:00
Marshall Dawson 188f1bd5b8 soc/amd/picasso: Fix typo in SMU argument base
Correct the base address.  This should have no noticeable effect,
as SMC_MSG_S3ENTRY accepts no arguments and doesn't return.  The
argument writes were not getting to any target.

BUG=b:171037051
TEST=Run SST on morphius
BRANCH=Zork

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ie3402f743cf7d4f4f42b8afa3e8b253be4761949
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-19 15:00:31 +00:00
Nico Huber e4ab31bc7f mb/siemens/chili: Add Chili variant
This Chili mainboard is used in an all-in-one PC.

For more information see
https://www.secunet.com/fileadmin/user_upload/_temp_/importexport/Print/Factsheets/englisch/SINA_Workstation_H_Client_V_Factsheet_EN_Web.pdf

Change-Id: Ic7a5dccbb0d5b7bceb154fb050cf991254475f7b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39995
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19 13:24:41 +00:00
Elyes HAOUAS fa2db84a47 soc/rockchip/rk3288/include/soc/display.h: Add missing includes
Change-Id: I3e4824722d3add989a352122b365c2a73f3f703b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-10-19 07:12:07 +00:00
Elyes HAOUAS 78efb84509 soc/rockchip/rk3288/gpio.c: Use GPIOx_BASE macros
Change-Id: Idd16454884d6d847eb7ad071ff1d3e0c0de53e5b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-10-19 07:11:52 +00:00
Elyes HAOUAS 59143bbebd src/soc/samsung: Move common headers to "common/include/soc"
Change-Id: I8d54e157e4f0065fa0fd3df9df81a5b336031a99
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-10-19 07:11:32 +00:00
Thomas Heijligen 819d872606 mb/siemens/chili: Add new mainboard
The Chili base board is a ruggedized laptop with additional industrial
interfaces. So far, only booting and basic interfaces (USB, UART,
Video) are working with the original model, the "base" variant.
No further development is planned for this variant, as our primary
target was another one that will be added in a follow-up.

Change-Id: I1d3508b615ec877edc8db756e9ad38132b37219c
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-19 07:10:25 +00:00
James Chao 1d9b059c52 mb/google/octopus/variants/ampton: Add G2Touch touchscreen support
BUG=b:170703029
BRANCH=octopus
TEST=emerge-octopus coreboot

Signed-off-by: James Chao <james_chao@asus.corp-partner.google.com>
Change-Id: I2bf642963283b8a31a3bd9504c40541ca2f64b34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-10-19 07:10:09 +00:00
Michael Niewöhner 4e8baf9202 soc/intel/*: drop useless XTAL shutdown qualification code
The XTAL shutdown (dis)qualification bit already unconditionally gets
set to 1 by FSP for these platforms, making this code redundant.

Change-Id: I7fa4afb0de2af1814e5b91c152d82d7ead310338
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46016
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19 07:09:12 +00:00
Michael Niewöhner 4b6ff98e84 Revert "soc/intel/cannonlake: Enable ACPI timer emulation if PM timer is disabled"
This reverts commit e5269a8fd9.

Reason for revert: BIOS spec says, it's recommended to always enable
emulation (regardless of the OS version).

Change-Id: If0d7fa6f9766c7c4e2fa9e846c179adc6a4e1681
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-19 07:08:57 +00:00
Angel Pons 4eedd938fa util/abuild/abuild: Do not check out submodules
This force-downloads the qc_blobs repository, whose license is then
automatically accepted. This may also cause race conditions with git.

Change-Id: Id760172289abbe4d5ad5f230c9f1d3e1ab3908ec
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45607
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19 07:07:31 +00:00
Paul Menzel b9a5152cfa Documentation: Fix spelling of *assumptions*
Change-Id: I36e0e713647cfc0d25e6b4ead81aa212be530afb
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33742
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19 07:06:59 +00:00
Angel Pons 5c2d1906d9 sb/intel/ibexpeak: Use ARRAY_SIZE macro
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.

Change-Id: I01730e25ee78a74048f0b93faef00ebaee82ba77
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46529
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19 07:06:41 +00:00
Angel Pons 00e58c35c6 superio/nuvoton: Factor out equivalent Kconfig option
There's no need to have multiple Kconfig symbols which do the same
thing. Introduce `SUPERIO_NUVOTON_COMMON_COM_A` and update boards to use
the new symbol. To preserve alphabetical order in mainboard Kconfig,
place the new symbol above the Super I/O symbol (instead of below).

Change-Id: Ic0a30b3177a1a535261525638be301ae07c59c14
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46522
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19 07:06:20 +00:00
Angel Pons 9357ac3860 superio/nuvoton: Correct NCT6791D COM A mux toggle
Bit 6 of global CR 0x2a toggles the mux for COM B. Bit 7 works just like
on the other two Nuvoton Super I/Os, so fold the conditionals together.

Change-Id: I8cebe35587ae68cac93ed392342662678621efd6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-19 07:05:42 +00:00
Nico Huber e16971ac64 util/supermicro: Always include commonlib/bsd/compiler.h
We rely on `compiler.h` for definitions like `__packed`. Without it,
`smcbiosinfo.c` simply declared a global struct with that name, but
nothing was packed.

Found-by: reproducibility test

Change-Id: Ide055317115fc374a63812bcd3791445ca4f2dcc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-19 07:04:43 +00:00
Jes Klinke 5c80519466 volteer+vendorcode: Retrieve Cr50 version only via SPI
No recent Chromebooks have used I2C for TPM communication, and as a
result, a bug has crept in.  The ability to extract Cr50 firmware string
is only supported via SPI, yet code in mainboard and vendorcode attempt
to do so unconditionally.

This CL makes it such that the code also compiles for future designs
using I2C.  (Whether we want to enhance the I2C protocol to be able to
provide the version string, and then implement the support is a separate
question.)

This effort is prompted by the desire to use reworked Volteer EVT
devices for validating the new Ti50/Dauntless TPM.  Dauntless will
primarily be using I2C in upcoming designs.

BRANCH=volteer
TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x

Change-Id: Ida1d732e486b19bdff6d95062a3ac1a7c4b58b45
Signed-off-by: jbk@chromium.org
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-10-19 07:03:37 +00:00
Shelley Chen d5faa90df5 security/vboot: Rename mem_init.h to mrc_cache_hash_tpm.h
As ongoing work for generalizing mrc_cache to be used by all
platforms, we are pulling it out from fsp 2.0 and renaming it as
mrc_cache_hash_tpm.h in security/vboot.

BUG=b:150502246
BRANCH=None
TEST=emerge-nami coreboot chromeos-bootimage

Change-Id: I5a204bc3342a3462f177c3ed6b8443e31816091c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-19 07:01:04 +00:00
Benjamin Doron dc667980f8 soc/intel/skylake: Do not let FSP set the subsystem IDs
The subsystem ID registers are read/write-once. Writes by coreboot will
not take effect if FSP sets them.

Note that FSP sets one device ID for the SA devices and another for PCH
devices. coreboot will copy individual vendor and device IDs if
subsystem is not provided.

Change-Id: I9157fb69f2a49dfc08f049da4b39fbf86614ace3
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-19 07:00:32 +00:00
John Zhao 33f234e356 soc/intel/cannonlake: Fix memory corruptions
Coverity detects source memory is overrun. Fix this issue by using
the CONFIG_MAX_ROOT_PORTS value to avoid memory corruption.

Found-by: Coverity CID 1429762 1429774
TEST=None

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Icc253eb9348d959a9e9e69a3f13933b7f97d6ecc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-19 07:00:05 +00:00
Michael Niewöhner b37d4b95d3 soc/intel/common/acpi: correct indentation
Test: built google/volteer with `abuild --timeless` - SHA1 hashes match
Change-Id: Ice6cef402dfcc33f1fc7fdced66d38c380d338e5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-19 06:59:48 +00:00
Rob Barnes e5397bd116 Revert "mb/google/zork/dalboz: Increase eMMC initial clock frequency"
This reverts commit c4a5acdabc.

Reason for revert: Dalboz is missing pull-up on cmd line, so 400khz is not possible.

TEST=Boot Dalboz
BUG=b:159823235, b:169940175
BRANCH=zork

Change-Id: I89653bfeefa522c17ee2d736215bc22aa445871c
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2020-10-19 06:58:53 +00:00
Karthikeyan Ramasubramanian 94ce8c3b3d mb/google/dedede/var/waddledee: Enable GPIO based I2C Multiplexer
The camera sensor component chosen for UFC and WFC have an address
conflict. Resolve it by enabling GPIO based I2C Multiplexer. Also
configure the GPIO that is used as select line.

BUG=b:169444894
TEST=Build and boot waddledee to OS. Ensure that the ACPI identifiers
are added for I2C devices multiplexed using I2C MUX under the
appropriate scope.

Change-Id: I9b09e063b4377587019ade9e6e194f4aadcdd312
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-19 06:58:03 +00:00
Karthikeyan Ramasubramanian bf089d2a62 drivers/i2c/gpiomux: Add chip driver for multiplexed I2C bus
This chip driver adds ACPI identifiers for multiplexed I2C bus that are
selected using GPIO. The multiplexed bus device defines the address
to select the I2C lines. These ACPI identifiers are consumed by the
i2c-mux-gpio kernel driver:
https://www.kernel.org/doc/html/latest/i2c/muxes/i2c-mux-gpio.html

BUG=b:169444894
TEST=Build and boot to OS in waddledee. Ensure that the ACPI identifiers
are added in appropriate context.
Scope (\_SB.PCI0.I2C3.MUX0)
{
    Device (MXA0)
    {
        Method (_STA, 0, NotSerialized)  // _STA: Status
        {
            Return (0x0F)
        }

        Name (_ADR, Zero)  // _ADR: Address
    }
}

Scope (\_SB.PCI0.I2C3.MUX0)
{
    Device (MXA1)
    {
        Method (_STA, 0, NotSerialized)  // _STA: Status
        {
            Return (0x0F)
        }

        Name (_ADR, One)  // _ADR: Address
    }
}

Change-Id: If8b983bc8ce212ce05fe6b7f01a6d9092468e582
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-19 06:57:52 +00:00
Karthikeyan Ramasubramanian cbc29a2160 drivers/i2c: Add chip driver for GPIO based I2C multiplexer
Add identifiers in ACPI tables for GPIO based I2C multiplexer. The
multiplexer device defines the GPIO resource used to select the
adapter/bus lines. The multiplexer adapter device defines the address
to select the adapter/client lines. These ACPI identifiers are consumed
by the i2c-mux-gpio kernel driver:
https://www.kernel.org/doc/html/latest/i2c/muxes/i2c-mux-gpio.html

BUG=b:169444894
TEST=Build and boot waddledee to OS. Ensure that the ACPI identifiers
are added for I2C devices multiplexed using I2C MUX under the
appropriate scope. Here is the output SSDT:
Scope (\_SB.PCI0.I2C3)
{
    Device (MUX0)
    {
        Name (_HID, "PRP0001")  // _HID: Hardware ID
        Method (_STA, 0, NotSerialized)  // _STA: Status
        {
            Return (0x0F)
        }

        Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
        {
            GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly,
                "\\_SB.PCI0.GPIO", 0x00, ResourceConsumer, ,
                )
                {   // Pin list
                    0x0125
                }
        })
        Name (_DSD, Package (0x02)  // _DSD: Device-Specific Data
        {
            ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
            Package (0x02)
            {
                Package (0x02)
                {
                    "compatible",
                    "i2c-mux-gpio"
                },

                Package (0x02)
                {
                    "mux-gpios",
                    Package (0x04)
                    {
                        \_SB.PCI0.I2C3.MUX0,
                        Zero,
                        Zero,
                        Zero
                    }
                }
            }
        })
    }
}

Change-Id: Ib371108cc6043c133681066bf7bf4b2e00771e8b
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-19 06:57:29 +00:00
Elyes HAOUAS eac283fb0c soc/amd/common/acpi: Convert to ASL 2.0 syntax
Change-Id: I3d5f595ebbc865501b086aebee1f492b4ab15ecd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-19 06:55:47 +00:00
Jakub Czapiga a01138b7a4 lib/imd: move struct definitions to a new header file
Make IMD private structures definitions accessible by other units.

To test IMD API correctness there is a need to access its internal
structure. It is only possible when private implementation is visible
in testing scope.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Iff87cc1990426bee6ac3cc1dfa6f85a787334976
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-10-19 06:55:03 +00:00
Ronak Kanabar 72cd6b0d01 vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2376
The headers added are generated as per FSP v2376.
Previous FSP version was 2295.
Changes Include:
- add GpioOverride UPD in Fspm.h
- add new header FirmwareVersionInfo.h

Cq-Depend: TBD
Change-Id: I65c03d8eda11664541479983c7be11854410e1c6
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45899
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19 06:54:21 +00:00
Kangheui Won 362ec8dee2 amd/picasso/verstage: replace rsa accel with modexp
Replace vb2ex_hwcrypto_rsa_verify_digest with vb2ex_hwcrypto_modexp.

Instead of using hardware acceleration for whole RSA process,
acclerating only calculation part(modexp) increases transparency
without affecting boot time.

BUG=b:169157796
BRANCH=zork
TEST=build and flash, check time spent on RSA is not changed

Change-Id: I085f043bf2014615d2c9db6df0b7947ee84b9546
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45987
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19 06:53:51 +00:00
Duncan Laurie 5b6ec3e4dc mb/google/volteer: Enable USB4 retimer driver
Enable the USB4 retimer driver with GPP_H10 as the power control.

Change-Id: I166bc477f94c159bb411620a6bf77b5d1f194fb2
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-10-19 06:52:04 +00:00
Duncan Laurie 2cc126be2c drivers/intel/usb4: Add driver for USB4 retimer device
The USB4 retimer device needs to declare a _DSM with specific functions
that allow for GPIO control to turn off the power when an external
device is not connected.  This driver allows the mainboard to provide
the GPIO that is connected to the power control.

BUG=b:156957424

Change-Id: Icfb85dc3c0885d828aba3855a66109043250ab86
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44918
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19 06:51:40 +00:00
Hung-Te Lin b22dc1daf4 mb/google/kukui: Support SKU from camera EEPROM
To support camera second source GC5035 for kodama, add world facing
camera id as part of the sku id, which is determined by the data in
camera EEPROM. For models other than kodama, the camera id is always 0
and hence the sku id is unchanged.

BUG=b:144820097
TEST=emerge-kukui coreboot
TEST=Correct WFC id detected for kodama with GC5035 camera
BRANCH=kukui

Change-Id: I63a2b952b8c35c0ead8200d7c926e8d90a9f3fb8
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45811
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19 06:50:46 +00:00
Yu-Ping Wu e68ef7d75c drivers/camera: Add config CHROMEOS_CAMERA
Add cros_camera_info struct for camera information, and
check_cros_camera_info() for checking the magic, CRC and version.

BUG=b:144820097
TEST=emerge-kukui coreboot
BRANCH=kukui

Change-Id: I1215fec76643b0cf7e09433e1190e8bd387e6953
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46042
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19 06:50:20 +00:00
Wisley Chen f580d9ffef mb/google/volteer/elemi: Add memory.c for DDR4
Add new memory.c to support DDR4 memory types.

BUG=b:170604353
TEST=emerge-volteer coreboot chromeos-bootimage

Change-Id: If96b0bda0ce95766f0957c37aa7cbecefc9c03e0
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-10-19 06:48:44 +00:00
Angel Pons 42aa2cb94a mb/purism/librem_skl: Clean up FSP-M RCOMP settings
There's no need to use static functions to fill these settings in. Also,
add missing include for <stdint.h> and initialize `mem_cfg` in one line.

Change-Id: I82b0997846d4ec40cf9b1a8ebfb1e881b194e078
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46252
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19 06:48:10 +00:00
John Su 965439be12 mb/google/zork/var/vilboz: update dptc stapm time
Update dptc setting:
Stapm_time_constant		1400

BUG=b:170696020
BRANCH=zork
TEST=emerge coreboot and check "Stapm_time_constant"

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I61d9e00a9d098ad9699b8cf89e70d11de2b95ffd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-10-19 06:47:57 +00:00
Sridhar Siricilla d6ffbf0e43 soc/intel/tigerlake: Reflow long lines
Use the 96 character limit.

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I43d77db1f81d72aa13f3a702abff490a68a52bd7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-10-19 06:47:30 +00:00
Marc Jones b9365ef377 soc/intel/xeon_sp/cpx: Implement platform_fsp_silicon_init_params_cb
platform_fsp_silicon_init_params_cb is called by the fsp driver and
calls mainboard_silicon_init_params which sets the mainboard
PCH GPIOs.

Change-Id: Icf401e76741a6a7484295e999ddd566fe9510898
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46309
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Bryant Ou <bryant.ou.q@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-19 01:35:50 +00:00