Commit Graph

5660 Commits

Author SHA1 Message Date
Sven Schnelle c045b4cc45 X60/T60: disable USB power during suspend
Change-Id: I11afba5d7531132a0274e55e8a478985a0ef956f
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/38
Tested-by: build bot (Jenkins)
2011-06-16 17:20:56 +02:00
Sven Schnelle 86e1aea3e6 Lenovo H8 EC: add usb_power_enable()
Can be used to disable/enable Power output on USB ports.

Change-Id: I5eb52b33c9e3359b0e5874bda2c0c8d75c196bc2
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/37
Tested-by: build bot (Jenkins)
2011-06-16 17:00:12 +02:00
Sven Schnelle bfe8e5186e SMM: don't overwrite SMM memory on resume
Overwriting the SMM Area on resume leaves us with
all variables cleared out, i.e., the GNVS pointer
is no longer available, which makes SMIF function
calls impossible.

Change-Id: I08ab4ffd41df0922d63c017822de1f89a3ff254d
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/34
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-15 23:11:44 +02:00
Sven Schnelle b629d14bec i945 GMA: restore tft brightness from cmos
Change-Id: Iaf10f125425a1abcf17ffca1d6e246f955f941cc
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/24
Tested-by: build bot (Jenkins)
2011-06-15 19:40:24 +02:00
Sven Schnelle d4dc9a5a03 Remove old ACPI code
it isn't used anywhere, and could be fetched from git/svn history if
needed.

Change-Id: Iaa2ba39af531d0389d7ab1110263ae7ecaa35c70
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/35
Tested-by: build bot (Jenkins)
2011-06-15 19:03:39 +02:00
Sven Schnelle d8c68a9d08 i82801gx: replace cafed00d/cafebabe by defines
We're using '0xcafed00d' all over the code as magic for ACPI S3
resume. Let's add a define for that. Also replace 0xcafebabe by
a define.

Change-Id: I5f5dc09561679d19f98771c4f81830a50202c69f
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/33
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-06-15 15:15:07 +02:00
Stefan Reinauer 5eef65bbbf Update README with newer version of the text from the web page
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I4f181979ca5e47b27731c681a320b34cbecc0027
Reviewed-on: http://review.coreboot.org/19
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Reviewed-by: Sven Schnelle <svens@stackframe.org>
2011-06-15 10:16:33 +02:00
Sven Schnelle 8b39e07d04 X60: handle EC events in SMM if ACPI is disabled
Change-Id: I0fee890bd2d667b54965201f5c90da3656d7af5c
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/27
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-15 08:51:36 +02:00
Sven Schnelle 4297a9a101 X60: trigger save cmos on volume/brightness change
Change-Id: I020e06bc311c4e4327c9d3cf2c379dc8fe070a7a
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/25
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-15 08:51:18 +02:00
Sven Schnelle d29e5bb933 CMOS: add set_option()
Change-Id: I584189d9fcf7c9b831d9c020ee7ed59bb5ae08e8
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/23
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-06-15 08:44:15 +02:00
Sven Schnelle d40d4f7712 X60/T60: set CMOS defaults
Change-Id: I5789a03898cdbade67887c0389aab5c773f867d9
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/26
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-13 21:58:52 +02:00
Marshall Buschman eab1db192f ASRock/E350M1: Skip memory clear for boot time reduction
Applying Scott's patches to e350m1, svn r6600:
Memory clear is not required for non-ECC boards.

Change-Id: Ia1a7c926611de72351434cbdc1795ed10bc56ed1
Signed-off-by: Scott Duplichan <scott@notabs.org>
Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Reviewed-on: http://review.coreboot.org/20
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2011-06-12 19:27:34 +02:00
Sven Schnelle 0f9cd43514 X60/T60: fix return value of mainboard_io_trap_handler()
The handler should return 1 if it handled the request. The current
code returns 0, which causes 'Unknown function' logs.

Change-Id: Ic296819a5f8c6f1f97b7d47148182226684882a0
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/29
Tested-by: build bot (Jenkins)
2011-06-12 17:28:10 +02:00
Sven Schnelle 5d9a83c9f0 log ec data with DEBUG_SPEW
Change-Id: I26424e80c776bfc134528f42e87fde42d6a13108
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/28
Tested-by: build bot (Jenkins)
2011-06-12 17:13:51 +02:00
Jonathan A. Kollasch fed129b0d5 Add ACPI automatic PIC/APIC interrupt routing logic for ck804
Change-Id: I2d462ca1220ea31af243c7a58a1dc33c39e9c840
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/13
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-10 19:44:04 +02:00
Uwe Hermann c55bcdecf7 superiotool: Cosmetics and coding style fixes.
Change-Id: Iacda2a9e37635d5cffc5004caf588ef3e5e09b5e
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Reviewed-on: http://review.coreboot.org/18
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2011-06-09 21:26:47 +02:00
Sven Schnelle 1b8068e244 H8 EC: add volume CMOS setting
Change-Id: I5332c8fa52556db34dfb5e772bf544f0323e823d
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/12
Tested-by: build bot (Jenkins)
2011-06-09 10:05:46 +02:00
Peter Stuge cc5dd98c1b util/crossgcc: Add build-without-gdb Makefile target
Change-Id: I5d02f1a23e54aa67be0cc01d921898c28c22f8e4
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/16
Tested-by: build bot (Jenkins)
Reviewed-by: Marshall Buschman <mbuschman@lucidmachines.com>
2011-06-09 06:09:17 +02:00
Peter Stuge ceacd77356 util/crossgcc: Add buildgcc -G and --skip-gdb options
Change-Id: Ic31130774ad56abf0b5498b04b4890348352a621
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/15
Tested-by: build bot (Jenkins)
Reviewed-by: Marshall Buschman <mbuschman@lucidmachines.com>
2011-06-09 06:09:17 +02:00
Peter Stuge 0b6b4d6d43 Change make crossgcc to build without gdb by default
Using gdb with coreboot is not (yet) very common, so at least for
now it makes sense to not build gdb by default. A make crosstools
target is also added, which runs the full build in util/crossgcc
and thus generates a toolchain with both compiler and debugger.

Change-Id: I939ebcd06ae9a1bc485fd18e70cac98112d3bbbf
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/17
Tested-by: build bot (Jenkins)
Reviewed-by: Marshall Buschman <mbuschman@lucidmachines.com>
2011-06-09 06:09:17 +02:00
Marc Jones 486e03228e Revert changes to set the sb800 to AHCI mode.
Seabios doesn't have this support included yet,
which causes the generic Persimmon and other CIMx
sb800 platforms to not boot.

Change-Id: If07328b7c62d7fc314647adce8fab983ed327854
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/14
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2011-06-09 01:07:01 +02:00
Cristian Măgherușan-Stanciu fe0b4c5916 Add basic .gitignore
Ignore directories created by abuild, jenkins, payloads and crossgcc.

Change-Id: I7d4145fc1e54a10ffdc4b884d8b8f0ae53e615c6
Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Signed-off-by: Peter Stuge <peter@stuge.se>
Reviewed-on: http://review.coreboot.org/10
Tested-by: build bot (Jenkins)
2011-06-09 00:13:10 +02:00
Sven Schnelle 51e1bc3a7b T60/PMH7: move 'touchpad' option to pmh7
This option is PMH7 specific, and should be moved there,
so all Notebook utilizing a PMH7 have this option.
For Thinkpads without Touchpad (like the X60), simply
don't add 'touchpad' to cmos.layout.

Change-Id: Icdd0093670d565f1b16e2483aa286f4d63ccc52a
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/6
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-07 22:43:14 +02:00
Sven Schnelle e261807bac i82801gx: enable ACPI during S3 resume
disabling ACPI during S3 wakeup breaks ACPI wakeup, as the
Host OS is assuming that ACPI is enabled.

Change-Id: I8ced72c4b553d41a57f26d64998118e8a77621f8
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/7
Tested-by: build bot (Jenkins)
2011-06-07 22:11:46 +02:00
Sven Schnelle f4dc1a73e4 SMM: add defines for APM_CNT register
in the current code, the defines for the APM_CNT (0xb2) register
are duplicated in almost every place where it is used. define those
values in cpu/x86/smm.h, and only include this file.

And while at it, fixup whitespace.

Change-Id: Iae712aff53322acd51e89986c2abf4c794e25484
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/4
Tested-by: build bot (Jenkins)
2011-06-07 22:01:29 +02:00
Patrick Georgi bb60528e73 Add "gitconfig" make target to simplify gerrit configuration
"make gitconfig" installs the gerrit commit-msg hook and validates
that user.name and user.email are configured.

No data will be overwritten.

Change-Id: I49ec98538574866e7ad6238ff3d02b9c1beef1bb
Reviewed-on: http://review.coreboot.org/2
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2011-06-07 21:46:08 +02:00
Sven Schnelle b924eb45f1 T60: fix touchpad option
Code used 'int' as return type, but the cmos option is only one
bit. get_option returned with the value in bit 0-7, but all remaining
bits were left unitialized by get_option(). fix this by using char
as type.

Change-Id: I60e609164277380f936f66c99ef9508fa6a6b67c
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/5
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-06-07 12:50:42 +02:00
Stefan Reinauer 44c1d3111b re-indent, so files conform to coding guidelines.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

Change-Id: If840164fa0e2b6349ba920edf06386ba1fe08aab
Reviewed-on: http://review.coreboot.org/8
Tested-by: build bot (Jenkins)
Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
2011-06-07 11:58:31 +02:00
Sven Schnelle c21b054acc SMM: add mainboard_apm_cnt() callback
motherboards can use this hook to get notified if someone writes
to the APM_CNT port (0xb2). If the hook returns 1, the chipset
specific hook is also skipped.

Change-Id: I05f1a27cebf9d25db8064f2adfd2a0f5759e48b5
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/3
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2011-06-06 17:56:13 +02:00
Patrick Georgi 140a990a61 Teach abuild to emit JUnit formatted build reports
Jenkins can produce reports from JUnit test cases, so we fake testcases
for each board.

Change-Id: I34d46d15c83f4f04d2228f302eb626b261ac098d
Reviewed-on: http://review.coreboot.org/1
Tested-by: build bot (Jenkins)
Reviewed-by: Sven Schnelle <svens@stackframe.org>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-06-06 17:13:50 +02:00
Stefan Reinauer fb38eb01ca WARNINGS_ARE_ERRORS is y per default, don't set it twice.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6637 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04 16:30:27 +00:00
Peter Stuge d1760c834a Port persimmon r6594 to e350m1: Cosmetic cleanup
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6636 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04 15:48:14 +00:00
Peter Stuge f8e33e356f Port persimmon r6593 to e350m1: Remove unused Kconfig options
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6635 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04 15:47:56 +00:00
Peter Stuge 2334c8d2b7 Port persimmon r6592 to e350m1: Update GPP port configuration
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6634 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04 15:47:30 +00:00
Marshall Buschman 314f4a2077 Port persimmon r6591 to e350m1: ROM cache early
Enable rom cache early to reduce boot time.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6633 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04 15:47:05 +00:00
Marshall Buschman 1a7699f42a Port persimmon r6590 to e350m1: Work around memory allocation problem
Fix memory allocation problem in amdInitLate. Disabled until further debug.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6632 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04 15:46:50 +00:00
Marshall Buschman bb2ca2bafd Port persimmon r6589 to e350m1: Strip down AGESA options
Remove some non-essential agesa options to reduce boot time.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6631 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04 15:46:32 +00:00
Marshall Buschman af85315707 Port persimmon r6588 to e350m1: VGA framebuffer
Declare legacy video frame buffer so that Windows generic VGA driver will work.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6630 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04 15:46:13 +00:00
Marshall Buschman adc89b033e Port persimmon r6587 to e350m1: RTC is not PIIX4 compatible
Declare RTC as not PIIX4 compatible to match AMD hardware.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6629 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04 15:45:46 +00:00
Marshall Buschman ac4bef4907 Port persimmon r6586 to e350m1: FADT revision
Make fadt revision match its length. Solves Windows 7 checked build assert.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6628 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04 15:45:29 +00:00
Marshall Buschman 552ad9f75e Port persimmon r6584 and r6601 to e350m1: SPI prefetch early
Enable SPI cacheline prefetch early to reduce boot time.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6627 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04 15:45:12 +00:00
Marshall Buschman fd460e620e Port persimmon r6583 to e350m1: pstate 0 early
Switch processor cores to pstate 0 early to reduce boot time.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6626 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04 15:44:54 +00:00
Marshall Buschman b3ee0d6bd6 Port persimmon r6582 to e350m1: 33 MHz SPI read early
Enable 33 MHz fast mode SPI read early to reduce boot time.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6625 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04 15:44:31 +00:00
Peter Stuge 69e1bfcf34 Port persimmon r6578 and r6596 to e350m1: MMCONF base
Remove multiple mmconf settings and just use kconfig setting.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04 15:44:14 +00:00
Marshall Buschman eb92b5ad64 Port persimmon r6574 to e350m1: MMCONF size
Size mmconf according to CONFIG_MMCONF_BUS_NUMBER.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6623 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04 15:43:56 +00:00
Marshall Buschman 5a403191cb Port persimmon r6573 to e350m1: VGA, PCI MMIO and SB800 legacy
1) Use D18F1xF4 VGA Enable to simplify legacy video I/O support.
2) Extend PCI MMIO limit from dfffffff to fecfffff.
3) Add AMD recommended non-posted mapping for SB800 legacy devices.

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6622 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04 15:43:38 +00:00
Marshall Buschman 6d5ee2d80a Port persimmon r6572 to e350m1: I/O APIC ID
1) Set I/O APIC ID according to BKDG recommendation
2) Correct I/O APIC ID reported by mptable

Signed-off-by: Marshall Buschman <mbuschman@lucidmachines.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6621 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04 15:43:15 +00:00
Peter Stuge e1898b5fa1 vt8237r: Simplify bootblock init to work around nested if() romcc problem
During the hackathon in Prague we discovered that romcc has a problem
compiling the previous nested if() statements correctly. This patch
makes the code a little simpler, and indeed works around the romcc issue.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6620 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-04 15:40:12 +00:00
Marc Jones 471f103e53 This patch sets max freq defaults for ddr2 and ddr3for fam10.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Scott Duplichan <scott@notabs.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6619 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-03 19:59:52 +00:00
Alexandru Gagniuc 23d3dfaa96 Correct wrong PCI ID for VIA K8M890 Chrome.
With the K8T800/M800 patch from r6367 the PCI IDs for the VIA chrome were
moved to pci_ids.h. The PCI ID for K8M890 chrome was copied incorrectly.
(3220 instead of 3230). This patch defines the correct PCI ID for this device.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6618 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-03 19:46:25 +00:00