This board doesn't have a UART on the super I/O. Selecting this option
speeds up boot time from ~493 ms to ~416 ms.
Change-Id: I1d84f373831381da79022638e1082adf68f47aad
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Field 'OEMID' & "OEM Table ID" are related to DSDT table
not to mainboard.
So use macro to set them respectvely to "COREv4" and
"COREBOOT".
Change-Id: I060e07a730e721df4a86128ee89bfe168c69f31e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Guckian
DSDT revision is =1 for ACPI v1 and =2 for greater ACPI version.
This will cause the AML interpreter to use 32-bit integers and math
if the version is 1, and 64-bit if the version is >=2.
Current spec version is 2 for ACPI 6.2-a.
Change-Id: I77372882d5c77b7ed52dcdd88028403df6f6fa7f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29626
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Used default console log level is 7 in src/console/Kconfig.
So let cmos.default use the same level as default.
Change-Id: Ia39ee457a8985142f6e7a674532995b11cb52198
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
The file `data.vbt` matches the VBT in the latest version of the vendor
firmware (version 3603). Tested with Linux 4.9 and everything works as
expected.
Change-Id: I8e3b1d274ac0df63989d966f477013e780611fa1
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/28050
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since only a handful of boards have descriptor blobs in the tree, it makes no
sense to have `HAVE_IFD_BIN` enabled by default then disabled on each mainboard.
This patch flips the default value of said variable, rendering all current
overrides unnecessary. The few boards which have an IFD in the blobs repo use
`select HAVE_IFD_BIN` to enable adding the IFD by default.
Since `HAVE_ME_BIN` depends on `HAVE_IFD_BIN`, the former has been removed
alongside the latter, and has been added to the boards with a ME blob as
`select HAVE_ME_BIN`.
Both `HAVE_IFD_BIN` and `HAVE_ME_BIN` have been removed from autoport as well.
Change-Id: I330c4886f8bea4b1a8ecad6505a0e5cc381654d1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/27218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Move inline function where they belong to. Fixes compilation
on non x86 platforms.
Change-Id: Ia05391c43b8d501bd68df5654bcfb587f8786f71
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25720
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested with GRUB 2.02 as a payload, booting Debian GNU/Linux 9.3 with
kernel 4.9. This code is based on the output of autoport.
Working:
- S3 suspend/resume
- USB
- Gigabit Ethernet
- integrated graphics
- PCIe
- SATA
- eSATA
- PS/2 port (only a mouse has been tested)
- hardware monitor
- onboard audio
- front panel audio
- native raminit (2 x 4GB + 2 x 8GB, DDR3-1333)
- native graphics init with libgfxinit
- EHCI debug. The debug port is the port closest to the HDMI port.
- flashrom, using the internal programmer. Tested with coreboot,
untested with the vendor firmware.
- NVRAM settings. Only `gfx_uma_size` and `debug_level` have been
tested with values different from the default.
Untested:
- VGA BIOS for graphics init
- PCIe graphics
- S/PDIF audio
Not working:
- "clear CMOS" button
The CPUTIN sensor on the Super I/O is not connected. The PECI agent is
likely connected instead to give CPU temperature readings. However,
there does not appear to be enough information in the publicly available
datasheets to fully set up the PECI agent. As a result, there is
currently no accurate, automatic fan control via the Super I/O.
Change-Id: I1fc7940bb139623a5a0fde984c023deca9b551f2
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/24971
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
