Commit Graph

53560 Commits

Author SHA1 Message Date
Fred Reitberger c53ab57017 mb/google/myst: Disable APOB NV
Disable the APOB cache for only Myst, and re-enable APOB for other
Phoenix SOC mainboards.

BUG=b:290763369
TEST=verify APOB cache is disabled

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ie611e0b84611b2f50c989c75612fc2186b2dbfdf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76567
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-07-24 11:19:53 +00:00
Fred Reitberger 7bb960d7df soc/amd/common/block/apob: Add Kconfig option to disable APOB NV
Add Kconfig option to disable the non-volatile APOB cache for a
mainboard using an SOC that supports APOB.

BUG=b:290763369
TEST=verify APOB cache is disabled when selected

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I0170355bbf29ea6386fa69a318e61f057b9a9a3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76566
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-07-24 11:19:37 +00:00
Fred Reitberger 5f5e73cddd soc/amd/phoenix/Makefile.inc: Enable amdfw manifest
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ic030f91bbfd7226d7adbbe83a2f9e7930af46207
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-07-24 11:18:25 +00:00
Daniel_Peng ed7a474db5 mb/google/dedede: Add ALC5650 to AUDIO_AMP in devicetree
Mapping to the fw_config of AUDIO_AMP in dedede,
and set new AUDIO_AMP configuration of ALC5650 as value 4.

BUG=b:284060672
BRANCH=dedede
TEST=build pass

Change-Id: Ic3dccd09d3ba1619cce2ac0d5f123badbeeaccdc
Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-24 03:57:33 +00:00
Nico Huber b37c51d3b6 toolchain.inc: Set CCACHE_COMPILERCHECK=mtime
From ccache(1):

mtime
  Hash the compiler’s mtime and size, which is fast. This is the default.

Hashing the compiler binary's content would only be necessary when we
expect different binaries of the same size with the same path (e.g.
during a compiler bootstrap) and wrong modification timestamps (might
happen when checking an older version out of a (package) repository).
Neither should be the case during our builds. And even if everything
fails at once, chances are additionally low that a wrong cache hit
would cause a problem.

tl;dr we're building and testing firmware, not toolchains.

Change-Id: I264a72c628559384fcc2060d777c52af927d5e14
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-07-23 22:39:53 +00:00
Martin Roth baf82808ae util/docker: Update libncurses5-dev to libncurses-dev package
The libncurses5-dev package no longer seems to be available in debian
sid. It's been marked as a transitional package, pointing to
libncurses-dev (ncurses 6) for since 2018, so this patch updates the
package to the new name.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I81e1a174ab25f573a7d7711eeeb26ef22fd3854b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-07-23 20:59:19 +00:00
Arthur Heymans 2e3cb63925 acpi.c: Add functions to create GTDT
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ica6b2d79d61558706998edbbaee185125ff5b36c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-07-23 18:26:13 +00:00
Maximilian Brune c202be793f payloads/external/LinuxBoot: Clean up
There were some issues with the current Linuxboot Makefiles.
- multithreaded compilation didn't work, because some prerequisites
  were missing
- initramfs wasn't added for x86 qemu boot.
- riscv support was incomplete

It began with separate patches, but resulted in a clean up patch, that
is hard to separate. The most important changes are the following:
- Instead of phony targets, actual files are now used as prerequisites
- riscv can now be used as target
- initramfs works now also for x86
- instead of querying the most recent version from the internet, I set a
  known working version (because I tested it) that can be customized
  and/or upgraded in the future. The reasons:
      - querying the version from the internet requires a constant
        connection to the internet even after linux kernel is already
        build (aka subsequent builds).
      - one usually wants to use a known working version, but optionally
        still have the posibillity to choose a custom one. This patch
        introduces this possibility in its most simple form.
- I removed as much ifeq statements as possible and moved that
  responsibility to Kconfig, because they tend to make the
  Makefile less readable.

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I25e757108e0dd473969fe5a192ad0733f1fe6286
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76150
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-23 18:24:39 +00:00
Subrata Banik 449c6d981c mb/google/rex/var/screebo: Reduce TCC from 90°C to 80°C
This patch increases the `tcc_offset` to reduce the TCC
(Thermal Control Circuit) activation temperature to avoid running
into abrupt power off during power cycle tests.

On Intel processors, the core frequency can be by an HW agent when
the current temperature reaches the TCC activation temperature.

The default TCC activation temperature is specified by MSR_IA32_TEMPERATURE_TARGET (which is 90°C for google/rex variants).

However, this patch adjusted the TCC by specifying an offset in
degrees C (i.e., using `tcc_offset` from variant override device tree).

Note: The bigger the TCC offset is, the lower the effective TCC activation temperature would be, to ensure that processors can be throttled earlier before the system critical overheats.

BUG=b:283008762
TEST=Able to perform power cycle on google/screebo w/o any crash/shutdown.

Change-Id: Ib19703877dbbfc26b2d9f538dda4f10c27cf872d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76658
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-22 17:50:50 +00:00
Bora Guvendik 4a58d14506 soc/intel/alderlake: Hook up UPD PchHdaSdiEnable
Hook the PchHdaSdiEnable UPD so that mainboard can change the
settings via devicetree. PchHdaSdiEnable UPD enable HDA SDI lanes.

BUG=b:268546941
TEST=Verified the settings on google/brya using debug FSP logs.

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I82bbfa5442936aefa53f8826e395b7ce75c895a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-07-21 19:17:41 +00:00
Rob Barnes 0572d557ac mb/google/volteer: Add EC_HOST_EVENT_PANIC to SCI mask
Adding EC_HOST_EVENT_PANIC to SCI mask allows the EC to interrupt the
Kernel when an EC panic occurs. If system safe mode is also enabled
on the EC, the kernel will have a short period to extract and save info
about the EC panic.

BUG=b:290985698
BRANCH=firmware-volteer-13672.B
TEST=Observe kernel ec panic handler run when ec panics

Change-Id: I87173f93d0e47baa816d15dad0777007342b4fdb
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-21 13:52:15 +00:00
Subrata Banik f9419eadf1 mb/google/rex: Use BOARD_GOOGLE_MODEL_REX instead variant name
Choose BOARD_GOOGLE_MODEL_REX while setting up the default config value
for variants created using google/rex model.

TEST=Able to build and boot google/rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I107f4e375b5c9e9c0fb80c4d396164c10c1fc1e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-21 07:58:25 +00:00
Dinesh Gehlot 648ad8c5b1 mb/google/rex: Create rex4es variant
This patch creates a new variant rex4es. The new variant will support ESx samples. The existing rex variant will support the QS samples.

BUG=b:290732344
TEST=Able to build google/rex4es board and boot on target hardware.

Change-Id: I25dd1f42ee812f47289da0c2ef7aa79d6f340d48
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-21 07:57:59 +00:00
Subrata Banik ecb2a84690 mb/google/rex: Create a `rex` model for easier variant integration
This patch creates  a rex model so that other variants developed using
`rex` baseboard are easy to land without duplicating the config
selection.

So far, `rex0` and `rex_ec_ish` are developed using the `rex` model.
The plan is to extend the support for `rex4es` and `rex4es_ec_ish`
variants.

TEST=Able to build and boot google/rex.

Change-Id: Id4e8d1162da93b7266ee1108f870e89b6d884ab9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76608
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-21 07:57:53 +00:00
Arthur Heymans 92a3b67eae acpi/acpi.c: Split of ACPI table generation into separate files
acpi.c contains architectural specific things like IOAPIC, legacy IRQ,
DMAR, HPET, ... all which require the presence of architectural headers.

Instead of littering the code with #if ENV_X86 move the functions to
different compilation units.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I5083b26c0d4cc6764b4e3cb0ff586797cae7e3af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-07-21 07:33:37 +00:00
Arthur Heymans 9c1f78d3e5 acpi/acpigen.c: Ignore compiler warning about stack overflowing
With arm64 -Wstack-usage= is enabled which is triggered on any use of
alloca(). Since this function basically works on x86 without wrecking
things and causing massive stack consumption it's unlikely to cause
problems on arm64.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I5d445d151db5e6cc7b6e13bf74ce81007d819f1d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76007
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-07-21 07:33:06 +00:00
Konrad Adamczyk 86dfcb80ce vendorcode/amd/fsp/common: Refactor dmi_info.h
SoC family is able to provide SoC-specific information
via amd/fsp/<soc_family>/soc_dmi_info.h.

Use common amd/fsp/common/dmi_info.h for all AMD platforms.
This way, duplicated dmi_info.h files in
vendorcode/amd/fsp/<soc_family>/ can be removed.

BUG=b:288520486
TEST=Dump `dmidecode -t 17`.

Change-Id: I5e0109af51b78360f7038b20a2975aceb721a7d5
Signed-off-by: Konrad Adamczyk <konrada@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76107
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-21 07:30:08 +00:00
Matt DeVillier 0a96a1ca06 soc/amd/common/pi: Ensure AGESA S3 resume called before SMM lock
AGESA S3 restore needs to occur before SMM finalization/locking,
but it's a crapshoot as to which runs first since both use the same
BS_OS_RESUME/BS_ON_ENTRY boot state callback, and there's no way
to prioritize/force ordering.

To work around this, move the AGESA S3 resume call to the preceding
boot state (BS_OS_RESUME_CHECK) to ensure it runs first, and guard it
to ensure it only runs on the S3 resume path.

BUG=none
TEST=build/boot google/liara, verify S3 resume successful.

Change-Id: I765db140c6708a0b129f79fb7d3dc8a4ab3095bd
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76592
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2023-07-20 20:33:12 +00:00
Wentao Qin cecb7a75b8 mb/google/rex/var/screebo: Change GPIO of WIFI module
Follow baseboard Rex to make GPIO changes

BUG=b:286187821
TEST=Ability to enable and disable WIFI function in OS.

Change-Id: I805ce859c42c7c0a9d117418a80555658f844e09
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76551
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-07-20 15:01:04 +00:00
Felix Held c3529dd804 soc/amd/common/smn/Kconfig: expand SMN acronym
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icce4092f1e09d492e0faf4b5e85525871614d73d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76607
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-07-20 14:24:53 +00:00
Felix Held ed7b1c4ba0 soc/amd/common/block/smn: add smn_read64
Add smn_read64 which calls smn_read32 twice to read two adjacent 32 bit
SMN registers and merges the results into a 64 bit value which it then
returns.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib2d58ec9818559cbefd7b819ae311ad02fafa18f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-07-20 14:24:07 +00:00
CoolStar 545d9992dc mb/google/link: rework TP/TS ACPI for new Windows I2C driver
This supports a brand new I2C driver that is designed specifically
for the Pixel 2013 chromebook (LINK). The GMBus interface on the IGPU
is an i2c-compatible interface, but AFAIK only Link has touch devices
attached in this way.

On Windows, the PCIe device for the IGP is owned by the Intel
proprietary driver, hence a separate ACPI device has to be added for
the I2C driver arbitrator to attach to. The MMIO method is used instead
of _CRS so that Windows does not try to assign ownership of the
resource to our device (even though we're using the MMIO registers at
the same time as the IGP driver).

Even though in theory 2 drivers accessing the same MMIO may cause
problems, in testing, there has been no issues with
sleep/wake/hibernate, updating/installing/uninstalling the IGP driver,
or changing display resolutions with the i2c driver attached.

The arbitrator is necessary as well, since even though there are
multiple i2c buses, the MMIO registers are shared. Hence a shared lock
is required for i2c access across the buses.

The original Sleep Button devices are preserved for Linux due to the
completely custom and non-standard implementation of the Windows driver
in order to work around the non-standard nature of Link's hardware.

Change-Id: If7ee05d15bc17d335cf8c1a8e80bea62800de475
Signed-off-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-07-20 13:11:16 +00:00
Felix Held 97439ecc01 soc/intel/xeon_sp: use VGA_MMIO_* defines from arch/vga.h
Now that we have x86 architecture specific VGA_MMIO_* defines in
arch/vga.h, use those instead of having SoC-specific defines for this.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I77b914d563bdc83e7fad7d7fccd5cf7777cb4918
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-07-20 13:10:41 +00:00
Arthur Heymans 8193eabd8d acpi: Add GTDT structs
Copied from Linux kernel.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I09f84e63346a270f1c7b77e8088b114800ff4864
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75923
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-20 10:39:53 +00:00
Arthur Heymans a9a92ac961 acpi: Move ECAM resource below PNP0C02 device in a common place
From the Linux documentation (Documentation/PCI/acpi-info.rst):
[6] PCI Firmware 3.2, sec 4.1.2:
    If the operating system does not natively comprehend reserving the
    MMCFG region, the MMCFG region must be reserved by firmware.  The
    address range reported in the MCFG table or by _CBA method (see Section
    4.1.3) must be reserved by declaring a motherboard resource.  For most
    systems, the motherboard resource would appear at the root of the ACPI
    namespace (under \_SB) in a node with a _HID of EISAID (PNP0C02), and
    the resources in this case should not be claimed in the root PCI bus’s
    _CRS.  The resources can optionally be returned in Int15 E820 or
    EFIGetMemoryMap as reserved memory but must always be reported through
    ACPI as a motherboard resource.

So in order for the OS to use ECAM MMCONF over legacy PCI IO
configuration, a PNP0C02 HID device needs to reserve this region.

As no AMD platform has this defined in DSDT this fixes Linux using
legacy PCI IO configuration over MMCONF. Tianocore messes with e820
table in such a way that it prevents Linux from using PCIe ECAM. This
change fixes that problem.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I852e393726a1b086cf582f4d2d707e7cde05cbf4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75729
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-20 10:38:42 +00:00
Annie Chen d31cbc74d1 mb/inventec: Add Intel SPR server board Inventec Transformers
CPU:
- 2 SPR sockets
- 64 total PCIe 5.0 lanes with up to 64 lanes of Flex Bus/CXL per CPU
- Up to 32 DDR5 DIMM
- 1 Gbase-T NIC port
- 1 USB3.0 type A, 1 USB2.0 connector
- 1 VGA connector

BMC:
- ASPEED AST2600 BMC
- 1 DDR4 8Gb memory
- 1 8GB eMMC

Test:
The board boots to Linux 4.19.6 with all 192 cores available.

Change-Id: Ic9d99c3aadaa9f69e6d14d4b1a6c5157f5590684
Signed-off-by: Annie Chen <Chen.AnnieET@inventec.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Wei Chen <Chen.HW@inventec.com>
Reviewed-by: Annie Chen <chen.annieet@inventec.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-07-20 10:11:07 +00:00
Dtrain Hsu 77b71cf9d7 mb/google/nissa/var/uldren: Decrease GT7996F stop_delay_ms to 200ms
In order to reduce S0ix resume time, decrease stop_delay_ms from
300ms to 200ms for Goodix GT7996F. The value source is from
https://partnerissuetracker.corp.google.com/issues/285999032#comment16.

BUG=b:285999032
BRANCH=firmware-nissa-15217.B
TEST=boot uldren to ChromeOS and touchscreen is workable.

Change-Id: I2f0adadbd3d0774da03338cc0abd1639104876d9
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76577
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-20 05:20:28 +00:00
Cong Yang bb0c68ff9e drivers/mipi: Modify INX_P110ZZD_DF0 panel initialization code
There is a problem of screen shake on the old panel[1]. So increase the
panel GOP component pull-down circuit size in hardware, and update the
initialization code at the same time. The new initialization code is
mainly adjusted for GOP timing. When Display sleep in, raise all GOP
signals to VGHO and then drop to GND. In order to be consistent with
the current panel model, let's rename this file.

[1]: INX old panel product number is HJ110IZ-01A-B1, and the new
panel product number is HJ110IZ-01A-B2. We have recalled the shipment
old panel.

BUG=b:270276344
BRANCH=trogdor
TEST= test firmware display pass

Change-Id: I2b2534afee1ed700c39d3c360aafd685b63ccbfb
Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-07-20 00:36:59 +00:00
Subrata Banik d0eeba38de mb/google/rex/var/ovis: Update the Type-C USB2/3 port mapping
This patch updates the Type-C USB2/3 port mapping to reflect the mux
connection change as mentioned in previous patch
commit ee3f796200 (mb/google/rex/var/ovis: Fix mux
change as per schematics).

Here is the correct port mapping after considering the mux swap:

+--------------------------------+-------------+---------------+
| TCSS-USB Mapping |  Port C0    |    Port C1  |   Port C2     |
+------------------+-------------+-------------+---------------+
|  USB2-Port       |     2       |      3      |      1        |
|  USB3-Port       |     0       |      2      |      1        |
+------------------+-------------+-------------+---------------+

BUG=b:289300284
TEST=Able to build and boot google/ovis to get display over Type-C1
and Type-C2 port.

Change-Id: I460004842dd8fcdc03fca6639d03e422259380ca
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76464
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-19 13:24:22 +00:00
Subrata Banik 5259568bda soc/intel/alderlake: Use 1MB CBMEM console buffer with FSP debug
Patch to increase CONSOLE_CBMEM_BUFFER_SIZE to contain FSP debug serial log.

The existing implementation uses larger cbmem size irrespective of FSP debug is enabled or
not. Ideally. larger cbmem size is required only if FSP debug is enabled.

Bug=b:284124701
TEST=Able to build and boot google/marasov.

Change-Id: I9a9e660f2738813808e0dd65d2783424b49f9a5e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-19 13:02:09 +00:00
Subrata Banik 9d78308194 soc/intel/{adl, mtl}: Reduce CAR usage while using FSP debug binaries
Reduces the CAR (Cache-as-RAM) variable usage while using FSP debug binaries, which can prevent the CAR from becoming too full and unable
to integrate other CAR global variables.

This change has the following downsides:

- FSP debug output into the cbmem buffer will be partial.

To test this change, you can:

Build and boot google/rex without any function impact with non-serial
and serial FSP debug image (unless what has been documented here).

Bug=b:284124701
TEST=Able to build and boot google/rex.

Change-Id: I16a1aa25fd32327d03a37381a696c86c95014ba0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-07-19 13:01:57 +00:00
Kun Liu 5f8f05b1b5 mb/google/rex/var/screebo: Change SD_CLKREQ_ODL from GPP_D19 to GPP_D18
Change SD_CLKREQ_ODL from GPP_D19 to GPP_D18

BUG=b:291051683
BRANCH=none
TEST=emerge-rex coreboot

Change-Id: Ic102e42482328580c5334e6ff036b774f5002e00
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76565
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-19 07:50:34 +00:00
Felix Held c04d3ddbae include/cpu/amd/msr: introduce and use PSTATE_MSR_COUNT
Add and use a define for the total number of P-state MSRs to avoid magic
constants in the code.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I37a89faa0f216790b3404fc03edc62408684cc24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-07-18 21:51:33 +00:00
Felix Held 8e0bbb30b6 soc/amd/stoneyridge/pstate_util: fix off by one in P-state MSR number
There are 8 P-state MSRs and not only 7.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic2899b6e454233c6cbb8fc1e439ff069c4d3d3a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-07-18 21:51:22 +00:00
Arthur Heymans b2de1a3368 soc/amd/*/root_complex.c: Use newer function for resource declarations
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: If2048c9cade731b2e4464d0670e0578f5f4bcea0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-07-18 21:00:03 +00:00
Arthur Heymans 885efa1102 soc/amd/stoneyridge: Use newer function for resource declarations
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I2d01424731b149daa3d3378d66855ee5e074473b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76290
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-07-18 20:52:26 +00:00
David Wu dd9481542f mb/google/brya/var/osiris: Enable CsPiStartHighinEct for Hynix memory
According to Intel doc#763797 to overcome early command training hang
issue, the CsPiStartHighinEct needs to be enabled for hynix memory.

BUG=b:284192689
BRANCH=firmware-brya-14505.B
TEST=Built and booted into OS.

Change-Id: Ic177c5ffcb6a3d3f76292a0d99ab0e806d43fc11
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76549
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-07-18 19:09:20 +00:00
Joey Peng cd1006cb0e mb/google/brya/var/taeko: Enable CsPiStartHighinEct
Enable CsPiStartHighinEct to fix MRC Cache fail issue

BUG=b:279835630
BRANCH=none
TEST=Pass MRC Cache test with toolkit 1000 times

Change-Id: I25cd856785bab9c661e30e2987b43f0dc2ba9564
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-18 19:08:34 +00:00
David Wu 41b92fef81 mb/google/brya/var/kano: Enable CsPiStartHighinEct for Hynix memory
According to Intel doc#763797 to overcome early command training hang
issue, the CsPiStartHighinEct needs to be enabled for hynix memory.

BUG=b:281643325
BRANCH=firmware-brya-14505.B
TEST=Built and booted into OS.

Change-Id: I95702e675fa3b73c7e8ee0c8625c7828d8129ea8
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76355
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18 19:08:05 +00:00
Kane Chen caa8a20d87 soc/intel/alderlake: Hook up CsPiStartHighinEct UPD
This commit provides option for board to set CsPiStartHighinEct
FSP UPD using a new cs_pi_start_high_in_ect mb_cfg field.

BUG=b:279835630
BRANCH=none
TEST=CsPiStartHighinEct UPD is set properly

Change-Id: I7d0d5f3c782e29fb047ea421e1a5fdfc30bcc26d
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-18 19:07:32 +00:00
Nick Vaccaro ea025af4dc spd_tools: bring README up to date
bug=b:260128250
TEST=none

Change-Id: I412044a13f636e87db1d2266b33c9134e746e1a2
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76543
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18 18:40:40 +00:00
Patrick Rudolph c39eb20027 memory_info: Bump to 64 DIMMs
Intel SPR supports up to 64 DIMMs on a 4 socket board.
Bump DIMM_INFO struct to 64 slots to properly present all
of them to the OS.

Change-Id: I52d77c4e9bff96adba6d265a272e0e425dbdb791
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73367
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh <naresh.solanki.2011@gmail.com>
2023-07-18 15:06:05 +00:00
Tim Crawford b1ef846da8 mb/system76/rpl: Add Galago Pro 7 as a variant
The Galago Pro 7 (galp7) is a Raptor Lake-H board.

Tested with a custom TianoCore UefiPayloadPkg.

Working:

- PS/2 keyboard
- I2C HID touchpad
- Both DIMM slots (with NMSO480E82-3200EA00)
- M.2 NVMe SSD
- All USB ports
- SD card reader
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Backlight controls on Windows 10 and Linux 6.2
- HDMI output
- DisplayPort output over USB-C
- Internal microphone
- Internal speakers
- Combined headphone + mic 3.5mm audio
- S3 suspend/resume
- Booting Pop!_OS Linux 22.04 with kernel 6.2.7

Not working:

- Detection of devices in TBT slot on boot

Change-Id: I1ae3b2c647aa75976a1ea97f7681f93eb000ba8a
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75277
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18 15:04:35 +00:00
Tim Crawford 903b3ff356 mb/system76/adl: Disable Intel ME by default
Disable the CSME by default now that S3 is used instead of S0ix.

The CSME will not go into a low power state during S0ix when it is
disabled. This prevents the CPU from reaching C10 and so increases the
power usage during suspend compared to leaving CSME enabled. (This was
measured to be a ~2W different on TGL-U.) In S3, the state of the CSME
doesn't matter because the CPU will be off.

Change-Id: I88c0aebdcc977f3ba9dd8f46a6abfaa7a4ae8eb6
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73354
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-07-18 15:04:09 +00:00
Tim Crawford 6255c13927 {ec,mb}/system76: Replace color keyboard logic
System76 EC since system76/ec@9ac513128a detects if the keyboard is
white or RGB backlit via `RGBKB-DET#` at runtime. Remove the Kconfig for
the selection and update the ACPI methods for the new functionality.

Change-Id: I60d3d165a58e30d2afc8736c0eb64dd90c8227ca
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76152
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18 15:03:16 +00:00
Tim Crawford 6875231472 mb/system76/rpl: Add Darter Pro 9 as a variant
The Darter Pro 9 (darp9) is a Raptor Lake-P board.

Tested with a custom TianoCore UefiPayloadPkg.

Working:

- PS/2 keyboard
- I2C HID touchpad
- Both DIMM slots with 5200 MT/s memory
- Both M.2 SSD slots
- All USB ports
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Internal microphone
- Internal speakers
- Combined 3.5mm headphone + mic audio
- 3.5mm microphone input
- S3 suspend/resume
- Booting Pop!_OS Linux 22.04 with kernel 6.2.7

Change-Id: If19caa90e5f90939b2946392da343b7f91f568ca
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75278
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18 15:02:24 +00:00
Tim Crawford d7a07c2873 mb/system76/rpl: Add Serval WS 13 as a variant
The Serval Workstation 13 (serw13) is a Raptor Lake-HX board.

Tested with a custom TianoCore UefiPayloadPkg.

Working:

- PS/2 Keyboard
- I2C HID touchpad
- Both DIMM slots with 5200 MT/s memory
- Both M.2 SSD slots
- All USB ports
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Internal microphone
- Internal speakers
- Combined 3.5mm headphone + mic audio output
- 3.5mm microphone input
- S3 suspend/resume
- Booting Pop!_OS Linux 22.04 with kernel 6.2.7

Not working:

- Discrete/Hybrid graphics
- Thunderbolt

Change-Id: Id709a7d06854ba9de673d5e3f25c0a1bbcc53d21
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73440
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18 15:01:56 +00:00
Tim Crawford ff865a329f mb/system76/adl: Switch from S0ix to S3
After fixing TPM logs clobbering other regions in CB:73297, S3 no longer
causes cache issues resulting in power off after multiple suspends.

This is required for disabling Intel CSME by default.

Change-Id: I7eef4c883fd65db93dae81adabd895b2de90496a
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-07-18 15:00:09 +00:00
Jeremy Soller f501128536 security/tpm: Respect CBMEM TPM log size
The preram TPM log was being copied to the end of the CBMEM TPM log no
matter what the size of the CBMEM TPM log was. Eventually, it would
overwrite anything else in CBMEM beyond the TPM log.

This can currently be reproduced by enabling TPM_MEASURED_BOOT and
performing multiple S3 suspends, as coreboot is incorrectly performing
TPM measurements on S3 resume.

Change-Id: If76299e68eb5ed2ed20c947be35cea46c51fcdec
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73297
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18 14:58:34 +00:00
Nico Huber f9aec6e298 Makefile,genbuild: Provide length for abbreviated commit hashes
The original default, minimum abbreviated hash length was 7. It dif-
fers on newer systems, however. This breaks reproducibility, so set
an explicit length. 12 hex digits should be good enough.

Note: This sets only a minimum. With a high enough number of commit
objects in the repository, Git could still decide to use a longer
hash, again breaking reproducibility. 12 digits will hopefully pro-
vide enough margin.

Change-Id: Ia86e9cc41e27a0a57d498dcb13aec954c4ea0f04
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-07-18 14:57:11 +00:00