Commit Graph

6742 Commits

Author SHA1 Message Date
Vadim Bendebury 8049fc91de Allow device ID arrays in the PCI driver structure
Many PCI devices share the very same driver despite having different
PCI device IDs, which causes a lot of copy and paste of driver
definitions.

This change introduces a way to specify the array of acceptable
device IDs in a single driver entry. As an example the Intel
{Sandy|Ivy} Bridge SATA driver is being modified to use a single
driver structure for all different SATA controller flavors, a few
more Ivy Bridge IDs are being added as well.

BUG=none
TEST=manual
  . modified coreboot brought up an Ivy Bridge platform all the
    way to Linux login screen.

Change-Id: I761c5611b93ef946053783f7a755e6c456dd6991
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/982
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-01 20:02:21 +02:00
Gabe Black 599e204efc Clean up Emerald Lake 2 mainboard directory
Change-Id: I4a64a56dda22050a31232807096e15565a665377
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/967
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-01 20:01:18 +02:00
Stefan Reinauer 8172d0be97 Allow more CPU cores on Emerald Lake 2 CRB
The Emerald Lake 2 CRB can potentially have more
than 8 CPU cores, so update the number of max cores
accordingly.

Change-Id: Ia42ed8a84916f66dfbfdf2a72cbbed5cea61899b
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/966
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-01 19:53:53 +02:00
Gabe Black f40a2590ac Set up ChromeOS dev mode, recovery, and write protect GPIOs on Emerald Lake 2.
The Emerald Lake 2 CRB wasn't designed with ChromeOS in mind, so there aren't
any actual developer mode, recovery mode, or write protect switches, let alone
GPIOs to read them from. Instead, I've commandeered signals connected to GPIOs
which are for other things but which aren't used by hardware or, for instance,
the EC to do something Coreboot doesn't control.

The recovery mode switch is connected to GPIO 22 and is called BIOS_REC on the
schematic. The name is at least very reminiscent of the right thing even if
it's supposed to be used for something else. There's a jumper on the board
labelled J8G1 which can force the line to ground, and if not, there's a switch
on the front of the case which toggles its value. "RECOVER" is for recovery
mode and "KEEP" is for normal mode.

The developer mode switch is connected to GPIO 57 and is called SV_DET on the
schematic. It's connected to a jumper labelled J8E2 on the board and, as far as
I can tell, can't be controlled in any other way. When the jumper is in place
and the pins are shorted, developer mode is selected. When the jumper is
removed, normal mode is selected.

The write protect is connected to GPIO 48 which is called BIOS_RESP on the
schematic. It's connected to a jumper labelled J8E3 which, like j8E2, seems to
be the only way to control the line it's on. When the jumper is in place,
write protect is "disabled", and when it's in place it's "enabled" even though
there's no functional difference.

The input for the recovery mode switch was chosen because of the name it
already had on the CRB, BIOS recovery, and because there's a switch to control
it on the front of the case which makes it easy to get at. The jumpers for
developer mode and recovery mode were chosen because there weren't very many
options available, and of those these were next to each other which should
make them easier to find and work with. It might be a good idea to wire toggle
switches up to the pins of those jumpers so they'll be easy to identify, can
be labelled, and would be easier to work with than little jumpers in the
middle of the motherboard.

Change-Id: Ib2c3dc05077dacfbede596dae143ed81a99dbebd
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/965
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-05-01 19:33:58 +02:00
Stefan Reinauer e6063fee5c Fix Sandybridge/Ivybridge mainboards according to code review
This fixes a few cosmetics with the following three boards:

 - Intel Emerald Lake 2
 - Samsung ChromeBook
 - Samsung ChromeBox

The following issues were fixed:

 - rely on include path in ASL code instead of specifying relative
   paths
 - use updated ALIGN_CURRENT in acpi_tables.c
 - use preprocessor defines instead of hard coded values where possible

Change-Id: Ia5941be3873aa84c30c13ff2f0428d1c52daa563
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/963
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
2012-05-01 19:27:34 +02:00
Patrick Georgi a1155b47ca Move VSA support from x86 to Geode
Instead of the special case in the generic Makefile.inc,
use cbfs-files in the CPU directories.

Change-Id: I71d9c8dff906c9a516ac0dd09a315f8956075592
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/962
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-05-01 11:35:40 +02:00
Patrick Georgi 0909d86760 Support adding stages with cbfs-files
stages have special cbfstool syntax, which we need to support.

Change-Id: I119255246af818f010acfc7ec2091a6184e74eb3
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/961
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-05-01 11:35:34 +02:00
Patrick Georgi 843005c769 Add vsa processor to cbfs-files
Change-Id: I548e86084acc51b0471160d37439385f524224cf
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/960
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-05-01 11:35:28 +02:00
Patrick Georgi 943ddcee53 Make geode_lx use the vsa from blobs repository
... or fail if repository is not enabled.

Change-Id: I0a1e6d6fed852ec7edf96ace8346ae6b23838a56
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/959
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-05-01 11:35:22 +02:00
Gabe Black 5fe7a209f5 Set up the Emerald Lake 2 SMI and SCI sources based on the schematic.
This sets up the SMI and SCI inputs on the PCH for Emerald Lake 2 based on my
best interpretation of the schematic. It may not be correct, but it doesn't
seem to cause any problems either.

Change-Id: I21238b3853a92893ec7f08baa2a3ebd35c49dd97
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/964
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-05-01 07:24:16 +02:00
Patrick Georgi bea8421145 abuild: Add option to use binary files
abuild -B enables the use of the blob repository.

Change-Id: I2dd823d3b024ad249d72d668657bf6a6e92145cf
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/958
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-05-01 00:28:01 +02:00
Patrick Georgi 7e9b9d893c Add Kconfig options to handle the blobs repository
One option to allow using the repo (defaults to no),
one to let boards state that they require it in the
current configuration.

The build system checks out the repo if allowed, and
fails if the repo is requested by the configuration
but not desired by the user.

Change-Id: If71d80b329cf528aa467fcb0b4d9d7c7434aab27
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/957
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-05-01 00:09:27 +02:00
Patrick Georgi 1db6e2aa19 Add 3rdparty as submodule
The build system will make sure only to fetch this if
desired by the user.

Change-Id: Ie3c1b44f67ba2595cae001234e29e36cf855a3e4
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/956
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-05-01 00:08:37 +02:00
Stefan Reinauer e1ae4b212f Add support for Sandybridge base Samsung ChromeBox
Change-Id: Ic93ad2749834c8f7a2ca1651d343561f2a496312
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/953
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-30 23:09:26 +02:00
Stefan Reinauer 155e9b5533 Add support for Sandybridge based Samsung ChromeBook
Change-Id: I8bf439bc903c1ec105016866753c7cb9ccfe5974
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/952
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-30 23:09:10 +02:00
Stefan Reinauer 6651da3bcd Add support for Intel Emerald Lake 2 CRB
This adds support for Intel's Emerald Lake 2 board.

Change-Id: Ifaeeac9d52fe655324ee29df5f7187b89b35f73a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/951
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-30 23:08:06 +02:00
Stefan Reinauer c31384e62c Fix up Sandybridge C state generation code
This code fixes the sandybridge C state generation code to work with
the current version of the ACPI code generator.

Change-Id: I56ae1185dc0694c06976236523fdcbe5c1795b01
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/950
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-30 23:07:55 +02:00
Stefan Reinauer f69b46805c acpigen: make acpigen_write_CST_package_entry non-static
It's used by Sandybridge specific C state generation code.

Change-Id: Ia6f1e14e748841a9646fd93d0a18f9e8f2a55e29
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/949
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-30 23:07:44 +02:00
Stefan Reinauer 6ea86b19f3 Sandybridge: Temporarily disable MRC cache finding code
This code is still using libfdt which was denied for inclusion
in coreboot, so it won't compile as is.
Without MRC cache, waking from suspend won't work, and cold boots are
significantly slower (adds around 300-400ms per channel IIRC).
A rework of this code is currently in the works, but will take a little bit
more time (and should not hold back the mainboards being merged)

Change-Id: Ifb9e7d7b86c1f52378803a748810da0d51b58384
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/948
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-30 23:07:31 +02:00
Stefan Reinauer 35555167c2 acpi: Add defines for functional fixed hardware
Change-Id: I9c5148eb315e2f478cb753d9918144a19e417379
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/945
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2012-04-30 23:06:42 +02:00
Stefan Reinauer 39205c6702 acpigen: Add support for generating T state tables
Change-Id: I58050591198bb06de5f0ca58ca3a02f1cfa95069
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/944
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2012-04-30 23:06:08 +02:00
Stefan Reinauer 4cc8c70c32 Rework ACPI CST table generation
... in order to unify the Sandybridge and Lenovo implementations
currently used in the tree.

- use acpi_addr_t in acpigen_write_register()
- use acpi_cstate_t for cstate tables (and fix up
  the x60 and t60)
- drop cst_entry from acpigen.h

Change-Id: Icb87418d44d355f607c4a67300107b40f40b3b3f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/943
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2012-04-30 23:05:40 +02:00
Martin Roth a403c687b1 Add default map_oprom_vendev() for AMD Family 14h processors.
AMD supplies their video bios for the Family 14h processor line
with Vendor ID: 1002, Device ID: 9802.  This rom should work for
Device IDs 9802-9809.  This patch maps all those device IDs to
0x9802 so coreboot will be able to load the vbios.  If a vbios
rom using the ACTUAL Device ID is loaded, this function will not
be called.
This file should contain of all Family 14h Graphics PCI IDs so
that they don't need to be overridden on a per mainboard basis.

Change-Id: If3d4a744b3c400dea9444a61f05382af2b2d0237
Signed-off-by: Martin L Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/955
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-04-30 17:20:32 +02:00
Marc Jones f3005f515b Update SeaBIOS stable to the version 1.7.0 tag.
Change-Id: Id3a2dd29e07ed11755468e89f8e80efdef5e2b2f
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/954
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-04-29 22:51:08 +02:00
Martin Roth 40aa9bce7d Update amd/south_station/fadt.c with various fixes
This is a model fadt.c that I would like to use for updating
several other AMD platforms with after acceptance.

- Updated to match ACPI 3.0b specification and added comments
  to reflect that.
- Since smi_cmd is 0, remove commands that rely on it:
  acpi_enable, acpi_disable, & pstate_cnt
  Add comments to that effect.
- Changed preferred_pm_profile to SOHO Server (platform
  specific)
- The southstation platform is legacy free - Updated
  iapc_boot_arch and flags to reflect that.
- Added reset_register flag so that operating systems
  will actually use the reset_reg.  This is important
  on legacy free systems.
- Updated Generic Address Structures to use access_size
  name in the updated acpi.h.  Added access sizes to
  the structures where reasonable.
- Removed 64-bit x_firmware_ctl pointer to facs.  This was
  causing a fwts failure and windows-64 BSOD.
- Added bit width for pm2_cnt_blk and modified gpe0_blk bit
  to match the hardware.

Change-Id: Icf1a982aa122636d1088c8b80f53d04732b54c49
Signed-off-by: Martin L Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/942
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-04-29 18:34:08 +02:00
Raymond Danks a293714579 nvramtool: Allow build under Cygwin
To build under Cygwin, nvramtool depends upon the package ioperm:
http://openwince.sourceforge.net/ioperm/

for sys/io.h and sys/perm.h.  This change causes the nvramtool make to correctly include and link against these headers and libraries.

Change-Id: If6cd9d324de7bc19830e0018844f42761b28ddd3
Signed-off-by: Raymond Danks <ray.danks@se-eng.com>
Reviewed-on: http://review.coreboot.org/940
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-29 18:27:30 +02:00
Stefan Reinauer 61e7c289d4 ChromeOS: Add missing prototype for acpi_get_vdat_info()
Change-Id: I4bd9b52cfc24a8ff73be05ee535b9e16c0d9bd79
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/946
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2012-04-28 18:39:12 +02:00
Stefan Reinauer 5b73d4d1bb acpigen: make acpigen_write_len_f() non static
since it is used in CPU specific ACPI generation code

Change-Id: I2559658f43c89dc5b4dc8230dea8847d2802990c
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/947
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-04-28 09:03:40 +02:00
Raymond Danks 51b8f05ab3 ectool: Allow build under Cygwin
To build under Cygwin, ectool depends upon the package ioperm:
http://openwince.sourceforge.net/ioperm/

for sys/io.h and sys/perm.h.  This change causes the ectool make to correctly include and link against these headers and libraries.

Change-Id: I7d54ab5110c2bb1fd21dfa48d56031f3f29cd54e
Signed-off-by: Raymond Danks <ray.danks@se-eng.com>
Reviewed-on: http://review.coreboot.org/941
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-28 02:46:54 +02:00
Martin Roth e9dfdd9dbd Reverse Vendor ID & Device ID for map_oprom_vendev()
- When calling map_oprom_vendev() the vendor ID and device ID
  are joined into a 32 bit value.  They were reversed from the
  order that I would have expected - Device ID as the high 16 bits
  and the Vendor ID as the low 16.  This patch reverses them so
  so that the the dword comparison in map_oprom_vendev() matches
  what's entered into Kconfig for vendor,device.
- Change files calling map_oprom_vendev()

Change-Id: I5b84db3cb1a359a7533409fde7d05fbc6ba3fcc4
Signed-off-by: Martin L Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/938
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-28 02:45:22 +02:00
Stefan Reinauer 0e672b52d4 coreboot_table.c: Add missing include files
If compiling coreboot with ChromeOS support, two
more include files are required.

Change-Id: I7e042e250e4a89e7dd4bab58443824d503c3f709
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/931
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-27 20:16:47 +02:00
Stefan Reinauer 16401b8f6d SMM: Add udelay on Sandybridge systems
Cougar Point southbridge does udelay in SMM, hence add it on Sandybridge
systems.

Change-Id: I6e5520ca27e7c6eaae632992fb68612067bc1e30
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/937
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-27 19:24:19 +02:00
Stefan Reinauer 80529abdfb Cougar Point southbridge: Add includes and drop post_code()
post_code() was added in our internal tree by duplicating code. It's not of
much use at this point, since the code is quite well tested, so avoid bloating
the bootblock (since compiled with ROMCC).
Also add some missing include files that didn't seem to be needed with an
older version of coreboot.

Change-Id: Id62b838728a247e8bcadb4f1db17269be0d4f3f4
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/936
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-27 19:24:13 +02:00
Stefan Reinauer adc7bb06cd ChromeOS: add missing string.h in gnvs.c
string.h is required to build with the reference toolchain.

Change-Id: I9fd8d2ea8fc676d3502989cbcc7aefe3b2d738b6
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/935
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-27 19:24:04 +02:00
Stefan Reinauer b5866f2fb6 SMSC MEC1308: Fix ACPI code to work with newer IASL versions
Newer versions of IASL didn't like our IO constructs. Use
FixedIO instead, it's also shorter.

Change-Id: I9364d993ecb71ffd84c0313ca1e2f870af59eb24
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/934
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-27 19:23:58 +02:00
Stefan Reinauer bf34e94095 SMM: unify mainboard APM command handlers
rename from mainboard_apm_cnt to mainboard_smi_apmc to match the function
naming scheme of the other handlers. Add prototype for mainboard_smi_sleep
(mainboard specific S3 sleep handlers in SMM) that is required by Sandybridge.

Change-Id: Ib479397e460e33772d90d9d41dba267e4e7e3008
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/933
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-27 19:23:50 +02:00
Stefan Reinauer ac8209a4b3 cpu/cpu.h: add ROMCC guards
In order to use the generic microcode update code in the bootblock, cpu/cpu.h
needs ROMCC guards. Also, delete the unused struct device declaration and move
the struct bus declaration to where it's used.

Change-Id: I0cc731c555593946e931a680ec93994932530599
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/932
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-27 19:23:41 +02:00
Stefan Reinauer ae5e11d7cd Move top level pc80 directory to drivers/
There is no reason for this to be a top level directory.
Some stuff from lib/ should also be moved to drivers/

Change-Id: I3c2d2e127f7215eadead029cfc7442c22b26814a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/939
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-27 19:23:16 +02:00
Martin Roth aee1869fcf Updates to x86/include/arch/acpi.h for use in fadt.c
- Added a union to identify the byte that was reserved in the
  Generic Address Structure from ACPI 2.0 to ACPI 2.0b as the
  Access Size byte for ACPI 2.0c to ACPI 5.0
- Added various #defines for use in the FADT
- Added a couple of comments for the #endifs

Change-Id: I294ddfd89fcb0ad88bb6e52d911f807d84671e82
Signed-off-by: Martin L Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/930
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-04-27 01:36:30 +02:00
Stefan Reinauer 31109452c2 microcode: print date of microcode and unify output
Most subsystems print their name with a colon, and then the
message. Do the same thing for the microcode update code.

Also, each microcode update has a date header. Print the
date from that header to make it easier to determine whether
you're running the latest microcode.

Change-Id: Ic22947c4b9f0502d4091d975e1f1ab42f70aa1aa
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/929
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
2012-04-26 02:32:04 +02:00
Stefan Reinauer 3f8989ebbc Revamp Intel microcode update code
- add GPLv2 + copyright header after talking to Ron
- "bits" in struct microcode served no real purpose but
  getting its address taken. Hence drop it
- use asm volatile instead of __asm__ volatile
- drop superfluous wrmsr (that seems to be harmless but
  is still wrong) in read_microcode_rev
- use u32 instead of unsigned int where appropriate
- make code usable both in bootblock and in ramstage
- drop ROMCC style print_debug statements
- drop microcode update copy in Sandybridge bootblock

Change-Id: Iec4d5c7bfac210194caf577e8d72446e6dfb4b86
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/928
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-26 00:46:35 +02:00
Patrick Georgi 05e740fc40 Replace cache control magic numbers with symbols
Instead of opaque numbers like (1<<29), use
symbols like CR0_NoWriteThrough.

Change-Id: Id845e087fb472cfaf5f71beaf37fbf0d407880b5
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/833
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-25 16:27:07 +02:00
Denis 'GNUtoo' Carikli 8919729307 ASUS M4A785T-M mainboard: fix screen flickering issues
Without that fix the screen flickered with resolutions superior
  to 832x624 because the cpu_ht_freq was 0 (so it ran at 200Mhz).

Change-Id: I1056d76b1d77f6177594ed9d03ecc5ae7b3c2c13
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/900
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-04-25 12:07:07 +02:00
Kyösti Mälkki 1e9c1b3e1d Makefile: rename romstage linking filenames
Move final build results under $(objcbfs).
Move intermediate files under $(objgenerated).
Remove use of sed -i.

Change-Id: Ie035a1544848b26514a197c340f470201065b8d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/859
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-24 23:25:31 +02:00
Kyösti Mälkki 38f2e9cfe3 Makefile: rename coreboot_ap linking filenames
$(obj)/coreboot_ap -> $(objcbfs)/coreboot_ap.elf

It is really a ramstage for AP CPU and not a romstage, it is not
enabled for any mainboard by default, and it doesn't compile
even if enabled.

Change-Id: Ifb9c5cb6df65309660b000876cf6a9a3da9b6839
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/840
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-24 23:22:15 +02:00
Kyösti Mälkki 6b07b8df92 Makefile: rename ramstage linking filenames
Move final build results under $(objcbfs).
Move intermediate files under $(objgenerated).

Change-Id: I0046f68938be81b8efa525aa50b39328ca02ecb6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/839
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-24 23:13:00 +02:00
Kyösti Mälkki f775b8c8df Makefile: rename bootblock linking filenames
Move final build results under $(objcbfs).
Move intermediate files under $(objgenerated).

Change-Id: I0365304e1b0ed02a5a3ec720b0cf3e303eaefa7c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/838
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-24 23:12:19 +02:00
Patrick Georgi f526889e8b rk886: Add ACPI support for LID switch
Change-Id: Ib5a34491531228db9a9232322bd573fded27ee67
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/924
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-24 23:09:24 +02:00
Rudolf Marek 3294a0f1ca Make timestamp collection conditional in hardwaremain.c
Otherwise it breaks 486 boards without RDTSC, ending with
exception 6.

It ends like this on bifferboard:

Jumping to image.
Unexpected Exception: 6 @ 10:001007e3 - Halting
Code: 0 eflags: 00000016
eax: 001001fe ebx: 00100118 ecx: 00000000 edx: 00108e00
edi: 0010aaf8 esi: 00000000 ebp: 00117ff4 esp: 00117fd8

Please keep in mind 486, dont use rdtsc/cpuid in generic code, or if you do make sure make it non-default option.

Change that broke it: http://review.coreboot.org/#/c/749/7/src/boot/hardwaremain.c

Change-Id: I974b25377c20a11430b35b24dcc275d8cbfd2b9a
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/925
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-04-24 18:19:54 +02:00
Alec Ari 02c204706f Fix whitespace for ma785gm
Fix tabs and whitespace for
ma785gm mainboard.c file.

Change-Id: I8c94bf428bc4e78871da8c64f89221af4151e16d
Signed-off-by: Alec Ari <neotheuser@ymail.com>
Reviewed-on: http://review.coreboot.org/923
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-04-24 03:58:17 +02:00