Add missing Power Management 2, old and new GPIO functions to modify the
contents of these MMIO blocks.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ie4db6a4d12d9122ea5b87147adbf7b632ac2b311
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Hide the fundamental BIOSRAM accessors to force use of the
memory space via abstraction functions.
Change-Id: I774b6640cdd9873f52e446c4ca41b7c537a87883
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37862
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Clean up devicetree as nothing special is needed here.
BUG=b:142769041
BRANCH=none
TEST=builds
Change-Id: I0790631233fdcaa6a785d2cb41e79b8f2f469d44
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Implement a free() that supports only the last malloc(). Rewind
the heap to the last allocation point if the ptr to be freed is
matching the end of heap before last malloc(). With current situation,
since free() is no-op, every call to malloc() is a memory leak.
BUG=b:140124451
TEST=Wrote a test function to do malloc and free operations.
Change-Id: I6d43cf54b79e6897cf6882335730b2310e4eae45
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Not built, relies on SMBUS for SPD and we do not have
a globally defined spd_read_byte() prototype.
Change-Id: Ifb9d3aa31207cb5b99f475b70f52a03aca73432b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
While I was working on updating the headers to move copyrights into
the AUTHORS file, I got a request to switch to SPDX headers as well.
Linux has moved completely to SPDX headers, which are easier to
maintain, have good definitions, are very short, and can be checked
automatically. This is completely unlike our current header situation.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ie86d34f7fa7bf7434ad8a38aa1eadcfece7124b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
In preparation to update to SPDX license headers, add identifiers
for the licenses seen in the coreboot project and create a command
line parameter allowing only SPDX license identifiers to be detected.
Here are example locations of these licenses:
Apache-2.0 - src/soc/sifive
BSD-3-Clause - Throughout coreboot & libpayload source
GPL-2.0-only - Throughout coreboot source
GPL-2.0-or-later - Throughout coreboot source
GPL-3.0-only - util/amdtools
GPL-3.0-or-later - src/lib/[gcov/libgcov/gnat]
ISC - src/lib/ubsan.c, soc/qualcomm/ipq806x/include/soc/gsbi.h, others
MIT - soc/nvidia/tegra210/mipi_dsi.c, files in mainboard/cavium/
X11 - include/device/drm_dp_helper.h, drivers/aspeed/common/ast_tables.h
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I07a7ca408ac8563e03e189d05ef7729dfb6fc24e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Unlike laptops and some trash cans, desktop boards do not have a lid.
Change-Id: I5f947e411a4c9295a294f55771cd123de6b1e702
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
These are the boards I have and currently working on.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I3f366105371c7d2568da6682b24cb52bce2d5467
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
These devices were just added in 727ac0d263 (AMD {SoC, AGESA, binaryPI}:
Don't use both of _ADR and _HID), but they don't provide any information
and are not referenced anywhere.
Change-Id: I862a3c43eb610e488eb7d9246feb94a6d1333ca0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The majority of Socket AM1 APUs [1] - three out of five - have the integrated
VGA with 1002,9830 ID, while only one Sempron has 1002,9836. Since VGA_BIOS_ID
is already defined in fam16kb Kconfig as 1002,9830 ID, drop the value here.
[1] https://en.wikipedia.org/wiki/List_of_AMD_accelerated_processing_units#%22Kabini%22_(2013,_SoC)
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I75c815b13934afcb5be316f85933f7c200d55bbd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33777
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Most of these are leftovers from the initial copy from Baytrail.
Change-Id: I1c437f34902400022ac6a5e95ff6168545ca557f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
NIDs 0x18 and 0x19 are flipped, and the verbs for NID 0x1b are instead
applied onto NID 0x1a. Fix that, so that it matches original Chromium
sources for the boards.
Change-Id: I20cc4b282602f8557fa4f25489adf899b7460a09
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Looks like the subvendor verb for codec #3 is erroneously using zero as
its codec number. Fix that.
Change-Id: I760533c229287627dd0548a06300c376e045302c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Denary, also known as "decimal" or "base 10," is the standard
number system used around the world. Therefore, make use of it.
Change-Id: I7f2937bb7715e0769db3be8cb30d305f9d78b6f8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This is a initial mainboard code aimed to serve as base for
further mainboard check-ins.
This is a copy patch from icelake_rvp as on commit ID:
I64db2460115f5fb35ca197b83440f8ee47470761
Below are the changes done over the copy patch:
1. Rename "Icelake" with "Jasperlake".
2. Replace "icelake_rvp" with "jasperlake_rvp".
3. Rename "icl" with "jsl".
4. Remove unwanted SPD file, add empty SPD as
placeholder.
5. Replace "soc/intel/icelake" with "soc/intel/tigerlake"
as tigerlake SOC hosts jasperlake code as well.
6. Empty romstage_fsp_params.c, to fill it later with
SOC specific config.
7. Empty GPIO configuration, to be filled as per board.
8. Change copyright year to 2019.
9. Add two board support namely BOARD_INTEL_JASPERLAKE_RVP
and BOARD_INTEL_JASPERLAKE_RVP_EXT_EC
10. Replace icl_u and icl_y variant with jslrvp variant.
11. Remove basebord gpio.c and rely on variant override.
12. Remove HDA verb table and config support.
Changes to follow on top of this:
1. Add correct memory parameters, add SPDs.
2. Clean up devicetree as per jasperlake SOC.
3. Add GPIO support.
4. Update chromeos.fmd to make 10MB BIOS region.
TEST=Build jasperlake rvp board
Change-Id: I3314215807959b7348b71933fbba98e6487c0632
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Let coreboot know there is a NIC device on the end so
that the mac from vpd is set at early boot.
Properly configure the link-leds in devicetree s.t.
valid values are written out to the register at initialization.
BUG=b:146592075,146999042,146999043
BRANCH=none
TEST=Boot to kernel.
Insert mac address into VPD
vpd -s ethernet_mac=<address>
reboot the system.
Ensure we have ip address and corresponding mac
address with ifconfig.
Ensure ethernet controller shows up with lspci.
Change-Id: I76ce6d8a5a26842fcb2544ee96567fe0da8603b1
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
I used register names guessed on what the registers do, since the SNB
documentation marked those registers as reserved; the IVB documentation
(326765-005) has names for the registers, so I'll use those.
Change-Id: I2f1194438a56546d9836dd12635d064a900a2fd8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38008
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove commented-out entries in dsdt.asl, and then remove files that do
not get built.
Change-Id: I579e7ffbc2d6596fd7ffe6863ff3b3fb14b0ade6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
To print times with 1 us resolution just adds unnecessary noise
when comparing logs across different boots. Furthermore, just
the printk itself is 1 ms if some slow console is enabled.
Change-Id: Ibea43124a1937f404a6e71fd9431086b2b72290a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
For each boot_state, report the times spent interleaved
with other console output and remove the samples arrays.
The time spent to report the times to console is not
accounted for.
Change-Id: I0c847da98901c56b356b4a933d9ae865dada98b6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Now that romcc is gone, move cmos_post_init() into post.c, and remove
some preprocessor workarounds.
Change-Id: I0ee4551e476cdd1102e86e7efc74d5909f64a37b
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Don't initialize fields with zeroes since gnvs structs were zeroed out
in southbridge already. See
* src/southbridge/intel/*/lpc.c
Change-Id: I5228f2cdc94df722ffa687c45b4e4fd25e82df82
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The gnvs structure was zeroed out before calling acpi_create_gnvs(...)
in the following files:
* src/southbridge/intel/*/lpc.c
Change-Id: Id7755b1e4b8f5cb8abd1f411b5dc174b6beee21c
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37956
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
After C_ENVIRONMENT_BOOTBLOCK became mainstream, coreboot build system
starts to produce larger bootblock, conflicting with former default
offsets.
This change makes these offsets configurable before building, with
default values lower than before, to better fit the larger bootblock.
Change-Id: Ie022663a4d0df7f431865b55f7329a9ebb90863b
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37778
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Michał Żygowski