Commit Graph

7 Commits

Author SHA1 Message Date
Aaron Durbin bf1e481944 lib: remove FLASHMAP_OFFSET config variable
The FLASHMAP_OFFSET config variable is used in lib/fmap.c, however
the fmdtool creates a fmap_config.h with a FMAP_OFFSET #define.
Those 2 values are not consistent. Therefore, remove the Kconfig
variable and defer to the #define generated by fmdtool.

Change-Id: Ib4ecbc429e142b3e250106eea59fea1caa222917
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14765
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2016-05-11 21:32:44 +02:00
Lee Leahy bf08da27d5 Documentation/Intel: Add minimal APCI and TempRamExit documentation
Update the documentation to add the minimal ACPI support.  Also add
TempRamExit entry to the FSP features table.

TEST=None

Change-Id: I7a4576d58005a0b6834188dfeca97f1683d03cb0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13757
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-24 15:55:42 +01:00
Lee Leahy de8c7e39bc Documentation: x86 device tree processing and memory map
Add documentation on:
*  FSP Silicon Init
*  How to start the x86 device tree processing for ramstage
*  Disabling the PCI devices
*  Generic PCI device drivers
*  Memory map support

TEST=None

Change-Id: If8f729a0ea1d48db4d5ec1d4ae3ad693e9fe44f0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13718
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-19 20:24:02 +01:00
Lee Leahy fcf776fd02 Documentation: x86 add sleep state and minimal memory setup
Document how to add the sleep state and minimal memory setup.

TEST=None

Change-Id: Ibebeef34269dbf2366f1bea6d734f6bade4e4028
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13446
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-05 22:57:25 +01:00
Lee Leahy 66decf1644 Documentation: x86 Enable Serial Output
Document the steps necessary to enable serial output

TEST=None

Change-Id: Ifc0e700d7ef54fb1e28ca9bca34b94cccd3633ac
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13444
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-05 22:57:03 +01:00
Lee Leahy e8424cf10f Documentation: Fix links to Intel/documentation.html
Fix links to the documenation.html page which was renamed from
x86Documenation.html.

TEST=Verified documentation links and searched for x86Documenation.html

Change-Id: Icee79bab4c05ac9b8010dc7acdde8dd5e2ab2909
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13592
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-05 22:52:46 +01:00
Lee Leahy c1e4f89953 Documentation: Add x86 documentation for required files
Document the required files to perform a minimal coreboot/FSP build for
x86.

TEST=None

Change-Id: I65b2947114634fce982ce82fb7c577fd5f47ed10
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13438
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-02-02 15:54:43 +01:00