Commit Graph

39244 Commits

Author SHA1 Message Date
Angel Pons 3aed6ac613 nb/intel/sandybridge: Add comments about I/O and RT latency
Document the algorithm to adjust I/O and roundtrip latencies.

Change-Id: Ic8b9aed54a34bb3252c457e87e81387fd410e305
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48397
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-23 16:04:22 +00:00
Angel Pons c8ac2ccf80 nb/intel/sandybridge: Rename I/O data timings
Tested on Asus P8H61-M PRO, still boots.

Change-Id: I147ba0ade8a5317a0fe76e9ea84947fd91d794b4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47773
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-23 16:03:44 +00:00
Angel Pons 9fcc110c37 nb/intel/sandybridge: Use bitfields for I/O data timings
Refactor in preparation to split up `program_timings`.

Tested on Asus P8Z77-V LX2, still boots.

Change-Id: I68410165f397d8b4f662e40e88fb6a58ab1c5cff
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47772
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-23 16:02:17 +00:00
Angel Pons 075d123f6a nb/intel/sandybridge: Compute data timings independently
Use absolute values for the Rx and Tx bus timings instead of values
relative to the CA (Command/Address) bus timing. This makes the
calculations more accurate, less complex and less error-prone.

Tested on Asus P8H61-M PRO, still boots. Training results do not seem to
be affected by this patch, and the margins roughly have the same shape.

Change-Id: I28ff1bdaadf1fcbca6a5e5ccdd456de683206410
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47771
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-23 16:01:53 +00:00
Raul E Rangel 81ff33cffc Makefile: Add $(xcompile) to specify where to write xcompile
This file was being written to the root src directory. It is the only
file being written to src during a normal build, while all others are
being written to $(obj). I added a new variable to allow specifying the
xcompile path. This allows generating a single file if building multiple
boards. I also moved the default location into $(obj) so we don't
pollute the src directory by default.

I also cleaned up the generation of xcompile by removing the unnecessary
eval and NOCOMPILE check.

I also left .xcompile in distclean so it cleans up stale files.

Since .xcompile is written into $(obj), `make clean` will now remove it.

The tegra Makefiles are outside of the normal build process, so I just
updated those Makefiles to point to the default xcompile location of a
normal build. The what-jenkins-does target had to be updated to support
these special targets. We generate an xcompile specifically for these
targets and pass it into the Makefile. Ideally we should get these
targets added to the main build.

BUG=b:112267918
TEST=ran `emerge-grunt coreboot` and `make what-jenkins-does`

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia83f234447b977efa824751c9674154b77d606b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/28101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-23 03:40:35 +00:00
Subrata Banik deba7deda6 vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1514_11
List of changes:
FSP-S Header:
- Add UPD MicrocodeRegionBase and MicrocodeRegionSize
- Adjust UPD Offset for Reservedxx

Change-Id: I376abf6cd64dcf8c848901074e2c2f30d4f302da
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2020-12-23 03:32:42 +00:00
Nico Huber a69d682a0b libpayload/keyboard: Revise scancode set and translation config
Some background first: The original XT keyboards used what we call
scancode set #1 today. The PC/AT keyboards introduced scancode set #2,
but for compatibility, its controller translated scancodes back to
set #1 by default. Newer keyboards (maybe all we have to deal with)
also support switching the scancode set.

This means the translation option in the controller and the scancode
set selection in the keyboard have to match. In libpayload, we only
support set #1 scancodes. So we either need the controller's trans-
lation on and set #2 selected in the keyboard, or the controller's
translation off and set #1 selected in the keyboard.

Valid configurations:
* SET #1 + XLATE off
* SET #2 + XLATE on

Both with and without the PC_KEYBOARD_AT_TRANSLATED option, we were
only configuring one of the two settings, leaving room for invalid
configurations. With this change, we try to select scancode set #2
first, which seems to be the most supported one, and configure the
controller's translation accordingly. We try to fall back to set #1
on failure.

We also keep translation disabled during configuration steps to
ensure that the controller doesn't accidentally translate confi-
guration data.

On the coreboot side, we leave the controller's translation at its
default setting, unless DRIVERS_PS2_KEYBOARD is enabled. The latter
enables the translation unconditionally. For QEMU this means that
the option effectively toggles the translation, as QEMU's controller
has it disabled by default. This probably made a lot of earlier
testing inconsistent.

Fixes: commit a95a6bf646 (libpayload/drivers/i8402/kbd: Fix qemu)
       The reset introduced there effectively reverted the scancode
       selection made before (because 2 is the default). It's unclear
       if later changes to the code were only necessary to work
       around it.

Change-Id: Iad85af516a7b9f9c0269ff9652ed15ee81700057
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-23 03:29:32 +00:00
Nico Huber 0e1d19baa6 libpayload/i8042: Add API to get/set kbd translation state
Change-Id: I49aa1c244cb60ea290df102f06f641c765f59fa5
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-23 03:29:16 +00:00
Subrata Banik 683c95e4ab soc/intel/alderlake: Enable support for extended BIOS window
Port commit ba75c4c (soc/intel/tigerlake: Enable support for
extended BIOS window) for Alderlake

Change-Id: Iaa8464d45884de433cca4f6a250cdd8d4c8f3661
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-23 03:29:00 +00:00
Subrata Banik 65f5932e0c soc/intel/alderlake: Add SPI DMI Destination ID
Port commit 237afda (src/soc/intel/tigerlake: Add SPI DMI Destination ID)
into Alderlake.

Change-Id: Ia0b465d405ab3c70b7d4094d32c182cab30fe531
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-23 03:28:47 +00:00
Subrata Banik 8943183b2c mb/intel/adlrvp: Make SI_ALL region within 16MiB
TEST=Able to build and boot ADLRVP.

Change-Id: I93da53f8835e0eec4cf4e78daab26332fd55d334
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-23 03:28:35 +00:00
Felix Singer e5706b6591 mb/clevo/cml-u: Reorder selects alphabetically
Change-Id: Idd02573e6b47c3bcbdcefa7b04fb9098b600df49
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-23 03:28:14 +00:00
Tim Wawrzynczak 7567890110 soc/intel/common: Fix XHCI elog driver
Commit 56fcfb5 misused the PCH_DEVFNs passed to the XHCI elog driver, by
passing them directly to pci_s_read_config32. This is incorrect, as it
is the wrong PCI devfn encoding to pass to that function.

BUG=b:175996770
TEST=abuild

Change-Id: Id7c146c1f50ee64a725bd50f9f11a7f159013a2b
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-22 22:37:56 +00:00
Patrick Rudolph 7a66ffb34a soc/intel/common/block/acpi: Fix get_cores_per_package
Current implementation uses CPUID 0Bh function that returns the number
of logical cores of requested level. The problem with this approach is
that this value doesn't change when HyperThreading is disabled (it's in
the Intel docs), so it breaks generate_cpu_entries() because `numcpus`
ends up being zero due to integer division truncation.

- Use MSR 0x35 instead, which returns the correct number of logical
  processors with and without HT.

- Use cpu_read_topology() to gather the required information

Tested on Prodrive Hermes, the ACPI code is now generated even with
HyperThreading disabled.

Change-Id: Id9b985a07cd3f99a823622f766c80ff240ac1188
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-22 22:22:21 +00:00
Gaggery Tsai 8d127846bc soc/intel/cannonlake: Add Iccmax and loadlines for CML-S
Following up 3ccae2b7, this patch adds Iccmax and AC/DC
loadlines and iPL2 for CML-S CPUs. The information is from
CML EDS volume 1, doc #606599 and pdg #610244.

Change-Id: Id2797a979a8b6a52a34baae66f95c7136ed1dc72
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38288
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-22 22:21:00 +00:00
Michael Niewöhner 8ba96b91dc soc/intel/apl/graphics: add missing left-shift
According to doc# IHD-OS-BXT-Vol 2b-05.17 the cycle delay is in the bit
range 8:4 of register PP_CONTROL. The current code writes the value to
bits 4:0, though. Correct that by shifting the value left by 4 bits.

Change-Id: If407932c847da39b19e307368c9e52ba1c93bccd
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-22 20:34:27 +00:00
Kyösti Mälkki e653942453 sb/intel/ibexpeak: Drop ChromeOS setup for GNVS
The CHROMEOS option was never used with ibexpeak, code was copy-pasted
and forked from bd82x6x. Since a custom ibexpeak/nvs.h was already made,
an accompanying globalnvs.asl is added here too without chromeos_acpi_t.

Change-Id: I16406516b51c13d49593bc8a3e1e5b868eea6f24
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48766
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-22 17:29:13 +00:00
Kyösti Mälkki b3a411cc7d sb,soc/intel: Drop unnecessary headers
Files under sb/ or soc/ should not have includes that tie those
directly to external components like ChromeEC os ChromeOS
vendorcode.

Change-Id: Ib56eeedaa9d7422e221efa9c8480ed5e12024bca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48765
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-22 17:28:23 +00:00
Marshall Dawson 42af26c527 soc/amd/common/psp: Remove files from bootblock
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I8d775d2d813cf92245f3be4d41b3295ca6da18ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48798
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-22 17:07:07 +00:00
Marshall Dawson af55b3f927 soc/amd/stoneyridge: Remove unused psp.h
psp.h was first included when Stoney Ridge began loading the first
SMU firmware.  That step was later moved from bootblock to romstage.

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Id646390ce377143d09455f797de1b149dbb615b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48797
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-22 17:06:12 +00:00
FrankChu cff6ad8c51 mb/google/volteer: Add GPIO to drobit support
Add support for gpio driver for drobit

BUG=b:175351914
BRANCH=none
TEST=emerge-volteer coreboot

Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I54ba182c6da3db282961b3c72a4d2d11d1001e95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-22 16:08:59 +00:00
FrankChu 8d3c397285 mb/google/volteer: Update SPD table for drobit
drobit memory table as follow:
value	Vendor	Part number
0x00	MICRON	MT53E512M32D2NP-046 WT:E
0x00	HYNIX	H9HCNNNBKMMLXR-NEE
0x01	MICRON	MT53E1G32D2NP-046 WT:A
0x02	HYNIX	H9HCNNNCPMMLXR-NEE

BUG=b:175351914
BRANCH=none
TEST=emerge-volteer coreboot

Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Icd9439f8449856d4ec6798a4e4310dd139bce05f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48496
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-22 16:08:51 +00:00
FrankChu afd5fd6d76 mb/google/volteer: Update drobit device tree
Update drobit device tree override to match schematics.

BUG=b:175351914
BRANCH=none
TEST=emerge-volteer coreboot

Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I48a3024df4270b111b90c4fb56847aad6e65bfa1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-22 16:08:45 +00:00
Michael Niewöhner 490120e1bb mb/clevo/cml-u: move gpio early init to bootblock_mainboard_early_init
Move gpio early init to bootblock_mainboard_early_init to make the
bootblock console work as early as possible.

Change-Id: I619f7d0e15adae284b606dd20c3c1f04f3eafd7b
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48801
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-22 13:44:16 +00:00
Felix Singer b2a749d4ac Revert "mb/clevo/cml-u: drop duplicated configuration of UART pads"
This reverts commit 1a0071c711.

Reason for revert:
UART pad configuration should not be done in common code, since it
could cause short circuits if the user configures a wrong UART index.

Change-Id: I6022935eaab748f82c6330be0729ff72f4880493
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-22 13:43:17 +00:00
John Su 6c0aba2059 mb/google/zork/var/vilboz: Add enable acp_i2s_use_external_48mhz_osc flag
Add enable acp_i2s_use_external_48mhz_osc flag and then
WWAN sku will use external clock source at next build.

BUG=b:174121847
BRANCH=zork
TEST=build vilboz and check MISC_CLK_CNTL1.

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Ida747938373f648524b1e7f34bc69e372a69c4f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48556
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-22 03:47:15 +00:00
Huayang Duan e05298b1d2 soc/mediatek/mt8192: Do dramc software impedance calibration
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: I2c6ffe885717997540a0a9721310e355a3b6a87d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-22 03:00:56 +00:00
Huayang Duan cc064c6c93 soc/mediatek/mt8192: Do EMI init before dram calibration
Reference datasheet:
  External Memory Interface (EMI).pdf, Document No: RH-A-2020-0055.

Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: I3b778698a09c999252fef3153ac1e869ea9d90cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-22 03:00:32 +00:00
Huayang Duan 131f3435fc soc/mediatek/mt8192: Do memory pll init before calibration
Memory PLL is used to provide the basic clock for dram controller
and DDRPHY. PLL must be initialized as predefined way.
First, enable PLL POWER and ISO, wait at least 30us, release ISO, then
configure PLL frequency and enable PLL master switch.
At last, enable control ability for SPM to switch between active and
idle when system is switched between normal and low power mode.

TEST=Confirm Memory PLL frequency is right by frequency meter

Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: Ieb4e6cbf19da53d653872b166d3191c7b010dca6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-12-22 03:00:07 +00:00
Marc Jones 63e2a84d59 soc/intel/xeon_sp: Use common block ACPI
Use the common block ACPI to further reduce the duplicate code.

Change-Id: If28d75cbb2a88363d70e3ae6a2cace46cb6bbbab
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48248
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-22 02:59:18 +00:00
Felix Singer f65945fe8c Revert "mb/clevo/kbl-u: drop duplicated configuration of UART pads"
This reverts commit ccceb2250e.

Reason for revert:
UART pad configuration should not be done in common code, since it
could cause short circuits if the user configures a wrong UART index.

Change-Id: Idc268debc60a027ed2f5a76e0de8ea2d1cde0fc4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-21 22:12:41 +00:00
Angel Pons db27d6f6d0 mb/prodrive/hermes: Update USB 2.0 settings
Test results show that USB signals look better with these settings.
Yes, there's a macro in the devicetree now. All ports use the same
settings except for the overcurrent pin, so this avoids redundancy.

Change-Id: Ib0dafab88d8dcc05388b724f6a7183c13ac64934
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48694
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-21 19:30:05 +00:00
rasheed.hsueh 3b879f46b4 mb/google/octopus/var/phaser: Add support for G2TOUCH Touchscreen
Add devicetree configuration for G2TOUCH Touchscreen controller.

BUG=b:175513059
BRANCH=octopus
TEST=build bios, check i2c bus and verify touch screen works fine

Change-Id: Ib57597c4998f205c664e13befb4c44532b7dbd4f
Signed-off-by: rasheed.hsueh <rasheed.hsueh@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-12-21 02:38:39 +00:00
Patrick Rudolph 2bea58db60 drivers/tpm/ppi_stub: Fix interface version
The latest version defined by TCG is 1.3.

Change-Id: Idb12e2212d6d38c720c8fe989678724c871af6ef
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45569
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-21 02:38:28 +00:00
Patrick Rudolph 39d6927609 drivers/tpm: Implement full PPI
Implement the ACPI PPI interface as described in
"TCG PC Client Physical Presence Interface Specification" Version 1.3.

Add a new Kconfig that allows to use the full PPI instead of the stub
version compiled in.

This doesn't add code to execute the PPI request, as that's up to the
payload with graphical UI support.

Tested on GNU/Linux 5.6 using the sysfs interface at:
/sys/class/tpm/tpm0/ppi/

Change-Id: Ifffe1d9b715e2c37568e1b009e86c298025c89ac
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45568
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-21 02:38:20 +00:00
Tao Xia f20151dfaa mb/google/dedede/var/storo: Generate SPD ID for supported memory parts
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the memory parts. The memory parts being added are:
MT53E512M32D2NP-046 WT:E
H9HCNNNBKMMLXR-NEE
MT53E1G32D2NP-046 WT:A
H9HCNNNCPMMLXR-NEE

BUG=None
TEST=Build the storo board.

Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: Ifd935865927bb9fccf95eb4924ca6986d0c19442
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-12-21 02:37:39 +00:00
rasheed.hsueh 8dad8248d4 mb/google/dedede: Update Boten setting for USI PEN detection.
Update devicetree and gpio driving of boten that enable stylus

PEN detect signal is not dual-routed on Boten. Since the gpio_keys kernel
driver expects the pad to be owned by GPIO controller (i.e. configured for
GPIO IRQ), it cannot be configured for ACPI (i.e. SCI).
Thus, this change updates the GPIO configuration for GPP_C12 to
PAD_CFG_GPI_GPIO_DRIVER and device tree entry for PENH device to
use WAKEUP_ROUTE_GPIO_IRQ. Additionally, the signal is marked as active
low in the device tree entry to indicate to the kernel driver that the signal
is inverted.

Not dual routing the signal results in wake source not being added to
eventlog when pen removal results in wake from S0ix.

BUG=b:160752604
BRANCH=dedede
TEST=Build and check behavior is expected.

Signed-off-by: rasheed.hsueh <rasheed.hsueh@lcfc.corp-partner.google.com>
Change-Id: I74a17088da64c22ef1c74d201c80274fc65a44c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-12-21 02:37:29 +00:00
Arthur Heymans 45a6ae35ef soc/intel/xeon_sp/skx: Properly set up MTRR's
Don't depend on the MTRR setup left over from FSP-M ExitTempRam.

Change-Id: I299123b3cd3c37b4345102c20fda77bf261892a2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-12-21 02:37:13 +00:00
Arthur Heymans 08d8dd3bd3 soc/intel/xeon_sp: Fix compiling with CONFIG_DEBUG_RESOURCES
Change-Id: I42ddea2c04bf1ecb2466db3d56d15d51bda486c8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2020-12-21 02:37:04 +00:00
Patrick Rudolph 9c581a74f6 mb/prodrive/hermes: Enable S3/S4 resume
Change-Id: I75f83bcc6c65a048e87f7295a66526eb384afc5d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-21 02:36:47 +00:00
V Sowmya ce07b5c0ab mb/intel/shadowmountain: Add Intel Pre-CEP shadowmountain board
This patch adds initial support for Alderlake Intel Pre-CEP
board called shadowmountain.

BUG=b:175808146
TEST=util/abuild/abuild -p none -t intel/shadowmountain -a -c max

Change-Id: I9cb650c88986badd6733b001d6f2a0e338421829
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-21 02:36:40 +00:00
Nick Chen 04da829a0f volteer/variants/eldrid: Enable RTD3 for the NVMe device
Enable Runtime D3 for the volteer variants that have GPIO power control
of the NVMe device attached to PCIe Root Port 9.

Enable the GPIO for power control for variants that do not already have
it configured to allow the power to be disabled in D3 state.

BUG=b:161270810
TEST=tested on eldrid

Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Change-Id: I941c8a9bb3221ad90528c323cd0f267dc77d2af3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-21 02:36:31 +00:00
Marc Jones 847043c207 soc/intel/common/block/acpi: Add soc MADT IOAPIC hook
Add a hook for SOCs to provide an IOAPIC MADT table. If the
SOC doesn't provide a table then a standard setting is used.

Change-Id: Ic818a634e4912d88ef93971deb4da5ab708c9020
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-21 02:35:21 +00:00
Chris Wang cbe1244071 soc/amd/picasso: Add UPDs for support eDP phy tunning adjust
Add UPDs for eDP phy tunning adjust

BUG=b:171269338
BRANCH=zork
TEST=Build, verify the parameter pass to picasso-fsp

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I6df063f828447841ac9a6dba00a4aad2001f04df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-12-21 02:34:32 +00:00
Zheng Bao bf29a0d21f amdfwtool: Add support of cezanne and renoir
Change-Id: I9e932631e88062b4c385567ed2eff76eda6e10c4
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48525
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-21 02:34:15 +00:00
Marc Jones a81703c37b soc/intel/common/block/acpi: Make calculate_power() global
Change static calculate_power() function to global and update the name
to common_calculate_power_ratio() for SOC ACPI code use.

Change-Id: I0e2d118ad52b36859bfc6029b7dee946193841f4
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
2020-12-21 02:32:44 +00:00
Michael Niewöhner 1aa8fc3cef drivers/intel/fsp2_0: recreate FSP targets on config change
When a different FSP binary was chosen in menuconfig, the split fd files
do not get updated. Thus, make them depend on `.config` to trigger a
rebuild when the config changes.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I54739eae50fa1a47bf8f3fe2e79334bc7f7ac3d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-21 02:32:16 +00:00
Maulik V Vaghela c5603145d3 Revert "mb/google/dedede: Update Imon slope and Offset Value for Drawcia"
Falling back to default values for Imon slope and offset for Drawcia
This is as per recommendation from ODM based on calibration

This reverts commit 2ac88f2347.

BUG=b:175629526
BRANCH=dedede
TEST=Debug FSP confirms that values are reverted to default

Change-Id: I605acdcd0de2c5dfc28af2aea8cefc6b629c0925
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48737
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-21 02:32:05 +00:00
FrankChu bc89e8337c mb/google/dedede: Add GPIO to galtic support
Add support for gpio driver for galtic

BUG=b:170913840
BRANCH=dedede
TEST=emerge-dedede coreboot

Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I01bb95545705efab1a2adf1582b6293fd89e6420
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48684
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-21 02:31:50 +00:00
Dtrain Hsu 85adcdbff4 mb/google/dedede/var/madoo: Configure Acoustic noise mitigation UPDs
Enable Acoustic noise mitigation for madoo and set slew rate to 1/8
which is calibrated value for the board. Other values like PreWake,
Rampup and RampDown are 0 by default.

BUG=b:173765599
BRANCH=dedede
TEST=Correct value is passed to UPD and Acoustic noise test passes.

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I968d8d43016e3569835b0a777335fa1d5c135f87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-12-21 02:31:42 +00:00