Commit Graph

37756 Commits

Author SHA1 Message Date
Kangheui Won 68e5fd2a5c Update vboot submodule to upstream master
Updating from commit id 4bb06cc1:
    COIL: Change denylist to blocklist

to commit id 4c523ed1:
    vboot2: Add support for modexp acceleration

This brings in 10 new commmits.

Change-Id: Iff6eb99c8ed3046b6fdb6c1e2892aab956f3b562
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-10-07 04:24:26 +00:00
Kangheui Won 9958731815 amd/picasso/psp_verstage: Add modexp svc wrapper
The PSP bootloader version 0.08.0B.7B added support for the Mod Exp
svc call.

BUG=b:169157796
BRANCH=zork
TEST=build verstage for zork

Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Ifdbf20544b21b7fa90a49c5497ff4a5da61bebb1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-10-07 04:23:47 +00:00
Martin Roth 9cf3298360 vc/amd/fsp: Update the svc call header for the Mod Exp SVC
The PSP bootloader version 0.08.0B.7B added support for the Mod Exp
svc call.

BUG=b:169157796
TEST=Build
BRANCH=Zork

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I1ce69c80cec77e1692cf9713a739cc4da4677da6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45942
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-07 04:23:04 +00:00
Furquan Shaikh 58d39d07a1 drivers/intel/wifi: Drop call to pci_dev_init
`pci_dev_init()` is used to load and run option ROM on VGA class
devices (PCI_CLASS_DISPLAY_VGA). WiFi device is not a VGA class device
and hence the call to `pci_dev_init()` is not required. This change
drops the call to `pci_dev_init()` from `wifi_pci_dev_init()` in Intel
WiFi driver.

BUG=b:169802515
BRANCH=zork

Change-Id: I6588ea0a5c848904088d05fd1cbdf677b2dc8ea9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-10-07 01:16:12 +00:00
Furquan Shaikh 7cb103461a drivers/wifi/generic: Use pci_dev_* operations for device ops
WiFi devices supported by the generic WiFi driver are PCIe devices
which need to be managed using the standard pci_dev_* operations to
read, set and enable resources. This change updates the
device_operations structure `wifi_generic_ops` to use the standard
pci_dev_* operations for these devices.

BUG=b:169802515
BRANCH=zork

Change-Id: I8b306259e205ecb963c0563000bd96ec6b978b8b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-10-07 01:15:54 +00:00
Paul Fagerburg f52e4a03ec templates: add an empty SPD to SPD_SOURCES
Add an empty SPD in SPD_SOURCES when creating a new variant of
hatch, volteer, waddledee, or waddledoo, so that coreboot can build
successfully.

For variants that use spd_tools, add an empty mem_parts_used.txt so
that the developer can add the supported memory parts and regenerate
the Makefile.inc with the correct SPD references.

Add an empty SPD for LPDDR4x for waddledee and waddledoo to use.

BUG=b:169422833
TEST=create a new variant of hatch, volteer, waddledee, and waddledoo.
Observe that each one succeeds.

Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: I06dfb6103701bf8949180595f1e98fac48bcc585
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-10-06 18:27:31 +00:00
Marc Jones 882a5687e6 drivers/ipmi/ocp/ipmi_ocp.c: Clean up includes
Remove #include "chip.h", which is not needed and causes a build
problem in a later change. Alphabetise the #includes. Add <types.h>.

Change-Id: If19ccd144bd352a196adccd75f9f6f139eae4e4a
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45968
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-06 17:43:38 +00:00
Marc Jones 301c7e67bf soc/intel/xeon_sp/skx: Move get_srat_memory_entries()
Prepare for common ACPI code.
Move get_srat_memory_entries() from soc_util.c to soc_acpi.c where
the other srat ACPI functions are located.

Change-Id: If26641497e1c16d5cf493490711aa08d6e1cb640
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45846
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-06 15:27:14 +00:00
Marc Jones 70ddbd8ce1 soc/intel/xeon_sp/cpx: Don't use SCI define
Continue preparations for common ACPI code.
Add code from skx and common/acpi to check the SCI register
instead of using a define.

Change-Id: I6b638d28775320894a6ab24ef486e67c181591eb
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45844
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-06 15:19:08 +00:00
Marc Jones ccfaf253b5 soc/intel/xeon_sp/skx: Move soc specific ACPI functions
Prepare for common ACPI code. Move skx soc ACPI functions to a
separate file.

Change-Id: I12526c17a0dcbc45494ae19c8abaf8bf9a1eab47
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-06 15:18:31 +00:00
Marc Jones 392bcca0c9 soc/intel/xeon_sp/cpx: Move soc specific ACPI functions
Prepare for common ACPI code. Move cpx soc ACPI functions to a
separate file, soc_acpi.c

Change-Id: I4aaca660e2f94d856676681417ae6c5d8c28a1f1
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-06 15:17:29 +00:00
Marc Jones 9f55574c90 soc/intel/xeon_sp/skx/: Reorder acpi.c functions
Reorder the functions to make it easier to compare with
soc/intel/common/block/acpi/acpi.c and cpx/acpi.c.

Move the xeon_sp specific functions to the top.

Change-Id: I7bc147781261c2fc39374f5bfe3ba79047b4993a
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-06 15:17:07 +00:00
Marc Jones 2bb09b418f soc/intel/xeon_sp/cpx/: Reorder acpi.c functions
Reorder the functions to make it easier to compare with
soc/intel/common/block/acpi/acpi.c.

Move the xeon_sp specific functions to the top.

Change-Id: I9034eb774a14ee1e2f9b16c7bd7673ebad69c113
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-06 15:16:44 +00:00
Marc Jones c1ba1d1e15 soc/intel/xeon_sp/acpi: Break out the ACPI PCH IRQ ASL
Continue separating the CPU from the PCH.
Move the PCH IRQ ASL from the uncore_irq.asl to a new file,
pch_irq.asl.

Change-Id: Iaf8ae87ecc9f8365cc093516f15d9c5a31c7d1d5
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-06 15:16:13 +00:00
Marc Jones efb583a6e9 soc/intel/xeon_sp/acpi: Move ACPI macros to a header file
Move ACPI macros to a header file to be used in multiple
ASL files.

This could be moved to intel/common in the future to reduce
the amount of duplicate ASL code.

Tested by checking build/dsdt.asl doesn't change.

Change-Id: Id2441763fe335154048c9a584a227a18e8c5391c
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-06 15:15:46 +00:00
Marc Jones b89624c558 soc/intel/xeon_sp/acpi: Remove ASL Package() NumElements
Remove the NumElements and allow the ASL compiler to fill them in.
This is safer than hard coding the NumElements.

For Package (NumElements) {PackageList}, "If NumElements is absent,
it is automatically set by the ASL compiler to match the number of
elements in the PackageList"  ACPI v6.2 sec 19.6.101.

Change-Id: I73df9e31011ad0861d4755fdbcbbd93e4e0b5a51
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-06 15:15:05 +00:00
Subrata Banik 0b11ff8aa8 soc/intel/alderlake/ramstage: Fix compilation issue
Refer to
commit 0359d9d (soc/intel: Make use of PMC low power program
from common block)
commit 1366e44 (soc/intel: Move pch_enable_ioapic() to common
code)
commit 78463a7 (soc/intel: Move soc_pch_pirq_init() to common code)
commit 8971ccd (soc/intel: Move pch_misc_init() to common code)
for details

Change-Id: Ic83d332cf2bfe8eded1667dd1503e718d854f10b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-06 12:30:15 +00:00
Subrata Banik 0808992441 soc/intel/alderlake/acpi: Add SoC ACPI directory for ADL
List of changes:
1. Select common ACPI Kconfig to include common ACPI code block
from IA-common code
2. Select ACPI Kconfig support for wake up from sleep states.
3. Add SoC ASL code in ASL 2.0 syntax for SoC IPs like IPU, ISH,
LAN, HDA etc.

Change-Id: I7509e8c46038b1edfc501db74e763f198efb56ab
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-06 12:29:58 +00:00
Lucas Chen 1fa35859fe zork/var/ezkinil: Adjust Touchscreen suspend off timing
Adjust Touchscreen delay off values to let suspend off timing match
power down specificatiion.

BRANCH=zork
BUG=b:163434386
TEST=Measuring scope timing

Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Change-Id: I58866122f441cc3c427e659b8a5fdb6643987882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2020-10-06 03:25:30 +00:00
John Zhao 6e8d38ec4e soc/intel/tigerlake: Update TCSS PM flow
There is requirement to change PM flow for S0ix along with TBT firmware
update under device attached and no device attached scenarios. This
change invokes D3CE and D3CX in DMA _PS3 and _PS0 respectively.

BUG=b:158777291
TEST=Validated s0ix cycles for USB4 device attached and no device
attached test cases along with updated TBT firmware rev35.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Iebc8065fe4c8600960d089577608890ab12a95fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-05 22:41:16 +00:00
Daisuke Nojiri ab2ad3f2f9 Fleex: Resume from suspend on critical battery
This patch makes Fleex EC wake up AP from s0ix when the state of
charge drops to 5%.

Demonstrated as follows:

1. Boot Fleex.
2. Run powerd_dbus_suspend.
3. On EC, run battfake 5.
4. System resumes.

BUG=b:163721887
BRANCH=Octopus
TEST=Verified on Fleex:

Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I4a998ad0aef5a7cfc6fd18995bde5571e6127e77
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-10-05 20:44:28 +00:00
Nick Vaccaro dfcd739fc7 lib/spd_bin: add LPDDR4X case to spd_get_name()
Add case for LPDDR4x to spd_get_name().

BUG=b:169800932, b:168724473
TEST=none

Change-Id: I6bae373468b8ad5ae0a6b8dd6bbe14143afb85af
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45886
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05 18:03:46 +00:00
Nick Vaccaro be34b500a6 mb/google/hatch,dedede,volteer: enable CHROMEOS_DRAM_PART_NUMBER_IN_CBI
Enable CHROMEOS_DRAM_PART_NUMBER_IN_CBI on hatch, dedede, and volteer
to use the common version of mainboard_get_dram_part_num().

Remove duplicate instances of mainboard_get_dram_part_num().

BUG=b:169789558, b:168724473
TEST="emerge-volteer coreboot && emerge-hatch coreboot &&
emerge-dedede coreboot" and verify it builds.

Change-Id: I4e29d3e7ef0f3370eab9a6996a5c4a21a636b40e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45883
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05 18:03:38 +00:00
Nick Vaccaro 53b99a84a5 soc/intel: remove duplicate weak versions of mainboard_get_dram_part_num()
Consolidate all weak declarations of mainboard_get_dram_part_num() to
instead use the common definition in lib/spd_bin.c.

BUG=b:168724473
TEST="emerge-volteer coreboot && emerge-nocturne coreboot &&
emerge-dedede coreboot" and verify build succeeds without error.

Change-Id: I322899c080ab7ebcf1cdcad3ce3dfa1d022864d1
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-05 18:03:22 +00:00
Nick Vaccaro edecf46187 vendorcode/google: add CHROMEOS_DRAM_PART_NUMBER_IN_CBI Kconfig option
Add CHROMEOS_DRAM_PART_NUMBER_IN_CBI Kconfig option to declare whether
the SPD Module Part Number (memory part name) is stored in the CBI.

Move mainboard_get_dram_part_num() into src/vendor/google/chromeos
to allow mainboards to use it without having to duplicate that code
by enabling the CHROMEOS_DRAM_PART_NUMBER_IN_CBI config option.

BUG=b:169789558, b:168724473
TEST="emerge-volteer coreboot && emerge-hatch coreboot &&
emerge-dedede coreboot && emerge-nocturne coreboot" and verify it
builds.

Change-Id: I0d393efd0fc731daa70d3990e5b69865be99b78b
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-05 18:02:51 +00:00
Nick Vaccaro 3b24bb6fc8 soc: move mainboard_get_dram_part_num prototype to memory_info.h
BUG=b:169774661, b:168724473
TEST="emerge-volteer coreboot && emerge-nocturne coreboot &&
emerge-dedede coreboot" and verify they build successfully.

Change-Id: I8b228475621ca1035fe13f8311355fc3b926e897
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-05 18:02:37 +00:00
Nick Vaccaro 0ed02d00cb mb, soc: change mainboard_get_dram_part_num() prototype
Change mainboard_get_dram_part_num() to return a constant character
pointer to a null-terminated C string and to take no input
parameters.  This also addresses the issue that different SOCs and
motherboards were using different definitions for
mainboard_get_dram_part_num by consolidating to a single definition.

BUG=b:169774661, b:168724473
TEST="emerge-volteer coreboot && emerge-dedede coreboot && emerge-hatch
coreboot" and verify build completes successfully.

Change-Id: Ie7664eab65a2b9e25b7853bf68baf2525b040487
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45873
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05 18:02:22 +00:00
Nick Vaccaro aef9ac97c7 soc/intel/elkhartlake: add __weak to mainboard_get_dram_part_num()
Add missing __weak declaration to Elkhart Lake's definition of
mainboard_get_dram_part_num().

BUG=b:169774482, b:168724473
TEST=none

Change-Id: I883d662315a9ab91eb6183ebcdfd7e7cc8064c64
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45871
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05 18:02:05 +00:00
Angel Pons 8975e7b025 lib/ubsan.c: Remove GCC 5.x workaround
The coreboot toolchain has been using a newer GCC version for a while
already. This code is build-tested from commit 13cd145e02 onwards.

Change-Id: Ic324b503878c73e4560d4d8f2e0d38ecb595b8fd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45822
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05 16:18:24 +00:00
Subrata Banik cf0ac156c4 soc/intel/tigerlake/acpi: Convert 'pch_hda.asl' into ASL 2.0 syntax
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I8deaeb29abed097d536f1c3c44606a549c6af4e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-05 15:18:05 +00:00
Subrata Banik 37a42da465 soc/intel/common/block/acpi: Factor out common ish.asl
This patch moves ish.asl into common block acpi directory to
avoid duplicating the same ASL code block across SoC directory.

TEST=Able to build and boot TGL, CML platform.
1) Dump and disassemble DSDT, verify ISHB device present inside
common ish.asl is still there with correct _ADR value.
2) Verify no ACPI error seen while running 'dmesg` from console.

CML platform:

Device (ISHB)
{
  Name (_ADR, 0x00130000)  // _ADR: Address
  Name (_DDN, "Integrated Sensor Hub Controller")  //_DDN: DOS Device Name
}

TGL/JSL platform:

Device (ISHB)
{
  Name (_ADR, 0x00120000)  // _ADR: Address
  Name (_DDN, "Integrated Sensor Hub Controller")  //_DDN: DOS Device Name
}

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I33c1649d7a632c7b147e1bf307cfb5c1dfd84c0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-05 15:17:53 +00:00
Angel Pons b70c66b00d nb/intel/ironlake: Drop unnecessary `smm_region_start` function
Change-Id: I4c4b40b2b4f54b7756b8485dad80a1b4786270f7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-05 09:19:28 +00:00
Angel Pons 11ca2ae167 nb/intel/ironlake/memmap.c: Clean up includes
Drop unused includes and add missing <types.h>.

Change-Id: Ifefe81d4727d67ea702c5e24527f80a0614aa396
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-10-05 09:19:08 +00:00
Zheng Bao 9c8ce3e423 amdfwtool: Remove the assumption of ROM_SIZE
Every platform passes (and need to) the --flashsize to the command
parameter, so we remove the macro definition about a built-time
romsize defined in Makefile.

Change-Id: I894e833ed23a7da38b36986b624e7dcdf1f4090c
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-05 08:37:46 +00:00
Zheng Bao 473969163d amdfwtool: Use a variable to get the return value of write
New Jenkins complaint about the original code that return
value gets to nowhere. Fix that with a new variable.

Change-Id: I8099b856ccb751dc380d0e95f5fe319cc3e2c6cc
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45812
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05 08:37:37 +00:00
Zheng Bao 7698a55202 amdfwtool: Clean up the Makefile of amdfwtool
Add Makefile.inc to compliant with other tools.
Makefile is kept for building amdfwtool by typing make
in the folder.

Change-Id: I3688d93de4459f5f838955892086b4b9bf30a9b8
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-10-05 08:37:28 +00:00
Mario Scheithauer 8725c0af09 mb/siemens/mc_apl6: Enable eMMC
Enable eMMC with HS200 mode for mc_apl6 mainboard.

TEST: Linux booted and checked with 'lspci'.

Change-Id: Ib760a1a26a92047e8916979ffb5001bcff0a6e45
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45898
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05 05:11:03 +00:00
Subrata Banik 6577ec4de4 soc/intel/common/block/acpi: Factor out common platform.asl
This patch moves platform.asl into common block acpi directory to
avoid duplicating the same ASL code block across SoC directory.

TEST=Able to build and boot TGL, CNL and CML platform.
1) Dump and disassemble DSDT, verify _PIC method present inside
common platform.asl is still there.
2) Verify no ACPI error seen while running 'dmesg` from console.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I5189b03d6abfaec39882d28b40a9bfa002128be3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-05 04:01:40 +00:00
Subrata Banik ae63c1e013 soc/intel/{cnl,icl,skl}: Convert 'platform.asl' to ASL 2.0 syntax
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I3fcd971402e540d91a7392ca58175eb3ecc24cec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45981
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05 04:00:46 +00:00
Subrata Banik 319a91f894 soc/intel/skylake: Align platform.asl with CNL
Refer _WAK and _PTS ASL functions from common platform.asl

TEST=Dump and disassemble DSDT, verify all methods present inside
common platform.asl like _WAK, _PTS etc. are still there.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I625e42b3c49abbb3595a4307da5fc24850a98fbb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45980
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05 04:00:34 +00:00
Subrata Banik 3b3bbd4fba soc/intel/common/block/acpi: Factor out common smbus.asl
This patch moves smbus.asl into common block acpi directory to
avoid duplicating the same ASL code block across SoC directory.

TEST=Able to build and boot TGL, CNL and CML platform.
1) Dump and disassemble DSDT, verify SBUS device present inside
common smbus.asl is still there.
2) Verify no ACPI error seen while running 'dmesg` from console.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Ib1ae48f7ece3e521501d92c40cd551287ea2f1ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-05 04:00:19 +00:00
Subrata Banik 73968fd14b mb/{google,intel}/{volteer,tglrvp}: Refer to common IPU ASL
Delete SoC local copy of ipu.asl and refer from common block ipu.asl

TEST=Dump and disassemble DSDT on tglrvp, verify IPU0 device
present there.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I6a0f8a919092f7bbcd64d4791746d30fdee33894
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-05 04:00:05 +00:00
Subrata Banik 500c245f3c soc/intel/jasperlake: Delete unused ipu.asl
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I8c7363d442ed40c36fc01dc3608bab864865f29d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45977
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05 03:59:43 +00:00
Subrata Banik 415b598742 soc/intel/common/block: Rename IPU ACPI device
IMGU->IPU0 to align with other SoC IPU entires.

TEST=Dump and disassemble DSDT on poppy, verify IPU0 device
present there.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I803c01f9156a56dbd903b6ba7897cc0f96b0a26a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-05 03:59:34 +00:00
Subrata Banik d2becae223 soc/intel/common/block/acpi: Factor out common pch_glan.asl
This patch moves pch_glan.asl into common block acpi directory to
avoid duplicating the same ASL code block across SoC directory.

TEST=Able to build and boot TGL, CNL and CML platform.
1) Dump and disassemble DSDT, verify GLAN device present inside
common pch_glan.asl is still there.
2) Verify no ACPI error seen while running 'dmesg` from console.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I479678c864eba39e5ab04f658600e8cba48198ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45975
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-05 03:59:08 +00:00
Rob Barnes 34cf7ccebc Revert "util/spd_tools: output binaries instead of hexdumps"
This reverts commit f23794cf04.

Reason for revert: This change breaks compatibility if the changes
in CB:44775 are not also included. CB:44775 is still under discussion,
so revert this change to make spd_tools usable again.

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I5840a1b895dcbc8b91c76d8b60df2f95b93a4370
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44999
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03 16:29:00 +00:00
Subrata Banik 2871e0e78c soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage
List of changes:
1. Add required SoC programming till ramstage
2. Include only required headers into include/soc
3. Add CPU, PCH and SA EDS document number and chapter number
4. Fill required FSP-S UPD to call FSP-S API

Change-Id: I3394f585d66b14ece67cde9e45ffa1177406f35f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-03 12:15:22 +00:00
Marc Jones 95bab4077e soc/intel/xeon_sp/acpi: Rename pci_irq.asl
Rename pci_irq.asl to pci_irqs.asl to match other intel soc file
names. This makes comparing differences much easier.

Change-Id: I622dfef675c3df2dff7a3024ccbe14c356a5cd86
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45834
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03 09:30:13 +00:00
Marc Jones 9f0c000227 soc/intel/xeon_sp: Clean up pci_devs.h
Prepare for merging cpx and skx pci_devs.h.

Remove duplicate defines. Move defines so they match each other.

Checked TiogaPass and DeltaLake BUILD_TIMELESS.

Change-Id: I146dd9e3f7eba053977d48dcf34d927dea310059
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45833
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03 09:29:53 +00:00
Subrata Banik 0359d9dde3 soc/intel: Make use of PMC low power program from common block
List of changes:
1. Select PMC_LOW_POWER_MODE_PROGRAM from applicable SoC directory
2. Remove redundant PMC programming from SoC and refer to common
code block
3. Remove unused 'reg8' and 'reg32' variable as applicable from SoC
function.

Change-Id: I18894c49cfc6e88675b5fb71bca0412e5639fb4b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45796
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-03 06:58:07 +00:00