The existing rule created a potential race condition between creating
the directory and putting files in there, so use our existing
infrastructure for directory creation instead.
Change-Id: If52a9f558c7d9ce85f71ba53232594699c9d357a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37798
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When regions are resized they are always aligned to the top of the
region. For the BIOS region this is correct. The other regions however
should be aligned to the bottom of the region.
Update the region handling to only align BIOS region to top of region.
BUG=N/A
TEST=verified image resize
Change-Id: Ied0e763b5335f5f124fc00de38e5db1a4d0f6785
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Update the two flashrom URLs to use HTTPS. All other URLs are already
using HTTPS.
Change-Id: I8e9861b2748289522ab418960a463ae55ab0d2d3
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
According to intels datasheet
Document Number: 341078-001
10th Generation Intel® Core™ Processor Families
Volume 2 of 2
we can dump the ICL MCHBAR similiar as on 8th / 9th gen CPUs.
The difference is that on ICL the MCHBAR address is definited by
the bits 38:16 instead of 38:15 giving the constraint that it has
to be 64kbit instead of 32kbit aligned. (Section 3.1.13)
Change-Id: Ia597a4b3738c11cb48ce5808d8459b4a2a768077
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Build the smcbiosinfo tool with other tools.
Fixes possible race condition on jenkins.
Change-Id: I38f7ee2fdef2818ad685b3de53ad74f7da50600f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Match each of the possible APCB items with a corresponding backup APCB.
A missing backup copy can prevent the system from booting.
Change-Id: I400194b2763239896214ea42cfe6fbeb8ed261a8
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The BMC and tools interacting with it depend on metadata placed inside
the ROM in order the flash the BIOS.
Add a new tool smcbiosinfo, integrate it into the build system, and
generate a 128byte metadata file called smcbiosinfo.bin on build.
You need to provide the BoardID for every SMC mainboard through a new
Kconfig symbol: SUPERMICRO_BOARDID
Some fields are unknown, but it's sufficient to flash it using SMC
vendor tools.
Tested on Supermicro X11SSH:
* Flashing using the WebUI works
* Flashing using SMCIPMITool works
No further validation is done on the firmware.
Change-Id: Id608c2ce78614b45a2fd0b26d97d666f02223998
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
In preparation to update to SPDX license headers, add identifiers
for the licenses seen in the coreboot project and create a command
line parameter allowing only SPDX license identifiers to be detected.
Here are example locations of these licenses:
Apache-2.0 - src/soc/sifive
BSD-3-Clause - Throughout coreboot & libpayload source
GPL-2.0-only - Throughout coreboot source
GPL-2.0-or-later - Throughout coreboot source
GPL-3.0-only - util/amdtools
GPL-3.0-or-later - src/lib/[gcov/libgcov/gnat]
ISC - src/lib/ubsan.c, soc/qualcomm/ipq806x/include/soc/gsbi.h, others
MIT - soc/nvidia/tegra210/mipi_dsi.c, files in mainboard/cavium/
X11 - include/device/drm_dp_helper.h, drivers/aspeed/common/ast_tables.h
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I07a7ca408ac8563e03e189d05ef7729dfb6fc24e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
create_coreboot_variant.sh now supports the Volteer baseboard in
addition to Hatch. The shell script and supporting python code are
moved up one level, while retaining the ${BASE}/template/* file
structure for each supported baseboard.
kconfig.py has to add slightly different text to Kconfig.name
depending on which baseboard is selected.
BRANCH=None
BUG=b:146646594
TEST=Create variants of Hatch and Volteer, check that the staged
commits are correct.
$ ./create_coreboot_variant.sh hatch sushi b:12345
src/mainboard/google/hatch/Kconfig and Kconfig.name will have new
sections for SUSHI. src/mainboard/google/hatch/variants/sushi
will have a copy of util/mainboard/google/hatch/template
$ ./create_coreboot_variant.sh volteer ripto b:12345
src/mainboard/google/volteer/Kconfig and Kconfig.name will have new
sections for RIPTO. src/mainboard/google/volteer/variants/ripto
will have a copy of util/mainboard/google/volteer/template
Also run the script with an existing board name to verify that you
can't create a variant that already exists.
Change-Id: I084b6c50bb76af0d11dc86a96b3c3c434569a0dd
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Running the x86_64 qemu mainboard target with '-accel kvm' results in hang,
as the 'D' and 'A' bits needs to be set in read only page tables.
Tested on QEMU Q35: Boots into payload with '-accel kvm'.
Change-Id: I4beae8deec6bf34f9762e7b54c5da4e5b63f6d24
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36778
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The ApolloLake SoC allows two Logical Boot Partitions. This patch
introduces a '-s' optional parameter to select the second Logical
Boot Partition.
Change-Id: If32ec11fc7291d52b821bf95c1e186690d06ba11
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37660
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If the compiler fails to inline all the FORCE_INLINE functions, it will
complain.
Change-Id: I7b8349c9a3d53c47ac189f02b296600abac8a0cf
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37734
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 547de69de7.
Merged out of order before CB:36317. The conflicting use of
_ADR and _HID needs to be properly addressed before we can
bump the IASL version.
Change-Id: Iacbc9877a8ff2324eba4789d65df8545b8a25413
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37713
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
cbfstool depends on vboot headers, and vboot expects to be able to use
modern C features like _Static_assert(). It just so happens that it
doesn't do that in any headers included from cbfstool right now, but
that may change. Let's switch cbfstool to a newer version to prevent
that from becoming a problem.
Change-Id: I884e1bdf4ec21487ddb1bca57ef5dc2104cf8e0e
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* GBB_HWID is no longer used in Hatch Kconfig, so remove the code
that creates the GBB_HWID and adds it to the Kconfig section
* Add more information in the usage message when the cmdline params
are incorrect.
* Remove messages that tell the user what to do, because the top-level
program that invokes this script will handle those commands, and so
this script telling the user what to do is noise (and possibly harmful)
* Add more information to the commit message that the script prepares
for the user.
* Bump script version number.
BRANCH=None
BUG=b:140261109
TEST=Create the "sushi" variant of the "hatch" baseboard:
`util/mainboard/google/hatch/create_coreboot_variant.sh sushi`
Inspect the files in src/mainboard/google/hatch/variants/sushi
Change-Id: I04e949aedce61ed7fc7df681b72c3cfef31b5513
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
This eases maintenance of our kconfig fork.
Change-Id: Ia4bc0bf22e66457356b9f8fcbea9412792495bca
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The old logic only uses the type to identify resources, which makes a
resource in override tree overriding the first resource with the same
type (but possibly different index) in base tree, and resources with
same type (but again different index) in override tree overriding each
other.
Resources had better be identified with both their type and index.
Change-Id: I7cd88905a8d6d1c7c6c03833835df2fba83047ea
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37109
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Binary strings should be joined with a binary string
* Binary files should be opened in binary mode.
* Division that wants truncation should make it explicit.
I have tested that these changes let me compile.
Change-Id: I7c41b80688a9c6bdb3c66561ff531311cc7ebb13
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37024
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Even with four cloc invocations it's faster than doing the rename
dance and messes up the tree less. It also opens up using cloc's git
mode to work on a git tree instead of a checkout.
Change-Id: I3ad8fc6802ecedb332359d00b28ea61c33ed2ea0
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
We had two _very_ long lines containing arguments that enumerate the
paths where blobs are stored: Now there's a variable containing them.
Change-Id: I501b27158d00ba00d1c9b9e2f00a17a8b9c3f682
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36955
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
git clone allows using a local repo as reference which reduces the
required network traffic.
Change-Id: I64722cd5dbdfc0c2bcd935715cffdb99b773711c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36954
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPG 2 expects the GPG_TTY variable to be configured so
that it can properly ask for the passphrase. If it's
not already set, do so.
Change-Id: I7e145a492c9eceda40cc1a1e04452a78852042d1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36953
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
I thought gcc ignores -Wno-* stuff that it doesn't know about, but
apparently not.
Change-Id: If265a7bcdcfb5e83cc06b1f914dd6bab964eaca6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The MIPS architecture port has been added 5+ years ago in order to
support a Chrome OS project that ended up going nowhere. No other board
has used it since and nobody is still willing or has the expertise and
hardware to maintain it. We have decided that it has become too much of
a mainenance burden and the chance of anyone ever reviving it seems too
slim at this point. This patch eliminates all MIPS code and
MIPS-specific hacks.
Change-Id: I5e49451cd055bbab0a15dcae5f53e0172e6e2ebe
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34919
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
After removing urara no board still uses this SoC, and there are no
plans to add any in the future (I'm not sure if the chip really exists
tbh...).
Change-Id: Ic4628fdfacc9fb19b6210394d96431fdb5f8e8f1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36491
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This uses less lines, is the original Markdown syntax, and for short
blocks better readable.
Change-Id: Id96ad0f65980dfb943eef3cde5626d56f97622f9
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35729
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Run
- make -C util/docker doc.coreboot.org to build the docker image
- make -C util/docker docker-build-docs to build the documentation
- make -C docker-livehtml-docs to serve autoupdated documentation over
http://0.0.0.0:8000
Change-Id: Ic07f216f8d90d6e212383250b852dc91575304c3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36104
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With GCC 9.x has a new warning *address-of-packed-member*.
> -Waddress-of-packed-member
>
> Warn when the address of packed member of struct or union is
> taken, which usually results in an unaligned pointer value.
> This is enabled by default.
This results in the build errors below, for example, with GCC 9.2 from
Debian Sid/unstable.
src/southbridge/intel/common/spi.c: In function 'spi_init':
src/southbridge/intel/common/spi.c:298:19: error: taking address of packed member of 'struct ich7_spi_regs' may result in an unaligned pointer value [-Werror=address-of-packed-member]
298 | cntlr->optype = &ich7_spi->optype;
| ^~~~~~~~~~~~~~~~~
Therefore, explicitly disable the warning.
Change-Id: I01d0dcdd0f8252ab65b91f40bb5f5c5e8177a293
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36940
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds an optional pre-RAM cache for the FMAP which most
platforms should be able to use, complementing the recently added
post-RAM FMAP cache in CBMEM. vboot systems currently read the FMAP
about half a dozen times from flash in verstage, which will all be
coalesced into a single read with this patch. It will also help
future vboot improvements since when FMAP reads become "free" vboot
doesn't need to keep track of so much information separately.
In order to make sure we have a single, well-defined point where the new
cache is first initialized, eliminate the build-time hardcoding of the
CBFS section offsets, so that all CBFS accesses explicitly read the
FMAP.
Add FMAP_CACHEs to all platforms that can afford it (other than the
RISC-V things where I have no idea how they work), trying to take the
space from things that look like they were oversized anyway (pre-RAM
consoles and CBFS caches).
Change-Id: I2820436776ef620bdc4481b5cd4b6957764248ea
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Joel Kitching <kitching@google.com>
CB:36385 makes dock init in ramstage fully mainboard-specific, so
keeping generating empty h8_mainboard_init_dock() for lenovo EC becomes
unnecessary and problematic.
Change-Id: I19f57f41403ffd0319cc86f21bec7e142095df83
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add support for x86_64 bootblock on qemu.
Introduce a new approach to long mode support. The previous patch set
generated page tables at runtime and placed them in heap. The new
approach places the page tables in memory mapped ROM.
Introduce a new tool called pgtblgen that creates x86 long mode compatible
page tables and writes those to a file. The file is included into the CBFS
and placed at a predefined offset.
Add assembly code to load the page tables, based on a Kconfig symbol and
enter long in bootblock.
The code can be easily ported to real hardware bootblock.
Tested on qemu q35.
Change-Id: Iec92c6cea464c97c18a0811e2e91bc22133ace42
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* Add defines for GPIO_MEM_CONFIG_0:3 in the template file, so
that code that relies on these defines can compile. Because they
are preprocessor symbols, there is no way to define them as
__weak in the baseboard header and allow the variant to override
as needed, so they need to be defined here and changed if needed.
* Add a version number for the script and an "auto-generated by"
line in the git commit message.
* Change the branch name so that it's not the same as the ones
that the other scripts will create, so that repo upload on those
CLs won't affect this one.
BUG=b:140261109
BRANCH=None
TEST=Create and build the "sushi" variant:
$ util/mainboard/google/hatch/create_coreboot_variant.sh sushi
$ util/abuild/abuild -p none -t google/hatch -x -a
Prior to this CL, you would get an error message that SPD_SOURCES is
not set. If you fixed that, then you would get failures for
GPIO_MEM_CONFIG_0, _1, _2, and _3 not defined, and/or gpio_table[]
and early_gpio_table[] not defined. After the CL, the build proceeds.
Change-Id: I0f48d6bb9544cad6d419d3a6fbb17f57200938b2
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36408
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To get a better idea what this code does, this patch adds
a new method called 'print_system_info'.
Change-Id: I16f1c9cdc402b1a816fac65d1490432e39c07baf
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36315
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
New changes in the latest binutils 2.32 lead to assembler errors causes
ipxe build failure. IPXE uses the divide test which requires /dev/null as
input as well as the output file name.
This patch facilitates the /dev/null as an exception to the current
changes in binutils package while building crossgcc for coreboot leads to
successful build of ipxe and further tests to pass based on /dev/null and
applies automatically during the crossgcc rebuild.
Also, this can be reverted once binutils/ipxe provides an updated release
in this respect.
Fixes: https://ticket.coreboot.org/issues/204
Change-Id: I9f664829b8c42420c0b2ab1f2316150f86ac0b1a
Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35098
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adds the MSR table for server family 6 model 85 (5065x) processors (Sky
Lake, Cascade Lake, Cooper Lake).
The cores number for these processors exceeds the limit of 8 cores
(it is hardcoded in cpu.c). For this reason, the patch also adds code
that determines the number of processor cores at run time.
These changes are in accordance with the documentation:
[*] pages: 2-265 ... 2-286, 2-297 ... 2-308.
Intel(R) 64 and IA-32 Architectures, Software Developer’s Manual,
Volume 4: Model-Specific Registers. May 2019.
Order Number: 335592-070US
Change-Id: I27a4f5c38a7317bc3e0ead4349dccfef1338a7f2
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <anpetrov@fb.com>
Increase the number of potential APCB images to 5 by adding to the
amd_bios_table. New instance IDs are from 0 to 4. The backup APCB
block (type 0x68) still supports only instance ID 0.
Change-Id: Ib70dc6417fecf94549a0c7df36ea42f63331be26
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
* Mark files in CBFS as IBB (Initial BootBlock)
* Will be used to identify the IBB by any TEE
Change-Id: Idb4857c894b9ee1edc464c0a1216cdda29937bbd
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Previously if .xcompile was missing, abuild would silently ignore the
error. With https://review.coreboot.org/c/coreboot/+/34241 we now check
the return code so abuild started failing.
We should generate the .xcompile if it doesn't exist. The Makefile will
handle that so we include it as the first Makefile.
We then need to override the default target so we don't use the one from
the Makefile.
BUG=b:112267918
TEST=ran abuild and made sure it generated a .xcompile in the root.
Change-Id: I79ded36d47b0219d0b126adff80a57be1c2bdf07
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
When `mode_validate` was added, a second copy of `mode_layout` was
accidentally added to the multiple-mode-argument check instead. This
prevents `-f` from working. Fix the check to reference the correct
variable.
Change-Id: Ibac6f090550ff63ec9158355b0450da204a300a7
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
According to the documentation [1], IA32_PLATFORM_ID MSR register
address should be 17H.
[1] Table 2-2. Intel (R) 64 and IA-32 Architectures Software Developer’s
Manual. Volume 4: Model-Specific Registers. May 2019.
Order Number: 335592-070US
Change-Id: I9a16b162db51d21c7849b3c08c987ab341845b1e
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Let `sconfig` output a C header file with the symbol names that we
generate since 5e2a2cd5e7 (util/sconfig: Expose usable PCI and PNP
device names).
We add another command line argument for the path to the header
file. As the file is similar in nature to our `config.h` we simply
put it in $(obj)/ too.
Change-Id: I8f87288c82f2844b61eba6534797a42b978b47bb
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add an option to ifdtool which validates that the flash regions defined
in the descriptor match the coresponding areas in the FMAP.
BUG=chromium:992215
TEST=Ran 'ifdtool -t' with a good bios image and verify no issues
run 'ifdtool -t' with a bad bios image and verify expected issues
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: Idebf105dee1b8f829d54bd65c82867af7aa4aded
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This tool downloads, caches and analyzes commits pushed to gerrit
for a specified range of commits. Currently it only works over SSH.
Data that is printed about the range of commits:
CSV Data about each individual commit:
- Commit ID
- Commit Date
- Author
- Commiter
- Submitter
- Lines added
- Lines removed
- Title
- Reviewers
It then prints the analysis it did on the data:
- Total Commits
- Total lines added
- Total lines removed
- Total difference
- Authors - Number of commits
- Total Authors
- Authors - Lines added
- Authors - Lines removed
- Reviewers - Number of patches reviewed
- Submitters - Number of patches submitted
The script relies on a number of perl modules
which must be installed separately.
Change-Id: I74896a97b5fe370c0b08562ac85d29435e438a31
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/14225
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Ubuntu 19.04 will fail looking for aclocal-1.15 if the scripts
are not regenerated because 19.04 ships with 1.16.
There are not enough eyes to roll when working with GNU autotools.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I4aa9f520499930ffc984ab0b0144c9c6b2e544a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Bring this over from the HEADS repo.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I36dc9860f4c4a2675fd3fa24fa3e534215ceb43e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The CRC result is treated as a signed value, and so in certain
situations, the calculated value for the last four digits will not
be correct. Ensure that the CRC is treated as an unsigned 32-bit
value prior to converting the last 4 decimal digits to a string.
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: I92f9ce1ceb7450f90b89c94e0ace6f79a9419b42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35604
Reviewed-by: Andrew McRae <amcrae@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When creating a new variant, adding a bug parameter after the name
of the variant will populate the BUG= field in the commit message.
If the parameter is not present, then BUG=None.
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: I3e08df5d80a5684c9f3675e3c0a8346240171cd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrew McRae <amcrae@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* Use all caps for variables.
* Use a single exit code for failures.
* No need to popd before exiting the script.
* Do ${var,,} and ${var^^} into variables instead of using it everywhere.
* Add more punctuation in comments.
* Specify LC_ALL=C so that upper/lower case show the desired behavior.
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: I63aa0aa633f36b9543e809fc42fac955da5960a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrew McRae <amcrae@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
The HWID in vboot GBB is an identifier for machine model. On Chrome OS,
that should be provisioned in manufacturing process (by collecting real
hardware information), and will be checked in system startup.
For bring up developers, they usually prefer to generate a test-only
string for HWID. However that format was not well documented and cause
problems. Further more, most Chromebooks are using HWID v3+ today while
the test-only HWID is usually v2. Non-Chrome OS developers may also
prefer their own format.
To simplify development process, the GBB_CONFIG now defaults to empty
string, and will be replaced by a board-specific test-only v2 HWID
automatically. Developers can still override that in mainboard Kconfig
if they prefer v3 or other arbitrary format.
BUG=b:140067412
TEST=Built 'kukui' successfully. Removed kukui GBB config and built
again, still seeing correct test HWID.
Change-Id: I0cda17a374641589291ec8dfb1d66c553f7cbf35
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The description.md and README.md was explicitly made for downloading or
extracting some resources, but we need to add more Chrome OS related
scripts soon; so the description should be revised.
Also changed README.md for better markdown style, for example
- Use #, ## to replace the old '-' headers
- Use code format for file names
- Use code block for example of shell execution
Change-Id: Icc3677fa318b03f4aee1b0f5fb13b2095f2afe64
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Based on the SCH5627 datasheet which is similiar
SCH5545 id 0xc4, SCH5627 id 0xc6.
Change-Id: I81f3f68690d2000a4fa8a1e703c01f54ebbce953
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/20237
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The script had a couple of bugs:
* It didn't create the required directory under variants/
* It was treating the wildcard as literal and so couldn't
find variant files to copy.
V.2: Drop verbose cp && fixup wild card usage.
Change-Id: Ie6f4179014b79ea45d0fcf406ca192046438dbf7
Signed-off-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrew McRae <amcrae@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Now that SOC_INTEL_COMETLAKE is selected by default in Kconfig,
utility to create a new variant does not need to do that anymore in
Kconfig.name
Change-Id: If68bcf14e2e0812d4f4dcb99371c65790154ff62
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Andrew McRae <amcrae@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
The current clang-format configuration is completely broken. It forces
one to change the code style of patches before pushing them, only to
find out that checkpatch now complains about it. This means newcomers
get scared away, and developers only get angered and frustrated about
it, and end up working around clang-format's requirements anyway.
For now, make clang-format's complaints non-fatal, reducing them to text
noise. However, since clang-format is currently unusable, reverting it
out would be preferred.
Change-Id: Iffa8934efa1c27c04e10545f66d8f9976e74c367
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
To create a new variant of the hatch baseboard, we need to
add the variant's GBB_HWID and other information to Kconfig
and Kconfig.name, and set up a skeletal build based on the
hatch baseboard.
BUG=b:140261109
BRANCH=none
TEST=``./create_coreboot_variant.sh sushi && git show``
Kconfig will have three new lines for the SUSHI variant, and
Kconfig.name will have an entirely new section.
New files created are:
variants/sushi/Makefile.inc
variants/sushi/overridetree.cb
variants/sushi/include/ec.h
variants/sushi/include/gpio.h
variants/sushi/include/variant/acpi/dptf.asl
Also run the script with an existing board name to verify that you
can't create a variant that already exists.
Change-Id: I1a5b9c8735faafebb2e4e384cb3346867d64c556
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add the 8086:041e integrated graphics controller.
Adding the definition makes the Intel HD 4400 graphics
recognized by inteltool.
It is found on the ark page of e.g. the Intel i3-4130 CPU.
Change-Id: I6d6b2eaa7cc5aa3912592ed3fcb73751b224eede
Signed-off-by: Christoph Pomaska <sellerie@aufmachen.jetzt>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34588
Reviewed-by: Mimoja <coreboot@mimoja.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
futility is built for the host. However, when cross-compiling,
the target's pkg-config is called to get the library paths which
can add paths from the cross-compilation tree instead of host.
e.g. /build/elm/usr/bin/pkg-config gets called instead of /usr/bin/pkg-config
. /build/elm/usr/bin/pkg-config adds the paths specific to the
cross-compilation target e.g. /build/elm/usr/lib instead of /usr/lib.
This causes linker to complain that files in library paths do not
match the architecture. BFD produces a warning while LLD errors out.
Fix this by passing PKG_CONFIG from host when building futility.
BUG=chromium:999217
TEST=coreboot builds
BRANCH=None
Cq-Depend: chromium:1778519
Change-Id: Id3afbf25001cf3daa72f36a290c93136cf9f162d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35316
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These devices can be accessed directly by symbolname,
without a search and walk through the tree, as they
have static paths.
Change-Id: I711058f5c809fa9bc7ea4333aaebad6847ebdfd4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31933
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This removes the need for COREBOOT_BUILD_DIR in Kconfig. Since the
original files will be replaced with the tmp file, the parent directory
already needs to be writable.
Before this change, the tmp files would be created in the CWD (src) if
COREBOOT_BUILD_DIR was not specified.
BUG=b:112267918
TEST=emerge-grunt coreboot and verified no tmp files were created in the
src directory.
Change-Id: Icdaf2ff3dd1ec98813b75ef55b96e38e1ca19ec7
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34244
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If KCONFIG_CONFIG is set to a full path, we should generate the tmp file
in the same directory instead of the current working directory.
BUG=b:112267918
TEST=emerge-grunt coreboot and verified with print statements that the
correct path was used.
Change-Id: Ia21e930a9b0a693f851c34bcde26b34886cbe902
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
I'm moving the .xcompile file into the $(obj) directory so we can leave
the source pristine. We need to pass the location of .xcompile into
genbuild_h.sh.
BUG=b:112267918
TEST=Ran genbuild_h with and without an .xcompile and verified it was
passed.
Change-Id: I8b3a75b478fad92a0b09246f0a00b0580f8c4aef
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This reduces disk usage during builds by removing all object files and
other intermediate files directly after a build instead of waiting for
the entire build to pass.
Change-Id: Ic2feecd58658e8bac8c6e7a851737784e35b83ef
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35112
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This option removes everything in the build tree but coreboot.rom,
config.build, config.h and make.log - a useful subset of the tree for
further testing.
Change-Id: I27e559d8d7dc90d8fe5c4ed8e25249e202e5da36
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35136
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Keep for every board: coreboot.rom, config.h, config.build
That way these can be used in follow-up jobs.
Change-Id: I5ca5cb84ab1bcffbc92a972980cd0769ebf02462
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Port_List is an array of 8 elements, and GCC 9 is warning that there
are no 'others' when all 8 elements are explicitly initialized, which is
causing the build to fail. Remove the 'others => Disabled' clause to
silence this.
Change-Id: Id082e7a76641438f3fb4c4d976dbd254a7053473
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34918
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This brings in 4 new commits from the upstream repository.
65a6d94 Free image buffer on read error
9de64c7 Fix various abort(), crashes, and memory errors
7c9db58 Bump to version 1.8
3b3c3cc Use C99 uintXX_t instead of implementation-specific u_intXX_t types
Change-Id: If949309a7481537de6529c205fe745d5509906a9
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This variable is overwritten on one branch of the next if statement, and
the other branch returns, so this assignment does nothing.
Change-Id: I63737929d47c882bbcf637182bc8bf73c19daa9f
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: scan-build 8.0.0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This change adds the following improvements:
* Easier to read.
* Checks to see if .xcompile is complete.
* Checks the make return code. This will catch if .xcompile is missing.
BUG=b:112267918
TEST=Modified my .xcompile and ran abuild and verified that
missing_arches got set correctly. Also deleted .xcompile and verified
there was a failure.
Change-Id: I7604d431f398fc0c80a857a0c7c21e164004cc99
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
FreeBSD doesn't have ENODATA defined, so the cbootimage utility wouldn't
build. It looks like the BSDs use ENOATTR in the same fashion, so
update the error to use that.
Change-Id: Ic70710d5726476755585fd1a3ae3f256a430e8df
Signed-off-by: Martin Roth <martinr@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/28365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The abuild script will `cd` into the build directory. FAILED_BOARDS
defaults to a relative path, so it ends up trying to echo into a
directory that doesn't exist.
If we set the realpath to the file then we can correctly update the
failed/passed boards file.
BUG=none
TEST=make what-jenkins-does and verified there was a failed_boards and
passed_boards in coreboot-builds.
Change-Id: Ib3af003b090668380a9425583a9f4367023820a6
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
It's better to format lists with bullet points.
Change-Id: I503ef2dea9146d67c220236b8a5b64c2ba2d794f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34504
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change the fletcher32 checksum calculation to match PSP and AGESA
implementations.
The symptom of the failure has only been noted in Picasso's BIOS
Directory Table, when a BIOS binary image of different sizes were
passed to amdfwtool. The PSP halts the boot process with the bad
BDT checksum, and if allowed to continue, AGESA asserts later due
to a failed BDT verification.
This version has been verified to produce the same result as found
at https://en.wikipedia.org/wiki/Fletcher%27s_checksum.
TEST=Build apu2, bettong, grunt and verify before/after amdfw.rom
is unchanged.
Change-Id: I2ba2c49a70aa81c15acaab0be6b4c95e7891234f
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
We recently added the --asserts option to set asserts as fatal in abuild
but didn't add the flag to getopts, so it gets rejected as an invalid
argument.
Change-Id: Ic70e9a2bec039955cf62c175875598773ade2d3d
Signed-off-by: Martin Roth <martinr@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
JENKINS_ABUILD_OPT is passed in abuild's command line
Change-Id: I5e7fbb77a3c6592a4414a6c1e3f7556c7e3a824c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
This enables fatal asserts, which can be useful to get better
diagnostics by the build tools (both compilers and static analysis.)
Change-Id: I1e1653f465fe1f545878d6eec83b8645dc17d9cb
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
The abuild command line can vary a lot depending on options and the line
became unwieldy (plus, it's on two lines because we run abuild twice),
so factor it out into a variable.
Change-Id: I102756fb95c93f542d534610bf9737a13ac1ad62
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
It can be useful to pass along to external projects, e.g. payloads.
Change-Id: I61c7bb162e2737a562cbef08b32ebbafd9cf1cb0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tianocore payload uses nasm. Supply it in the coreboot toolchain
instead of relying on system version.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I086cbe6c46f7c09b2a7a83e177b32fd1bdf99266
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33024
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-W is the old name for -Wextra, so let's rename it to be consistent with
the rest of the utility Makefiles.
Change-Id: I0e50f13d2617b785d343707fc895516574164562
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
The processor P_BLK doesn't support throttling. This behaviour could be
emulated with SMM, but instead just update the FADT to indicate no support
for legacy I/O based throttling using P_CNT.
We have _PTC defined in SSDT, which should be used in favour of P_CNT by
ACPI aware OS, so this change has no effect on modern OS.
Drop all occurences of p_cnt_throttling_supported and update autoport
to not generate it any more.
Change-Id: Iaf82518d5114d6de7cef01dca2d3087eea8ff927
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Only needed in ramstage, and only for MP tables.
Change-Id: Ia7c1e153b948aeefa4c3bea4920b02a91a417096
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33922
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
512 bytes is much too big for this buffer, which only needs to hold a
path that will have a length of at most 20. The large buffer size also
triggers a -Wformat-truncation warning with GCC since it is later
printed into the smaller temp_string array, so shrink it down to
something reasonable.
Change-Id: I6a136d1a739c782b368d5035db9bc25cf5b9599b
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
For AMD's Family17h processors, verstage needs to be run in the PSP,
before memory is initialized. This adds that binary into the PSP
directory.
See the Family17h documentation in the coreboot documentation directory
for more information.
BUG=b:137338769
TEST=Build, add test binary to mandolin board, boot
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I29002a1af51c59a2e6c715e15f3dc63e59cd5729
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
- Correct command line argument for microcode patches from -u to -O
- Add #if PSP_COMBO around new_combo_dir() as it's only called when
that's enabled.
- Remove unused variable in integrate_bios_firmwares()
- Correct enum type from amd_fw_type to amd_bios_type in
register_fw_addr()
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I51c6dbe700505bc2e32443000ae55cb644051e42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The JUnit output from the libpayload builds was getting deleted by the
coreinfo build. Move the libpayload to later in the coreboot-gerrit
job.
Also add messages to stdout indicating the various libpayload configs
that are built and a message indicating when all libpayload builds are
complete.
BUG=b:137380189
TEST=Upload test commit that includes a libpayload compile error and
verify buildbot fails.
Change-Id: I43b55f402216582dcf81be34171437be345572ab
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34183
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In patch e29a6ac16a (util/sconfig: Add
commonlib/helpers.h) helpers.h has been added to the include-list.
In headers.h we have a definition for __unused:
On a host system environment where glibc-headers-2.12-1.212 is
installed, a file included by <sys/stat.h> called bits/stat.h have the
following content on line 105 and onwards:
long int __unused[3];
where the mentioned part is part of the structure called struct stat.
If we include commonlib/helpers.h _before_ <sys/stat.h>, the symbol for
__unused will be defined by the preprocessor to be
'__attribute__((unused))', therefore the above mentioned structure member
will be expanded by the preprocessor to be
'long int __attribute__((unused))[3];', which is not a valid C syntax
and therefore produces a compile error for sconfig tool.
To handle this case we need to make sure commonlib/helpers.h is included
_after_ <sys/stat.h>. As the needed part of stat.h (which is
struct stat) is only used in main.c it is safe to move the include from
sconfig.h directly into main.c while taking care of the order.
Change-Id: I9e6960a318d3dd999e1e9c1df326d67094f3b5ce
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The right specifier for printing ptrdiff_t is %td.
Change-Id: I7bae4d47f15cfe85ca870f687c6f702339f680bb
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 14021{64,68,76}
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
With DEVTREE_EARLY we could create incomplete device
objects with topology links removed to reduce footprint
for bootblock.
Declare everything with 'static __unused DEVTREE_CONST'
to avoid compiler errors and to not expose unusable
device object names to global scope.
Change-Id: Ie4cb9e75f179f44edf4f8256ad8320bc2d4ae71a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
GNAT had a constant initialized at runtime which led to trouble
with compilers that decided to place it into an actual constant
section (e.g. GCC 9). Usually, this would be handled gracefully
if the Ada compiler knew about the runtime initialization. How-
ever, as the initialization was done by taking the address of
the variable, the compiler had no clue.
Change-Id: I73ce4cadc612c814ed2e22b44f429af2ad3db288
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34147
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for AST2400 Super I/O.
The device doesn't have an ID register, so probe for scratch register
not to read as 0xff.
Tested on platform which has an AST2400.
Change-Id: I86af69c6b2ccefe2c88eef875bc858239df834f1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Considering the following integer multiplication:
u64 = u16 * u16
What on earth, one might wonder, is the problem with this? Well, due to
C's unfortunately abstruse integer semantics, both u16's are implicitly
converted to int before the multiplication, which cannot hold
all possible values of a u16 * u16. Even worse, after overflow the
intermediate result will be a negative number, which during the
conversion to a u64 will be sign-extended to a huge integer. Not good.
The solution is to manually cast one of the u16 to a u32 or u64, which
are large enough to not have any overflow and will prevent the implicit
conversion. The type of the u64 is preferred, though a u32 is used
instead of size_t, since that can change depending on the platform.
Change-Id: I5391221d46d620d0e5bd629e2f9680be7a53342e
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 12297{03,04,05,06,07,08,09,10}
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This function is only used in this file, so it can be made static.
Change-Id: I90e673da91eb926424d1730c268860da7fa1627b
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
The prototype for is_ident() is in this header, so include it.
Change-Id: I45e0d58d1b891b18b3eb7741897ab691188a2bd9
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
None of these functions are used outside of the files they are defined
in, so they can all be static.
Change-Id: Ie00fef5a5ba2779e0ff45640cff5cc9f1d096dc1
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Add a utility to generate a compressed BIOS image for AMD Family 17h.
If the input is an elf file, the utility extracts the program portion
for compression. Otherwise the file is compressed as-is.
In modern AMD systems, the PSP brings up DRAM then uncompresses the
BIOS image into memory prior to x86 beginning execution. The PSP
supports a zlib engine, and interprets the first 256 bytes as a
header, where offset 0x14 containing the uncompressed size. For
further details, see AMD Platform Security Processor BIOS Architecture
Design Guide for AMD Family 17h Processors (NDA only, #55758).
BUG=b:127766506
TEST=Use with WIP Picasso
Change-Id: Id1c54e0a6dae9e4a0362c6635fe8b8aa48a369d8
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
The flag is useful for updaters to determine which areas to leave
alone, such as VPD (vital product data) regions that are set in
factory and might contain unique (MAC addresses) or hard to obtain
(calibration output) data.
It's also useful to see which regions are marked as such.
Change-Id: Ic0a229d474b32ac156cfabc917714ce9d339bac6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
These functions are only used in cbmem, so they can be made static.
Change-Id: I21f7d7c21064a8ae951e6d96b28c2ddcf52c0006
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Make sure that the type of the loop index matches the type of the upper
bound. This fixes several -Wsign-compare warnings.
Change-Id: Iaa94ce93bc35d523bc782ad914bfd283606becac
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
It's not perfect and we'll need to find a better place for that,
but I'll look into that as part of the big board-status rework.
Change-Id: I2ae50c58e3796563e0b2370105abc82b7e2e042a
Signed-off-by: Patrick Georgi <patrick@georgi.software>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Banner string format has been changed (CB:30935). We should update our
regular expression correspondingly.
Also add "verstage" into the stage search list since some boards (e.g.,
Kukui) might start console initialization at verstage.
Change-Id: I16eba3ac5e203e80b0bfd42a4294401dbccd4463
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
These functions are only used in ifdtool, so they can be made static.
Change-Id: Ia48bfecb89a7445dbd0f140acb5ac0592da2ebe7
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Fix error "Invalid option -A" by adding "A" to options list.
Also, atoi does not parse hex string, for instance 0x200 is interpreted as 0,
and this causes a failure when updating second FIT table using -j option.
Use strtol instead of atoi
BUG=none
BRANCH=none
TEST=Build and boot hatch after enabling dual bootblock feature.
Change-Id: Ib227437f88ffcccda1ce2f20a9ab098e5aa091c7
Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This is causing coreboot build in Chromium OS to fail.
BUG=None
TEST=emerge-eve coreboot
BRANCH=none
Change-Id: I4faa140b3046651b4ed0a9aeefe437048c6ef0da
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The ifittool is used instead. Drop old code.
Change-Id: I70fec5fef9ffd1ba3049badb398783f31aefb02f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Add the IntelFirmwareInterfaceTable-tool to modify the FIT.
As cbfstool is overloaded with arguments, introduce a new tool
to only modify FIT, which brings it's own command line syntax.
Provide clean interface to:
* Clear FIT
* Add entry to CBFS file
* Add entry to REGION
* Delete entries
* Add support for types other than 1
* Add support to dump current table
* Add support for top-swap
* Sort entries by type
Most code is reused from existing cbfstool and functionality of cbfstool
is kept. It will be removed once the make system uses only ifittool.
Based on "Intel Trusted Execution Technology (Intel TXT) LAB Handout"
and https://github.com/slimbootloader/slimbootloader .
Change-Id: I0fe8cd70611d58823aca1147d5b830722ed72bd5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Set up generic decode ranges based on the devicetree settings.
Change-Id: Ie59b8272c69231d6dffccee30b4d3c84a7e83e8f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Clang doesn't know `-Wlogical-op`, so let's move it into xcompile where
we can easily distinguish between the two. However, this requires us to
split out `GCC_ADAFLAGS*` from `GCC_CFLAGS*`.
Change-Id: I6a50de0bc5372f61337f237383d32645ba86b0fd
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33579
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add arguments for additional PSP blobs needed with Family 17h support,
including the new AGESA binary loaders.
Create a new type of structure and entry for a BIOS directory table,
containing PMU code, microcode updates, as well as the BIOS initial
code.
Details on each of these items may be found in the AMD Platform Security
Processor BIOS Architecture Design Guide for AMD Family 17h Processors
(NDA only, #55758).
BUG=b:126593573
TEST=Used with WIP Picasso
Change-Id: I4899dedb6f5e29a27ff53787a566d5b8633a8ad5
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
As CFLAGS_GCC and CFLAGS_CLANG are still the same at this point, this
just removes some duplicate flags.
Change-Id: I532e5fa146891b70e4c1949c614b280055524593
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
coreboot has decided to go with 96 characters per line.
Original Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original Reviewed-on: https://review.coreboot.org/c/coreboot/+/31651
Change-Id: I9c99e5cca6548e23cf755dc37193ff2aa669ac10
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Add the ability to generate two PSP directory table levels. The PSP
is capable of supporting two levels, with the primary intended to
remain pristine for the life of the system, and the second updatable.
In the event the second becomes corrupted, the primary is still
sufficient to allow a recovery of the other.
This patch modifies no directory table structures currently in use.
The soc or southbridge must pass an argument to force building the
secondary table.
BUG=b:126593573
TEST=Used with WIP Picasso
Change-Id: Id321f5142e461d4a7f3343c0835a09a1a1128728
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Align the PSP's NVRAM item since it's intended to be updateable
in the flash device.
Change-Id: I6b28525624b95b411cc82de0cbe430ea7871149d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Allow the soc build to pass a soft fuse value to the utility. This
helps maintain compatibility across PSP generations.
Add a generic 'other' item to the amd_fw_entry structure that may
be used by non-fuse entries in the future.
TEST=Verify google/grunt amdfw.rom unchanged before and after.
Compare internal board using override before and after.
Change-Id: I26223f0b42ad28c43d9bd87419a2a8f719ee91cb
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Instead of assuming GbE/PDR/EC regions may exist or not, check if there
is a valid region defined in the descriptor and set the region access
permissions based on that.
The net effect change is to enable the use of the PDR region on the
sarien platform, which also uses the GbE and EC regions.
This results in the following example changes:
mb/google/sarien (GbE, PDR, EC)
. DESC BIOS ME GbE PDR EC
-BIOS r rw rw r
-------------------------------
+BIOS r rw rw rw r
mb/google/eve: (no GbE, no PDR, no EC)
. DESC BIOS ME GbE PDR EC
-BIOS r rw rw r
-ME r rw r
-GbE r rw
-EC r rw
-------------------------------
+BIOS r rw
+ME r rw
+GbE
+EC
BUG=b:134703987
Change-Id: I7aeffc8f8194638c6012340b43aea8f8460d268a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33273
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As long as we keep the IS_ENABLED() definition in libpayload for
compatibility, we should check that IS_ENABLED() usage doesn't
sneak back in.
Also remove all other IS_ENABLED() checks.
Change-Id: Id30ffa0089cec6c24fc3dbbb10a1be35f63b3d89
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add T32 scripts that allow debug of any coreboot stage
on qcs405.
Change-Id: I4e792a2806e5ebd3b4075c7bb69c43587920deae
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29951
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix the following error from clang invoking gcc linker with wrong arg:
i386-elf-gcc: error: unrecognized command line option '--rtlib=libgcc';
did you mean '-static-libgcc'?
clang-4.0: error: linker (via gcc) command failed with exit code 1
Just remove --rtlib switch from CFLAGS relating to clang
Change-Id: Ife7ef6b6b47a04598fc67b40751bc59eed93b4af
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/21354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
inteltool can't detect whether address mapping is normal or
mirrored, which in turn may be cause RAM initialization to
fail when using spd.bin generated by inteltool.
Mention this in readme as it may help someone.
Change-Id: I8d24e4d9332bdcf484987581dd6941e2bf9c4f87
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
For x64 and x86_32 configurations, apply the -march flag to both GCC and
Clang flags.
This solves the problem of Clang-compiled coreboot failing due to Clang
emitting SSE instructions for code that is executed while SSE is not
enabled.
This patch takes functionality targeted for GCC configurations and moves
it down a few lines, modifying CFLAGS instead of GCC_CFLAGS in order
that it applies to both GCC and Clang.
This is an alternate patch to CB:32887.
Signed-off-by: Alan Green <avg@google.com>
Change-Id: I6a6a6136b01a64d46f730ed19ebbeaadaf2183df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
It is possible that 'lnode->val' is set to 0 on a previous iteration of
the loop, so check that it is non-null here before dereferencing it.
Change-Id: I9827dd5623eaf11240df605a8b50ff9e27a5fce0
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1129149
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The 'new_type' function already allocates memory, so it is only
necessary to clone the existing type if this function is not called.
Change-Id: I47065204c5f4b6bab022bd7ccf19838c3ce1f86e
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity Scan CID 1129106
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
It is possible that 'filename' is still null in this if statement,
so we add an extra check to prevent a null dereference in strcmp.
Change-Id: Iaba95b63a4d552051e0c56445522de7274dfd0b3
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1395330
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
In each of these cases it is possible that 'member' is NULL at the
beginning, which will skip the earlier while loops entirely and cause
a NULL dereference later on. Add extra error checks to prevent this.
Change-Id: Ib5873c0830b71397ef661976d387fc6ce33c5cd1
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1129147, 1129152, 1129153, 1129154
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
SMBus adapter will not appear if i2c-i801 module is not loaded.
Added it to the readme.
Change-Id: I3de0e02f13178d78b8cc02a74a745ad66e929070
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
When using -Werror=old-style-declaration, gcc reports an error:
"'static' is not at beginning of declaration"
Tested on 945G-M4 board.
Change-Id: I7216a4fab2d5878066c871166e6a481d1f201a9d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
If 'class > LAST_REGC', then there will be an out-of-bounds read when
accessing 'regcm_bound'. Prevent this by skipping to the next iteration
of the loop. Note that this should not generally happen anyway, since
'result' represents a bitset for the indices of 'regcm_bound', and so
iterations where 'class > LAST_REGC' should already be skipped by the
previous continue statement (since those bits of 'result' should all be
zero).
Found-by: Covericy CID 1129122
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Id5f5adb0a292763251054aeecf2a5b87a11297b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The corner case of an empty string literal was causing romcc to
segfault. This checks if the literal is empty, and if so allocates a
size one buffer for the terminating null character. A test case for
this is added to ensure it doesn't happen again.
Found-by: Coverity CID 1129099
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I067160a3b9998184f44e4878ef6269f372fe68bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Free 'arg_type' after it is used to prevent a memory leak.
Found-by: Coverity Scan CID 1129114
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I5e8661547bb7623463ed23fc45269049ffb8c50e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
'used_indices' is 64 bits wide, so use a fixed-width type to make
that clear. As such, 'index' can have a value of up to 63, so use a
64 bit integer when doing the shifts to prevent overflow.
Found-by: Coverity Scan CID 1287090
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Ibd089df6be60c8ea46da11e5e83cd58b2e2c54d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32854
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It appears that the rebase.sh script was renamed to
cross-repo-cherrypick and changed directories. Update comments to
reflect that change.
Change-Id: I863df48378feb48c9b195b1778dcaf1972a4f105
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Signed-off-by: Alex James <theracermaster@gmail.com>
Change-Id: I688cb60c98370bf74aa8554bab43594ff84c4e24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
At least one channel must be present, so print an error if there is
not. However, we cannot always assume it will be the first channel,
so make the appropriate selection when printing the timings.
Found-by: Coverity Scan #1370{584,585,588,589,590-596,600}
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I6b59989242e498474782876302e0850e3e4cf2d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
'name' and 'env' are supposed to be file system paths,
but could overflow the buffer if configured incorrectly.
Let's avoid that entirely.
Found-by: Coverity Scan #1362515
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I1aef36819d49ebcbde1c51995dc0961c85e74150
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
It is possible that 'malloc_fo_sub' and 'remalloc_fo' can
fail, so add appropriate error checks for those cases.
This incidentally fixes a possible memory leak when
'malloc_fo_sub' succeeds but 'remalloc_fo' does not.
Found-by: Coverity Scan #1396050
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I944b67f5cdcfd7a687e81d8bb01a209c9dc9b0b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
As the previous comment indicated, this null check is
currently superfluous, but adding it in makes Coverity
happy, and future-proofs the code in case someone changes
the internals of 'find_fcba' later and forgets/doesn't know
to update this error check.
Found-by: Coverity Scan #1395066
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I594cd0098f5b36cef5b3efc4c904710d3ba9b815
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
We keep the support, though. Just now that `libgfxinit` is fixed, we
don't need the distinction anymore. Causally, we also don't need
CPU_INTEL_MODEL_306AX any more.
TEST=Played tint on kontron/ktqm77. Score 606
Change-Id: Id1e33c77f44a66baacba375cbb2aeb71effb7b76
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Should include vb2_sha.h header when SHA library functions or
constants are required. This replaces NEED_VB2_SHA_LIBRARY.
BUG=b:124141368, chromium:956474
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: I9f32174dbf3de05fbe5279cb8017888757abf368
Signed-off-by: Joel Kitching <kitching@google.com>
Cq-Depend: chromium:1583820
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add the new field 'smbios_slot_desc', which takes 2 to 4 arguments.
The field is valid for PCI devices and only compiled if SMBIOS table
generation is enabled.
smbios_slot_desc arguments:
1. slot type
2. slot lenth
3. slot designation (optional)
4. slot data width (optional)
Example:
device pci 1c.1 on
smbios_slot_desc "21" "3" "MINI-PCI-FULL" "8"
end # PCIe Port #2 Integrated Wireless LAN
Tested on Lenovo T520.
Change-Id: If95aae3c322d3da47637613b9a872ba1f7af9080
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Sunrise Point-LP is used on Skylake and KabyLake platforms,
but the PCH IDs differ.
This commit adds the PCH IDs for Skylake mobile platforms
and renames the Kabylake macros to distinguish them.
Used Intel documents:
- 332995-001EN (I/O datasheet vol. 1)
- 332996-002EN (I/O datasheet vol. 2)
Change-Id: Id46224fcc44b06c91cbcd6c74a55c95e1de65ec6
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
TEST=build & run
Change-Id: I222a56f1c9b74856a1e1ff8132bab5e041672c5d
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25207
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If override tree does not have any device, then the chip info
structure in it cannot be associated with the correct device and ends
up being added as a standalone chip info structure without any device
actually using it. This change prevents this condition by throwing an
error during compilation.
BUG=b:130342895
Change-Id: I7b8bb6b3228030a465976ca32ce8ef63f41365dd
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The last attribute was never returned.
Fix size compare to retrieve all attributes.
Manually tested and seen all attributes, including the last one.
Change-Id: I08df073158a0f285f96048c92aa8066fa4f57e6f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Support for ACPI specification version 6.3:
Add PCC operation region support for the AML interpreter. This adds PCC
operation region support in the AML interpreter and a default handler for
acpiexec. The change also renames the PCC region address space keyword to
PlatformCommChannel.
Support for new predefined methods _NBS, _NCH, _NIC, _NIH, and _NIG.
These methods provide OSPM with health information and device boot
status.
PDTT: Add TriggerOrder to the PCC Identifier structure. The field value
defines if the trigger needs to be invoked by OSPM before or at the end
of kernel crash dump processing/handling operation.
SRAT: Add Generic Affinity Structure subtable. This subtable in the SRAT
is used for describing devices such as heterogeneous processors,
accelerators, GPUs, and IO devices with integrated compute or DMA
engines.
MADT: Add support for statistical profiling in GICC. Statistical
profiling extension (SPE) is an architecture-specific feature for ARM.
MADT: Add online capable flag. If this bit is set, system hardware
supports enabling this processor during OS runtime.
New Error Disconnect Recover Notification value. There are a number of
scenarios where system Firmware in collaboration with hardware may
disconnect one or more devices from the rest of the system for purposes
of error containment. Firmware can use this new notification value to
alert OSPM of such a removal.
PPTT: New additional fields in Processor Structure Flags. These flags
provide more information about processor topology.
NFIT/Disassembler: Change a field name from "Address Range" to "Region
Type".
HMAT updates: make several existing fields to be reserved as well as
rename subtable 0 to "memory proximity domain attributes".
GTDT: Add support for new GTDT Revision 3. This revision adds information
for the EL2 timer.
iASL: Update the HMAT example template for new fields.
iASL: Add support for the new revision of the GTDT (Rev 3).
More changes in this version at https://acpica.org/node/166
Change-Id: I3a825f568423c3a703ad1c13da976af322ed9de2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Release Note :
https://cmake.org/cmake/help/v3.14/release/3.14.html
"The FindFontconfig module added by 3.14.0 accidentally used uppercase
FONTCONFIG_* variable names that do not match our conventions.
3.14.1 revises the module to use Fontconfig_* variable names.
This is incompatible with 3.14.0 but since the module is new in the 3.14
series usage should not yet be widespread"
Change-Id: Ief7f5e8309597093f061789926bd3bd2ed3aec2d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
openjdk-8-jre-headless is no longer available in the debian image we're
basing the coreboot-sdk off of. Update it to 'default-jre-headless'.
Change-Id: I60f6ecbaedccc0da61f96e0bce4122406ba4bd91
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
build.h provides iasl's version but right now assumes that it's kept in
util/crossgcc/xgcc/bin. Often true, but not always, so use the one found
in .xcompile to query the version as that's the version that is used in
coreboot builds.
Change-Id: Iaeedc22e0e14fa96b4f2a68127f405c7f0c9d5cc
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Martin Roth <martinroth@google.com>
if git log --no-show-signature is not supported, retry without.
Change-Id: I9ee1f8e887cde5e4d6c5e6958f269c62572cdd53
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32299
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Both values in each array are only initialized if
`two_channels` is true, so we need to check that first.
Found-by: Coverity Scan #1370{584,585,588,589,590-596,600}
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: I592bc6ae00f834f74a61668d7a3919014ec635f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The Flashmap (FMAP) was not clearly documented. The new flashmap.md
explains where to find more details about that and how / why it was used
in coreboot. Also explained what is FMD and how to use it (based on
original README.fmaptool).
BUG=None
TEST=None (only documentation)
Change-Id: Ia389e56c632096d7c905ed221fd4f140dec382e6
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This check had very few false positives which were all easily resolved,
and it's unlikely that further false positives will become problematic
in the future. On the other hand, it does detect a very severe bug (when
you think you're using a Kconfig but you aren't due to a typo), so since
warnings are currently not very visible, let's turn this into an error
because the pros clearly outweigh the cons for that.
Change-Id: I897b5e13d3242fb77b69f0bd3585baa7476aa726
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32257
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
libssl1.0-dev is no longer available:
- Update to libssl-dev
- Add libcrypto++-dev to provide additional crypto libraries not
available in libssl-dev.
Change-Id: Ie10e14ebf7ae849301302008ee6ffeec1f40ccab
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
The patches added to `make` require that we use automake & aclocal
to rebuild the configuration, but version 1.15 of autotools is
expected. After debian sid updated to autotools 1.16, the tools can't
be located.
We'll just pretend to have version 1.15 with symbolic links. This
doesn't seem to be a good solution but gets the job done.
Change-Id: I9f616b96e728106e7adf321325caa06808e064c2
Signed-off-by: Martin Roth <martinr@coreboot.org>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/28544
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
%lx is the right format string for printing longs.
Found-by: Coverity Scan, CID 1229686, 1229687
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Ib7ab54dc039bdd60969c79f3c881d69fc68f0d2a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
When invoking 'make menuconfig' with gcc 4.9.2 an error is thrown:
ld: build/util/kconfig/lxdialog/checklist.o: undefined reference
to symbol 'acs_map'
This happens with ld version 2.24 and newer when menuconfig is
executed for the first time after make clean. This does not happen
with ld 2.20 (part of gcc 4.4.7).
It can be fixed with the flag -ltinfo in HOST_LOADLIBES.
Change-Id: I6216bb4d276d4bf98aa4ec06457b809fdcd73235
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Opens a binary file to extract DDR SPDs using known bits.
At the moment only DDR4 SPDs are supported.
Dumps the found SPDs into the current folder, as either
binary or hex encoded file.
Works with python2 and python3.
Change-Id: I26dd73d43b724ea6891bb5b6e96856c42db8577c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
This patch changes a few more Kconfig linter warnings to errors that
currently do not show up in the tree and that seem unlikely to become
false positive in the future. One instance of duplicated code that
essentially checks for the same thing was consolidated.
It also adds a new test for references to boolean Kconfig options that
do not use the CONFIG() wrapper macro. It's a little flaky (e.g. hard to
handle multi-line comments), but it should be helpful the majority of
the time as a warning in a Jenkins comment.
Change-Id: I975ee77d392ed426f76f7671d9b6ef9441656e6a
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The last part of the file has not been modified much.
Change-Id: Icc45824d5d1298146f459d75f0a5121dbdd70d41
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30969
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the values are hardcoded, we might as well hardcode values that
make sense.
Change-Id: I3ac0e2d74a42c1fe55b1cdc3e2a970ae80cc9f37
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30963
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 626ba097a2.
This change was submitted under the incorrect assumption that there was
agreement on a coding style change. There wasn't, so while the issue is
under discussion we should revert to the previous status quo.
Making clang-format honor the line length is a separate issue from
changing the line length, and can be reuploaded as a separate CL.
Change-Id: I433c82c95a897b3113cace3668cc8ce0f1ab75bf
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Values from
- Intel doc 337347 rev4
- coreboot soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h
On Coffeelake H (using Cannonlake / Cannonpoint PCH) p2sb is not
accessible. Using a static value instead. 0xfd000000 is a common value
chosen by coreboot and non-coreboot firmware.
Change-Id: Id637f703ab0a99eb0908ecdc3da27ba80db1c6b8
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
A side effect of the change 8e0dca05
"util/amdfwtool: Add generic image copy function"
was to treat a read operation of zero bytes as a failure. Some
implementations exist that use zero length files as a means of
removing functionality. This causes amdfwtool to exit with an
error.
Put the zero length capability back in, and generate the requested
table entry with a length field of 0x0.
TEST=Boot google/grunt, inspect PSP directory table
BUG=b:128507639
Change-Id: Ifc9204dbbf6b107f06116362358ab9d22caa71df
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31891
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This symbol was removed in
a6be58fece ("nb/intel/sandybridge: Remove the C native graphic init")
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Change-Id: I87801552e1c37162897949ec0db3904f850f0bfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The root port IDs on bd82x6x.go were for both the PCH and the CPU PCIe
root ports. Put the latter on sandybridge.go instead, and add missing
IDs.
Change-Id: I04b5220c460f1930accd64b63c11f512581f2c6c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30962
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch updates the Kconfig linter to support the new CONFIG() macro
in the same manner that IS_ENABLED() was previously supported. It will
be flagged when it is used on non-bool Kconfigs or used with #ifdef, and
it is supported for checking used Kconfigs. Remaining uses of
IS_ENABLED() are flagged with a deprecation warning.
Change-Id: I171ea8bc8e2d22abab7fc4d87ff4cf8aad21084f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31776
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some of the older chipsets that are known not to have ME at all
were removed for some reason, add them back in.
Also some newer chipsets/ME models were missing, add them in.
Change-Id: Iaed9a342e478a483113bf81d25042a6041fbc4ba
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Complete the removal of the fanless command line options. The only soc
using them has been converted to use the subprogram option instead.
TEST=Verify amdfw.rom is unchanged before and after the conversion
BUG=b:126691068
Change-Id: I187f17743cc98cc136b0df61caf8e95d17f98d51
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31737
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Separate the type field for the PSP directory table to better match the
AMD Platform Security Processor BIOS Architecture Guide (order #55758,
NDA only). Instead of a 32-bit type, change to an 8-bit value and an
8-bit subprogram field to allow for a more generic application across
family/model products.
This patch also eliminates the "fanless" types, previously added for
stoneyridge, and converts the --smufnfirmware and --smufnfirmware2
arguments to use a subprogram value of 1.
Subsequent patches will change the stoneyridge makefile to use the
new option, and eliminate the fanless arguments.
TEST=Boot google/grunt, confirm no difference in amdfw.rom file.
BUG=b:126691068
Change-Id: If8f33000c31cba21f286f54459de185c21e46268
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31735
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace variables and function arguments with a context that may be
maintained and passed. Add macros to clarify the pointer math. Add
functions to generate tables instead of relying on correct ordering
and math. Use defined sizes for tables instead of arbitrary additions
to an index.
TEST=Verify no difference in amdfw.rom for google/grunt before and
after, and verify a grunt build with PSP_COMBO=1 runs.
Change-Id: I7ad12fa5d615d1aa3648db40e3ea75f8cf2ed59a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Consolidate the code that opens, stats, copies, and closes the
individual files into a single function.
TEST=Verify no difference in amdfw.rom for google/grunt before
and after the patch is applied
Change-Id: I2da0dd79186ccc8c762b58cf3decb9980378a5f7
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Rename psp_fill_head() and call it with the cookie to populate the
header. The combo header and PSP directory header are similar and
should be calculated the same way.
Change-Id: I7e634542de65576addadbe683596cbe572de3dcd
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31732
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are effectively two unique sets of arguments for the utility,
causing one of two tables to be constructed. Both tables are
identical, however, and therefore the only practical difference is
the offset in the Embedded Firmware Structure which holds the pointer
to the table.
This patch is part 2 of 2 to reduce the number of command-line options
to amdfwtool. Part 1 added the --combo-capable option that helps
put the PSP directory pointer in the correct location. Part 2
removes the duplicated table, the support code, options, and updates
the usage text.
TEST=Build before/after images for grunt, bettong, apu2, and diff
hexdumps of the amdfw.rom files. Built/ran grunt with PSP_COMBO
defined as 1.
BUG=b:126691068
Change-Id: I542a7f5023137f30fbe00533452d4448117df487
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
There are effectively two unique sets of arguments for the utility,
causing one of two tables to be constructed. Both tables are
identical, however, and therefore the only practical difference is
the offset in the Embedded Firmware Structure which holds the pointer
to the table.
This patch is part 1 of 2 to reduce the number of command-line options
to amdfwtool. Create a new option that is used as an indicator for
which Embedded Firmware offset to use. Part 2 will be added once
makefiles no longer use the duplicated options.
This patch also adds two new options for fanless SMU firmware to be
used instead of the ones that will be removed in part 2.
TEST=Verify no difference in amdfw.rom for google/grunt before
and after the patch is applied
BUG=b:126691068
Change-Id: I249700c6addad1c0ecb495a406ffe7a022dd920b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The fletcher32 algorithm generates a sum over a range of 16-bit
WORDs. Change the function's interface to be more generic,
accepting a more intuitive size in BYTEs. Don't require the
caller to understand the nature of the algorithm and convert to
WORDs prior to calling.
TEST=Verify no difference in amdfw.rom for google/grunt before
and after the patch is applied
Change-Id: Iad70558347cbdb3c51bd598479ee4484219c0869
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31728
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace the use of multiples of DWORDs with structures that
describe the Embedded Firmware Table, and PSP directory
headers & entries.
TEST=Verify no difference in amdfw.rom for google/grunt build
(Family 15h Models 70h-7Fh), amd/bettong (F15h 60h-6Fh),
and pcengines/apu2 (F16h 30h-3Fh). PSP_COMBO builds but
was not verified.
Change-Id: If05952d9282a0fa5a397984eaae671fb33f6134a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Correct an oversight in the utility that attempts to match up eligible
PSP directory table entries with blob names passed on the command
line. A 1:1 matchup of items shouldn't be assumed, so the i iterator
shouldn't be used to walk both lists.
This change has no effect on google/grunt (Family 15h Models 70h-7Fh),
but eliminates blank entries of all FF's on builds of amd/bettong
(F15h 60h-6Fh) and pcengines/apu2 (F16h 30h-3Fh). Removal of entries
also affects the checksum accordingly.
TEST=Build before/after images for grunt, bettong, apu2, and diff
hexdumps of the amdfw.rom files
Change-Id: I13e359d3cc6f5ce408bbf077feec3707ee2b3838
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31726
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Until now the TCPA log wasn't working correctly.
* Refactor TCPA log code.
* Add TCPA log dump fucntion.
* Make TCPA log available in bootblock.
* Fix TCPA log formatting.
* Add x86 and Cavium memory for early log.
Change-Id: Ic93133531b84318f48940d34bded48cbae739c44
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The __pci_driver and __cpu_driver uses variable length arrays which are
constructed by the linker at build-time.
The linker always place the structs at 16-byte boundary, as per
"System V ABI". That's not a problem on x86, as the struct is exactly
16 Bytes in size. On other platforms, like x86_64 it breaks, because the
default data alignment isn't SysV compatible.
Set -malign-data=abi to make x86_64 gcc use the SysV psABI.
Fixes broken __pci_driver and __cpu_driver on x86_64.
Change-Id: I2491d47ed03dcfd8db110dfb181b2c5281449591
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30116
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on not publicly available IT8613E Preliminary Specification V0.3.
Change-Id: Iec99d4d998f645dbad9c803d6d5477580b0bccc4
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This is a great check, but unfortunately it's currently not effective
because most uses of IS_ENABLED() do not have whitespace in front of
them (they're mostly used as part of an if (IS_ENABLED(...)) condition).
This patch makes the linter a little more generous in what it considers
in scope to avoid these false negatives in the future.
Change-Id: I2296410c73cd6e918465c90db33e782936bec0f9
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31746
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When updating firmware, it is very often that we may want to preserve
few sections, for example vital product data (VPD) including serial
number, calibration data and cache. A firmware updater has to hard-code
the section names that need to be preserved and is hard to maintain.
A better approach is to specify that in FMAP area flags (the `area_flag`
field) using FMAP_AREA_PRESERVE. With this patchset, a FMD parser flag
"PRESERVE" is introduced and will be converted to FMAP_AREA_PRESERVE
when generating FMAP data (by fmap_from_fmd.c).
For example, The FMD statement:
RO_VPD(PRESERVE)@0x0 16k
will generate an FMAP firmware section that:
area_name = "RO_VPD"
area_offset = 0
area_size = 16384
area_flags = FMAP_AREA_PRESERVE
BUG=chromium:936768
TEST=make; boots on x86 "google/eve" and arm "google/kukui" devices
Manually added 'PRESERVE' to some FMD files, and verify (by running
fmap.py) the output coreboot.rom has FMAP_AREA_PRESERVE set
Change-Id: I51e7d31029b98868a1cab0d26bf04a14db01b1c0
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The recent toolchain update also updated binutils, which has a new
relocation type, introduced with commit bd7ab16b
(x86-64: Generate branch with PLT32 relocation).
Add support for R_X86_64_PLT32, which is handled as R_X86_64_PC32.
Add comment explaining the situation.
Fixes build error on x86_64.
Change-Id: I81350d2728c20ac72cc865e7ba92319858352632
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31468
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The idea of "annotation" for firmware sections was pretty flexible, but
in future we will want multiple attributes applied to same area. For
example, indicate the section must be preserved when updating firmware
so serial number or MAC address can be preserved.
The solution here is to extend annotation so it can take multiple
identifiers (flags) in a row. For example, to declare a 64KB COREBOOT
section as CBFS using annotation:
COREBOOT(CBFS)@0x0 64k
If there's a new flag "PRESERVE" indicating the section must be
preserved before update, we can declare it following CBFS flag:
COREBOOT(CBFS PRESERVE)@0x0 64k
The flags are directly parsed in fmd_parser, and stored in an union
flashmap_flags. Output modules can choose to ignore or process the
flags.
Currently the only supported flag is "CBFS" (for backward compatible
with annotation). There will be more new flags in follow up patches.
BUG=chromium:936768
TEST=make; boots on x86 "google/eve" and arm "google/kukui" devices
Change-Id: Ie2d99f570e6faff6ed3a4344d6af7526a4515fae
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31706
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
git diff needed to emit diffs without prefix (e.g. a/ and b/) for
clang-format-diff to be able to work.
Also require that the test succeeds, but note that it only runs on
trees whitelisted in $(top)/.clang-format-scope.
Change-Id: I7e9a32eb9281b5cb0b45506a206500fd1d315372
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
80 chars + 2 tabs was the compromise we got to in the last round of
discussion.
Change-Id: I9293a69d1bea900da36501cde512004d0695ad37
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Apollo Lake has four GPIO communities each with a single group named
after the physical location of the pads (I guess): North West, North,
West and South West.
Also add some logic to be able to tag the default function of a pad
(with an asterisk before its name). This seems easier to review in the
tables, but we could also encode the number of the default explicitly
instead.
Used Intel documents:
- 334817-001 (datasheet vol. 1)
- 334819-001 (datasheet vol. 3)
Change-Id: I5cd687fdc1d2ae81f2e948178bf319897b47f031
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
When updating firmware, we may need to preserve some sections like VPD,
calibration data, ... etc. The logic can be hard-coded in updater as a
list of known names, but a better solution is to have that directly
declared inside FMAP area flags.
To do that, the first step is to apply the changes in flash map
(http://crosreview.com/1493767). A new FMAP_AREA_PRESERVE is now
defined and will be set in future with new syntax in FMD parser.
BUG=chromium:936768
TEST=make; boots an x86 image.
Change-Id: Idba5c8d4a4c5d272f22be85d2054c6c0ce020b1b
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Relocations for PC relative instructions must not emitted.
As PC64 are unlikely with current code, it never was an issue.
Change-Id: Ife472a287ff15b1c04a516e25ff13221441fd122
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/31469
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The name was wrong. mFCPGA478 is actually a pseudonym for mPGA478MN,
the successor of the socket that was meant.
The official name of this socket is mPGA478MT. But "Socket M" is much
easier to distinguish.
Change-Id: I4efeaca69acddfcdc5e957b0b521544314d46eeb
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Because coreboot's asserts aren't fatal by default, scan-build finds
problems in code that is actually protected by an assert. This
change fixes that and allows us to add asserts to protect
against other failures.
Change-Id: I9fa605d6309bb40a9cef33b434c9256bf731f457
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/31650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Introduce a measured boot mode into vboot.
* Add hook for stage measurements in prog_loader and cbfs.
* Implement and hook-up CRTM in vboot and check for suspend.
Change-Id: I339a2f1051e44f36aba9f99828f130592a09355e
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Upstream intelmetool is out of date; I suggest I archive it
instead of trying to merge coreboot's changes into it.
However I would like to preserve the licensing of files in the tool
as GPLv2+ where possible instead of GPLv2-only.
Change-Id: I47b1ff2734f54c65f4214b39244bd868ef44b83c
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/c/31587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
VBT on Intel(R) systems is available via sysfs as
/sys/kernel/debug/dri/0/i915_vbt
However the size of this file reads as 0 causing
intelvbttool to fail. This patch implements incremental reads
with realloc for such cases or whenever the file size is not
available (e.g. reading from stdin).
After this patch is applied, intelvbttool can be used as follows:
sudo intelvbttool -f /sys/kernel/debug/dri/0/i915_vbt -d
Change-Id: I5d17095a5747550b7115a54a7619b7294a846196
Signed-off-by: Alex Feinman <alexfeinman@hotmail.com>
Reviewed-on: https://review.coreboot.org/c/31531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Allow EC region to be readable by BIOS/CPU so that flashrom
can read it.
BUG=b:123199222
TEST=Build coreboot with CONFIG_LOCK_MANAGEMENT_ENGINE set,
run firmware_LockedME test.
Change-Id: I306c74a0893355e57632a22a712b1f4fdaa19306
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Put the FMAP FMAP region right above the coreboot CBFS region.
The other regions like RW_MRC_CACHE and CONSOLE often have alignment
requirements so it makes sense to put those on top. This also
simplifies the code the generate the default fmap a little.
Change-Id: I24fa6c89ecf85fb9002c0357f14aa970ee51b1df
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30419
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The coreboot table entry containing the memory entries can have
fields unnaturally aligned in memory. Therefore one needs to perform
an aligned_memcpy() so that it doesn't cause faults on certain
architectures that assume naturally aligned accesses.
BUG=chromium:925961
Change-Id: I28365b204962ac89d65d046076d862b6f9374c06
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Manoj Gupta <manojgupta@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Now running 1.8.3, with a fix to the theme so search still works, and
a recommonmark version that properly rewrites links to .md files.
Change-Id: Ice25554c77a398a71782c8d1cb9e205debd80d67
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/31129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Version 2 IFD will have flmstr5 as EC region access control, consider it
during descriptor lock/unlock process.
BUG=N/A
TEST=Build coreboot with CONFIG_LOCK_MANAGEMENT_ENGINE set, and check
flmstr5 value by hexdump the SPI image at offset FMBA+0x90.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I970064dcf6114a15f054ab7c44349841deb99dc8
Reviewed-on: https://review.coreboot.org/c/31111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Cannonlake and Icelake have same read/write region permission settings
with skylake and kabylake, so add it here as well.
BUG=b:123199222
TEST=Turn on CONFIG_LOCK_MANAGEMENT_ENGINE and build image, check the
setting matches 0x0D for read and 0x04 for write.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I71d8b815c7dff7dcbcff2bf77c85ebf80b8df6d2
Reviewed-on: https://review.coreboot.org/c/31104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This reverts commit 48c24ce5ee.
Reason for revert: Commit broke bincfg, and sym_table as a global
variable is less bad than passing it around in function calls.
Change-Id: Ib8d64a1dc201d17a4e278ab0114958b6807a45ac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
F81866 detection tested with the iBASE SI-613:
superiotool r4.9-420-g034e5e6
Found Fintek F81866 (vid=0x3419, id=0x1010) at 0x4e
F8196* detection is based on chip IDs provided by iBASE, but untested.
Change-Id: I7210e1523a188a8593cd03547bb0c95cd3e7aa39
Signed-off-by: Kyle Stevenson <kstevenson@comqi.com>
Reviewed-on: https://review.coreboot.org/c/31052
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Converts `auto.conf` to an Ada spec file. Write to
$(obj)/cb-config.ads and set the package name to
`CB.Config`.
Change-Id: I97c060d8a613c74a82a18aff9524ad4b01f9df56
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/31053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
With the memory controller the separate sockets becomes a useless
distinction. They all used the same code anyway.
UNTESTED: This also updates autoport.
Change-Id: I044d434a5b8fca75db9eb193c7ffc60f3c78212b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/31031
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Idwer Vollering