Commit Graph

36132 Commits

Author SHA1 Message Date
Kevin Chiu b7107864b7 mb/google/kukui: Add discrete LPDDR4X DDR table support for burnet/esche
LPDDR4x DRAM table for burnet/esche:
[1] = "sdram-lpddr4x-H9HCNNNCPMALHR-4GB"
[2] = "sdram-lpddr4x-MT53E1G32D4NQ-4GB"
[3] = "sdram-lpddr4x-K4UBE3D4AA-MGCL-4GB"
[4] = "sdram-lpddr4x-H9HCNNNCPMMLXR-NEE-4GB"

BUG=b:161768221,b:159301679
BRANCH=master
TEST=emerge-jacuzzi coreboot
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: Ida7ab877c3f7e10a67680b69a1d724ec734d2928
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-07-27 05:14:55 +00:00
Karthikeyan Ramasubramanian f871278675 soc/intel/jasperlake: Invoke PCIe root port swapping
Invoke PCIe root port devicetree update to swap the enabled root port
devices with the disabled devices.

BUG=b:162046161
TEST=Ensure that the PCIe device 1c.7 corresponding to Root port 8 is
swapped with the PCIe device 1c.0 corresponding to Root port 1.

Change-Id: I7d422014a2f5cafc41296ce0a2c116c82aefb0d7
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43835
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-27 05:11:50 +00:00
Alex Levin ff1c5bec03 mb/google/volteer: Add gpio-keys ACPI node for PENH
Use gpio_keys driver to add ACPI node for pen eject event.  Also
setting gpio wake pin for wake events.

Removal and insertion (both edges) triggers IRQ and only removal is a
wake event (rising edge).

Adding for both Volteer and Volteer2 variants.

BUG=b:146083964
BRANCH=None
TEST=tested on a Volteer

Change-Id: Ida3217a5b156320856ce3302c2623eba2230f28d
Signed-off-by: Alex Levin <levinale@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43764
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-27 05:11:23 +00:00
Kane Chen 061f0d205b mb/google/volteer: Modify Delbin variant
Update delbin configuration include GPIO, memory SPD table, I2C devices
and USB type C.

BUG=b:158797761
BRANCH=None
TEST=emerge-volteer coreboot

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I59ce4720e0ffeeeb2c9440bb300686def80211ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42301
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-27 05:10:56 +00:00
Meera Ravindranath 2577407d03 mb/google/dedede: Remove Rcomp resistor and target values
MRC automatically detects the DDR type and sets Rcomp resistor
and target values for JSL and does not require explicit programming.

Change-Id: Ia130765e2cb91d6a39ad00ebbab20e7e87fa42d1
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-27 05:10:24 +00:00
Ren Kuo 98b7033f07 dedede: Create magolor variant
Create the magolor variant of the waddledee reference board by
copying the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.1.1).

BUG=b:58540772
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_MAGOLOR

Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: I3e39e650b82a0aa629a48a00227700b058effb34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-07-27 05:10:07 +00:00
Martin Roth a020903307 util/lint/Kconfig_lint: Update Naked BOOL reference to error
The lint-stable makefile target only watches for errors in the Kconfig
file, so has not protected additional "Naked" references to BOOL type
Kconfig symbols from entering the tree.  Update it to an error so that
they can't continue coming into the codebase.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Icce2a9a627c4fbcaa220df18474cb8bfea8b2a8c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-27 05:07:51 +00:00
Benjamin Doron 552ce003a5 util/inteltool/gpio_names: Make group and community titles consistent
Consistency is good for scripting and automation.
The lowercase "group" in Sunrise Point-LP, for example, was
breaking pattern matching used in intelp2m.

Change-Id: Iffa8a8ac9c17c5cbd8d7b838d9c703cae6a858b5
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43068
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 21:48:48 +00:00
Maxim Polyakov e9b0db388c mb/intel/cedarisland/Makefile: Add missing ramstage.c
Fixes a bug in Makefile.inc, which did not allow building ROM image
with ramstage.c from motherboard configuration.

Change-Id: I70d8a2e1f53e2fa56d514361116a55f175407753
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43457
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 21:47:22 +00:00
Shaunak Saha 148f8397d2 soc/intel/tigerlake: Disable CPU PCIe in FSP
In TGL SoC we have PCH and CPU side PCIe support. This patch
skips CPU side PCIe enablement in FSP if device is disabled in
devicetree. Disabling the initialization of CPU PCIe saves ~30ms
in FspSiliconInit!

BUG=b:158573805
BRANCH=None
TEST=Build and boot volteer and TGL RVP. Using cbmem tool measure the
boot time. FspSilicontInit time is reduced by ~30ms with this patch.

Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Change-Id: I7e8512d22b1463bc4207f80b16dcfb5d00ef4b46
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42557
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 21:45:30 +00:00
Angel Pons 4276050d13 mb/*/*/devicetree.cb: Normalize disabled PIRQ values
If bit 7 of a PIRQ route is set, it is disabled. Modern OSes don't use
PIRQ routing, so we might as well zero the other bits for consistency.

Tested on Asrock B85M Pro4 with SeaBIOS 1.13.0, still boots.

Change-Id: I78980b9ea5e878a6200df0f6c18c5e7d06a7950a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43861
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 21:45:12 +00:00
John Zhao 7417bb0e5a soc/intel/tigerlake: Disable VT-d and no DMAR table for pre-QS platform
Enabling VT-d on pre-QS silicon may have issues like rendering the
Thunderbolt driver useless. This change will ensure that VT-d is
disabled for pre-QS silicon and enabled for QS.

BUG=b:152242800,161215918,158519322
TEST=Validated VT-d is disabled for pre-QS (cpu:0x806c0) and enabled for
QS (cpu:0x806c1). Kernel walks through ACPI tables. If VT-d is disabled
and no DMAR table exists, IOMMU will not be enabled.

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I98a9f6df185002a4e68eaa910f867acd0b96ec2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-26 21:43:36 +00:00
Rizwan Qureshi ec321094f6 soc/intel/common/basecode: Implement CSE update flow
The following changes are done in this patch:
 1. Get the CSE partition info containing version of CSE RW using
    GET_BOOT_PARTITION_INFO HECI command
 2. Get the me_rw.version from the currently selected RW slot.
 3. If the versions from the above 2 locations don't match start the update
    - If CSE's current boot partition is not RO, then
        * Set the CSE's next boot partition to RO using SET_BOOT_PARTITION
          HECI command.
        * Send global reset command to reset the system.
    - Enable HMRFPO (Host ME Region Flash Protection Override) operation
      mode using HMRFPO_ENABLE HECI command
    - Erase and Copy the CBFS CSE RW to CSE RW partition
    - Set the CSE's next boot partition to RW using
      SET_BOOT_PARTITION HECI command
    - Trigger global reset
    - The system should boot with the updated CSE RW partition.

TEST=Verified basic update flows on hatch and helios.
BUG=b:111330995

Change-Id: I12f6bba3324069d65edabaccd234006b0840e700
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 21:42:06 +00:00
Paul Menzel 56642930ab mb/lenovo: Prepend EC event number with 0x to denote hex notation
Currently, the message below is printed, suggesting it’s decimal
notation:

    coreboot-4.12-1530-g7acbd5fc45 Sun Jul 19 07:47:58 UTC 2020 smm starting (log level: 7)...
    EC event 48
    GPI (mask 1000)

Prepend 0x, so it’s clear it’s hexadecimal notation.

    EC event 0x48

Use the command below change all places:

    git grep -l 'EC event %02x' | xargs sed -i 's/EC event %02x/EC event %#02x/'

Change-Id: I8d1e6434a0e550c5a19576f9f7fea05e7a812e49
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 21:40:16 +00:00
Paul Menzel 4907e62893 ec/lenovo/h8: Align macro values in one column
Change-Id: I5691a582d9a195317994413fff4fd3273413b5fe
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 21:40:00 +00:00
Elyes HAOUAS dcc0bb9b62 cpu/intel/car/romstage.c: Remove unused <bootblock_common.h>
Change-Id: Ib47497cf8576063d42bc4a1dd2cc2e0fc56868d3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 21:38:22 +00:00
Elyes HAOUAS 1b446cd4cf src/include: Remove unused 'include <stddef.h>'
Change-Id: I525eb58669d256286e8476b12174d37d1d9aa3bf
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 21:37:55 +00:00
Elyes HAOUAS 5817c56d19 src/include: Add missing includes
Change-Id: I746ea7805bae553a146130994d8174aa2e189610
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 21:37:35 +00:00
Elyes HAOUAS 722e610fbc soc/amd/common/block/psp/psp_smm.c: Add missing <string.h>
'memset' needs <string.h>.

Change-Id: Idc1d72e92c97cd5139ae7439aadb575ef011129a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42342
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 21:37:12 +00:00
Elyes HAOUAS 07b7fc1bca sb/amd/agesa/hudson/hudson.h: Add include <types.h>
BIT(x) needs <types.h>.

Change-Id: I709b98e57275a5666a9627af9f57a7d47c855c88
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43712
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 21:36:15 +00:00
Elyes HAOUAS 146d0c202d nb/amd/pi/00730F01/northbridge.c: Add include <types.h>
BIT(x) needs <types.h>.

Change-Id: I20526f20d9528dd1fce20bcae933e04aea3d24f9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 21:36:06 +00:00
Elyes HAOUAS 54f7847262 src/drivers/intel/soundwire/soundwire.h: Add include <types.h>
BIT(x) needs <types.h>.

Change-Id: Icf8b77713e7b5deb9def19c3e14e89a40ba46107
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 21:35:50 +00:00
Elyes HAOUAS 75f75bf285 src/soc/qualcomm: Add include <types.h>
BIT(x) needs <types.h>.

Change-Id: I6b89bd9616b3f091d6694f9cc20b4bd1a74aad3b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 21:35:36 +00:00
Elyes HAOUAS 29c4d1b717 src/soc/mediatek: Add include <types.h>
BIT(x) needs <types.h>.

Change-Id: I8e4a7af68a52d82117b8b091fa448bb6ad40ae7d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 21:35:27 +00:00
Elyes HAOUAS 23a60fa65b src/soc/intel: Add include <types.h>
BIT(x) needs <types.h>.

Change-Id: I674e3e423e06ee869366ebbd7c9d4248a2f3d9d9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 21:35:12 +00:00
Elyes HAOUAS a83a7db804 src/acpi/device.c: Add include <types.h>
BIT(x) needs <types.h>.

Change-Id: I1a7c5e15468b76e29aa32169fd8ca10445c2eff2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43704
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 21:34:21 +00:00
Tim Wawrzynczak 0aabd07c95 drivers/intel/dptf: Remove prompts from DPTF config options
The prompts for the DPTF Kconfig options were not necessary, they should
be selected based on what DPTF implementation is being used, ASL files
or generated at runtime. It's not really meant to be fiddled with at
build-time. Also rewrite the help text for the _HID selection, to try
and make it more clear when to use y or n.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I6edcabd28426916d9586d501b95b510dfc163fc1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43830
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 21:34:03 +00:00
Maxim Polyakov a76a64833b soc/intel/common/gpio_defs: Remove PAD_CFG_NF_BUF_TRIG
This macro is not correct because the RX Level/Edge Configuration
(trig) and the GPIO Tx/Rx Buffer Disable (bufdis) fields in DW0
register do not affect on the pad in the native function mode.

This is part of the patch set
"src/mb/*, src/soc/intel/common/gpio: Remove PAD_CFG_NF_BUF_TRIG ":

CB:43455 - cedarisland: undo set trig and bufdis for NF pads
CB:43454 - tiogapass: undo set trig and bufdis for NF pads
CB:43561 - h110m: undo set trig and bufdis for NF pads
CB:43569 - soc/intel/common/gpio_defs: Remove PAD_CFG_NF_BUF_TRIG

Change-Id: Ic0416e3f67016c648f0886df73f585e8a08d4e92
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Michael Niewöhner
2020-07-26 21:33:08 +00:00
Maxim Polyakov 6489a19c78 mb/asrock/h110m: undo set trig and bufdis for NF pads
According to the documentation [1], RX Level/Edge Configuration (trig)
and GPIO Tx/Rx Buffer Disable (bufdis) [2] settings are not applicable
in native mode and BIOS does not need to configure them. Therefore,
there is no need to configure this in gpio.h using PAD_CFG_NF_BUF_TRIG
macros. Use PAD_CFG_NF instead and set this fields to 0.

[1] Intel document #549921
[2] Intel document #336067-007US

This is part of the patch set
"src/mb/*, src/soc/intel/common/gpio: Remove PAD_CFG_NF_BUF_TRIG ":

CB:43455 - cedarisland: undo set trig and bufdis for NF pads
CB:43454 - tiogapass: undo set trig and bufdis for NF pads
CB:43561 - h110m: undo set trig and bufdis for NF pads
CB:43569 - soc/intel/common/gpio_defs: Remove PAD_CFG_NF_BUF_TRIG

Change-Id: I6a6b745bdaacb1c4fbf032e4ce54cb25a72d790a
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43561
Reviewed-by: Michael Niewöhner
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 21:32:50 +00:00
Maxim Polyakov 21f50a8fd4 mb/ocp/tiogapass/gpio: undo set trig and bufdis for NF pads
According to the documentation [1], RX Level/Edge Configuration (trig)
and GPIO Tx/Rx Buffer Disable (bufdis) [2] settings are not applicable
in native mode and BIOS does not need to configure them. Therefore,
there is no need to configure this in gpio.h using PAD_CFG_NF_BUF_TRIG
macros. Use PAD_CFG_NF instead and set these fields to 0.

[1] Intel document #549921
[2] Intel document #336067-007US

This is part of the patch set
"src/mb/*, src/soc/intel/common/gpio: Remove PAD_CFG_NF_BUF_TRIG ":

CB:43455 - cedarisland: undo set trig and bufdis for NF pads
CB:43454 - tiogapass: undo set trig and bufdis for NF pads
CB:43561 - h110m: undo set trig and bufdis for NF pads
CB:43569 - soc/intel/common/gpio_defs: Remove PAD_CFG_NF_BUF_TRIG

Change-Id: Icdb6cb39934548e125461929701b33477a74f2a2
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43454
Reviewed-by: Michael Niewöhner
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 21:32:13 +00:00
David Wu a4be3e7d7f mb/google/volteer/var/terrador: Support ELAN i2c-hid touchpad
Update ELAN i2c-hid touchpad configuration

BUG=b:160741785
BRANCH=None
TEST=Verify touchpad is working fine.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I098d8a305c6e04af1562a545ff4af6383665798b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-07-26 21:31:19 +00:00
Matt DeVillier 8437ac5623 mb/purism/librem_skl: Disable CLKREQ for NVMe
This effectively reverts commit 5086ccef
(mb/purism/librem_skl: Fix CLKREQ for 15v3 NVMe).

Some Librem 15v3/v4 boards are showing issues with NVMe detection or
booting via SeaBIOS, so revert this until a proper fix can be found.

Test: build / successfully boot Librem 15v4 with problematic NVMe drive.

Change-Id: I0659f77bbe693f3d3b192a28ff3ef013658930cc
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43490
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 21:30:55 +00:00
Hung-Te Lin 7fc2281715 mb/google/kukui: send SKU ID to EC for device-specific configuration
For devices sharing same firmware, there may be few customization based
on SKU ID - for example being clamshell or form factor. On Kukui and
Jacuzzi platforms the SKU ID is defined on AP SOC, so we have to send
the information to EC.

BUG=b:161767717
TEST=make -j # builds and boots on Juniper
BRANCH=kukui

Change-Id: I8ffdd9fd1e609c1dd4b0e22dc7aab560ccdc842e
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43788
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 21:29:45 +00:00
yan.liu ea63f80e10 soc/intel/common/hda: Add HDA ID for Jasper Lake
Currently, audio is not working on Boten, caused by the coreboot
HDA driver not being run as the Jasper Lake PCI ID is missing.
So, add the Jasper Lake ID.

BUG=b:160651126
BRANCH=NONE
TEST=Connect speaker to audio jack, and verify sound is played.

Signed-off-by: Yan Liu <yan.liu@bitland.corp-partner.google.com>
Change-Id: Ib62c332d8d87201b3e6903251d824e1c3e06cd68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43441
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Peichao Li <peichao.wang@bitland.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 21:28:44 +00:00
yan.liu 0c0faf43c9 mb/mainboard/dedede: update GPIO table for Boten
Adjust GPIO setting to match boten design

BUG=b:160741777
BRANCH=NONE
TEST=Add gpio.c for boten

Signed-off-by: Yan Liu <yan.liu@bitland.corp-partner.google.com>
Change-Id: I4eafee608f657f8ec5a06caf6e99b08b3330512b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43277
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 21:28:04 +00:00
Maulik V Vaghela 28bb308a7a mb/google/dedede: Change HDMI DDC GPIOs to native function
HDMI DDC GPIOs were configured as NC till now in waddledoo.
This may cause HDMI i2c transfer to break and EDID read will
fail due to wrong configuration

Configuring these GPIOs as NF in coreboot to fix the issue.

BUG=b:160324327
BRANCH=None
TEST=HDMI works on DDI2 onn Type-C port

Change-Id: If02f062132d7c3b01b07ea9401e81f451df35c3c
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43294
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 21:27:44 +00:00
peichao.wang 0358f7dada mb/google/vilboz: Tune I2C bus 3 clock
Tune I2C bus3 frequency and insure it meets I2C spec.

BUG=b:161650117
TEST=flash coreboot to the DUT and actual measured I2C bus3
make sure it meet Spec.

Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: Ifa9f0bce723f55a12fd2313788c995f8326e3e7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43661
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 21:27:25 +00:00
Paul Menzel 6d412d738c drivers/mrc_cache: Avoid unused variable assignment
Fix the scan-build warning below:

        CC         romstage/drivers/mrc_cache/mrc_cache.o
    src/drivers/mrc_cache/mrc_cache.c:450:26: warning: Value stored to 'flash' during its initialization is never read
            const struct spi_flash *flash = boot_device_spi_flash();
                                    ^~~~~   ~~~~~~~~~~~~~~~~~~~~~~~
    1 warning generated.

The function can return early before the value is read. Fix this, by
getting rid of the variable, as the value is only read once.

Change-Id: I3c94b123f4994eed9d7568b63971fd5b1d94bc09
Found-by: scan-build (clang-tools-9 1:9.0.1-12)
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-26 21:26:04 +00:00
Usha P 253b7d22fe soc/intel/jasperlakelake: Rename pch_init() code
Rename the pch_init function to bootblock_pch_init and romstage_pch_init
according to the stage it is defined in.

TEST=Able to build and boot Waddledoo successfully.

Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: Iaa0a41f3b5972251d6cd9359bbb46d392196b2e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 21:24:32 +00:00
Sindhoor Tilak 6217a15674 southbridge/intel/common: Replace outb with post_code in finalize.c
The outb() call is replaced with the post_code()

The post_codes.h is replaced with console.h since console.h
includes both the post_code definition and post_codes.h

Change-Id: I21345260e86de30614c416e2f509bd77b9e00cb7
Signed-off-by: Sindhoor Tilak <sindhoor@sin9yt.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-07-26 21:23:14 +00:00
Martin Roth c25c1ebd9e src: Update bare access to BOOL CONFIG_ vals to CONFIG()
BOOL type Kconfig values should be used through the CONFIG() macro.
These instances were not, so update them.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ie4706d82c12c487607bbf5ad8059922e0e586858
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 21:21:03 +00:00
Martin Roth f48acbda7b src: Change BOOL CONFIG_ to CONFIG() in comments & strings
The Kconfig lint tool checks for cases of the code using BOOL type
Kconfig options directly instead of with CONFIG() and will print out
warnings about it.  It gets confused by these references in comments
and strings.  To fix it so that it can find the real issues, just
update these as we would with real issues.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I5c37f0ee103721c97483d07a368c0b813e3f25c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 21:20:30 +00:00
Elyes HAOUAS af56a77915 src: Remove whitespace between 'sizeof' and '('
Change-Id: Iaf22dc1986427e8aa4521b0e9b40fafa5a29dbbd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 21:18:16 +00:00
Angel Pons 89739baf53 {sb,soc}/intel/**/*.c: Use macros for PCI COMMAND bits
We have definitions for the bits in the PCI COMMAND register. Use them.
Also add spaces around bitwise operators, to comply with the code style.

Change-Id: Icc9c06597b340fc63fa583dd935e42e61ad9fbe5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-26 21:17:50 +00:00
Rob Barnes 4d2db06ab5 util: Remove extra newlines in log messages
Print adds a newline implicitly. Simply remove the extra newlines.

BUG=None
TEST=Build zork, observe build log

Change-Id: Idb150c12c90719ba1465e7e7fe45c26d456e2a1c
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43786
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 21:16:35 +00:00
Patrick Rudolph 4aea6915a0 arch/x86/smbios: Fix type4 for EDK2
Mark the CPU as enabled and the socket as populated.
EDK2 tests these flags before further reading this structure.

Change-Id: Ic545bb47c502cb9d2352ba6d43eaed8c97229c02
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43703
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 21:15:34 +00:00
Patrick Rudolph 604295e508 smbios: Add Type19
Implement type 19 by accumulating the DRAM dimm size found in cbmem's
CBMEM_ID_MEMINFO structure. This seems common on x86 where the
address space always starts at 0.

At least EDK2 uses this table in the UI and shows 0 MB DRAM if not
present.

Change-Id: Idee8b8cd0b155e14d62d4c12893ff01878ef3f1c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-07-26 21:15:03 +00:00
Peter Lemenkov f04b262710 autoport: Don't initialize already initialized fields in acpi_tables
Don't initialize fields with zeroes since gnvs structs were zeroed out
in southbridge already. Also add some comments.

See also these commits:

* Commit a76cf28 with Change-Id
  I2ccf4699ba3ed3f5b9402c0340153d4a5bf82682 ("mb/lenovo/*/acpi_tables:
Don't initialize already initialized fields").
* Commit 0c52638 with Change-Id
  I71f092ed7582b4931122d72f41d0b42a7569b96e ("mb/lenovo: Remove
thermal.h header").

Change-Id: I1a0042bc93a2b30babcb896b3df23faf37998f3c
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40479
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26 21:14:10 +00:00
Elyes HAOUAS a92acecb54 mb/emulation/qemu-i440fx/northbridge.c: Use SMBIOS macros
Change-Id: I0297c8c4008d9e448793c38a3758dced9ede0d7e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 21:13:12 +00:00
Elyes HAOUAS 416644085a arch/x86/smbios.c: Use macro for 'type_detail'
Change-Id: I95c40acb2fb390c50c8d1af9dd44999f9d57c2d5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-26 21:12:54 +00:00