This patch adds the DPTF settings specfic to the mainboard and enables
the CPU and other thermal sensors as participant device for fizz.
It also enables the DPTF flag in the device tree for fizz.
BUG=b:64915426
BRANCH=None
TEST=emerge-fizz coreboot and run DPTF observation tool to make sure
DPTF is up and running.
Change-Id: Ic7d125a763f539158aa425fbba1d8a000a3465ca
Signed-off-by: Tsai, Gaggery <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/21147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
We have no wacom digitizer on I2C#3, so remove it.
TEST=build and boot on soraka.
Change-Id: I3f5a1b9ece6fc9a9443477c7a7aa77dbcdf6a703
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/21309
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The MPC.HPCE bit of the ExpressCard root port is not set in vendor
firmware, so autoport didn't generate the right pcie_hotplug_map to
support ExpressCard hotplug.
Also add comments for each PCIe root port.
Change-Id: Ic53e36a7192b9bfa8ff9fca57f4556e972e2611b
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/21310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Some of these will move to EARLY_CBMEM_INIT.
Change-Id: Ia969e30ad7097860180bd047eaf81859a42a747c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Keith Hui <buurin@gmail.com>
NOTE: Some code was currently left behind that may be
required for certain type of board reboots. A followup
patch will address this.
Change-Id: I8fb89fb82c3a3608bb84b29319eb793605538996
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
NOTE: Some code was currently left behind that may be
required for certain type of board reboots. A followup
patch will address this.
Change-Id: I3c1258b4e4dcf6fd04f57f5ab59cb1572a7d1fa3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Do not assert GPIO1_B3 otherwise BT would be disabled on Nefario.
Also, remove DVS support for CENTERLOGIC.
BUG=b:64702054, b:63537905
TEST=build coreboot
Change-Id: I350db2c080f2e41ae56413f5f895557978ef0ba8
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/21176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Enabling XHCI is additionally controlled with Kconfig
option HUDSON_XHCI_ENABLE. Even when it is enabled,
it EHCI debug works on the USB port next to the
DVD drive door.
Change-Id: I83738da6015f58ecd0819c553d333a176365dc78
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Support code for Trinity and Richland is identical now.
I have also come across a unit with Trinity model CPU,
whose CPUID was not listed in f15rl while f15tn already
had support for f15rl.
Change-Id: Ia869429b75a9b308b4d4a84f16914ca629b1b1b5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
BUG=b:64987428
TEST=Verified that touchscreen works on boot-up and after
suspend/resume. No power leakage via stop gpio in suspended state.
Change-Id: Ia260eb444081dbe1646c90e82c2725661e7306bc
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
We no longer use this touchscreen device, so get rid of it.
BUG=b:64987428
Change-Id: I67af787d231317a80998fb483eed5674de19aeb4
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Update cyan's SPD-related functions to more closely mirror
those of other Braswell boards, in order to simplify the upcoming
baseboard/variant setup for Braswell ChromeOS boards.
TEST: boot google/cyan, observe SPD correctly identified in
cbmem log, RAM-related data correct in SMBIOS tables.
Change-Id: Iafe99ec0795764f645e0a91f5b321be5b4c6fd88
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Replaces the ics/954309 driver with a more generic version to
accommodate clockgens with a different amount of registers.
It also features a mask to only touch certain bits of the clockgen.
TODO: set appropriate mask for X60/T60 since the datasheets for their
clockgens can be found.
Change-Id: Ie43c4de7891a39f2f443e78213ecd688134e68d7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Add a 16ms delay to DMIC init by the kernel driver in order to
prevent an audible 'pop' noise when starting to record.
BUG=b:63413023
TEST=manual testing to ensure this device property is present in SSDT:
Name (_DSD, Package () {
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301")
Package () {
Package () {
"realtek,dmic-init-delay",
0x10
}
}
})
Change-Id: If9160ce6992153ba49719029de336595bbf4ae72
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/21271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Current coreboot does not create ACPI device for OS to recognize Raydium
touchscreen.
List the touch screen in the devicetree so that the correct ACPI device
are created.
BUG=b:64705535
BRANCH=master
TEST=emerge-coral coreboot
Change-Id: Ifdea897ef66dd10f29a8a0e72f9406d316fbe8c7
Signed-off-by: Pan Sheng-Liang <Sheng-Liang.Pan@quantatw.com>
Reviewed-on: https://review.coreboot.org/21233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
What is present is APIC and legacy interrupt routing and the soft-off sleep
state. Other sleep states are missing, so are the SuperIO devices.
Boots Linux with and without "noapic" and a Windows XP (installed with
factory BIOS, the installer reportedly requires legacy keyboard).
Change-Id: Iee3ede8683d1ea51317228d4f782af27043cc945
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/18901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Initialize IRQ routing for legacy non-PNP OSes the same as the factory
firmware would do.
Change-Id: I0c7a7d584a2c47471456ab54ef6da815a2dc4e7c
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/18900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
G170 is a board manufactured by WinNET, used in thin clients including
HP Neoware CA19 and IGEL 2110.
Copied from mainboard/bcom/winnetp680 which seems to be a similar
board with an extra PCI slot.
The p680 should probably be moved to winnet/ too, since the board is an
OEM WinNET board, with BCom being just a machine that happens to it.
Change-Id: I90b89ee634d90cfba2e56cca5b76cfd2bd7a8d0b
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/18898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Remove obsolete code. The same settings are always done in southbridge.
Change-Id: Ic893ddbace73ae8b122c4fb675febc7d1e0b5da9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Vendorcode for f15 also has f10 support, so
AMD_AGESA_FAMILY_10 was never selected.
Change-Id: I9a026c36ace88f1110a52d7e24d3e6ab36508932
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tune I2C params for I2C buses 0, 1, 2, 4 and 5 to ensure that the
frequency does not exceed 400KHz.
BUG=b:35948024
TEST=Verified for 25 iterations that the frequency on each bus ranges
<= 400KHz.
I2C0: 375 - 400
I2C1: 377 - 400
I2C2: 377 - 400
I2C4: 375 - 397
I2C5: 375 - 397
Change-Id: Ie30e1a12b66c4660b648a585c4dfd66faf004129
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21208
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add critical and passive threshold to be advertised in thermal zone 0.
Change-Id: Ic75a80994b27ac19651ed52b7fc3c00c65cd9c01
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The LED polarity was set incorrectly, fix using values derived
from original Chromium sources:
branch firmware-mccloud-5827.B, ToT
src/mainboard/google/mccloud/smihandler.c
src/mainboard/google/mccloud/romstage.c
TEST: boot google/mccloud, observe power LED on normally,
blinking in S3/S4, and off in S5.
Change-Id: Ia1f63eebbccb48fcf8543188db390b23045d843e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Commit 0562783182 applied
this change to other Google boards, but cyan was left out.
Bring cyan in line with other Google boards.
Change-Id: Id86bea538a7b82367ea6ddbd3fe3efb1b1c0078d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Cleaning up code to remove support for pre-EVT rev of cyan board.
Analogous to what was done for intel/strago in commit 103f00d.
Change-Id: I29b32da8064e0743cc9c5df02ce7d3441459ee8f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Cherry-pick from Chromium commit a162348.
Remove the hard coded IRQ number for the keyboard interrupt.
IRQ number can change based upon the gpio bank index ordering.
Hence pass the gpio bank and index number so that kernel calculates
the IRQ number.
Original-Change-Id: Icfe5c3995007164bf617575b541758c18ee63a1d
Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I81ff19e3060c533ee76023c7651f741294e9db30
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Adapted from Chromium commit dc59188.
Disable L1 sub state to prevent WiFi randomly disappear condition.
Original-Change-Id: I8975bb4bbbc2fc89b91b06ae02716367890c672d
Original-Signed-off-by: T.H. Lin <T.H_Lin@quantatw.com>
Original-Reviewed-by: Rajat Jain <rajatja@chromium.org>
Original-Reviewed-by: Vincent Wang <vwang@chromium.org>
Oriignal-Tested-by: TH Lin <t.h_lin@quanta.corp-partner.google.com>
Change-Id: I51a1bcca6431e6bc28baf9b09433cec13db925c3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Cherry-pick from Chromium commit 1138727.
Elan touchscreen driver expects the first gpio resource in asl
to be the reset line.
The driver considers the gpio based irq line as reset gpio resource
and changes the direction to output.
This will cause irq registration to fail.
Solution is to pass Interrupt resource for touchscreen irq
instead of GpioInt.
Original-Change-Id: Ia72d4ad80117f3c0014098113c9027416026e65e
Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I1c4b029851e321feeedf713186976fbec42dd82e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Cherry-pick from Chromium commit e49deb1.
Configuring UPD PcdCaMirrorEn. This is a board specific parameter.
CA mirror is the Command Address mirroring option that is board
specific.
Original-Change-Id: I05174e18d650332d838e5036c713e91c4840ee75
Original-Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>
Change-Id: Ibd0c811d41cb592634f7785edb83ad2f423546c5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch to provide new config options to perform LPC and SPI
lock down either by FSP or coreboot.
Remove EISS bit programming as well.
TEST=Build and boot Eve and Poppy.
Change-Id: If174915b4d0c581f36b54b2b8cd970a93c6454bc
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In order to pass type C USB2 eye diagram for sku Santa,
USB2 port#1 PHY register needs to be overridden.
port#1:
PERPORTPETXISET = 7
PERPORTTXISET = 2
BUG=b:64880573
BRANCH=master
TEST=emerge-coral coreboot chromeos-bootimage
Change-Id: I07c0b7b0f08263a348befb7d6fd8d01028314470
Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/21199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move the fchec.h files, which do not seem mainboard specific, out of
the mainboard directories into the southbridge/soc directories.
Change-Id: Idd271c6ab618aa4badf81c702212e7de35317021
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This is not specific to a board but the binary IMC firmware
used on the platform. Also remove unused IMSP and IMWK methods.
Change-Id: I80026bca55f5ba236c080bcd882fc374559942e6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
It was not intentional to change oem_fan_control() to non-static
with commit
23e5ba9 binarypi mainboards: Clean up IS_ENABLED fan control
Every platform except bettong had its own static version of
oem_fan_control, so remove the definition of oem_fan_control from imc.h,
and move it out of imc.c into bettong's BiosCallOuts.c.
Change-Id: Ie95ac1fd3a57259bb35796903aa8753ef0e70d70
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21189
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove all checks for #if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) around
the imc.h includes. Convert from #if to if() for all fan control
setup code. Where necessary, make functions non-static to match the
prototypes in imc.h.
Change-Id: If88af42d00227285931829441909a982fc292b2b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Remove all checks for #if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) around
the imc.h includes. Convert all #if to if() for fan control setup.
Change-Id: I04a9fbbf6f64f45e1a0b544267bfe840ce7fa1d9
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Don't include src/include/cpu/amd/car.h in Via motherboards.
Change-Id: I9d2b3cfb619cf831c7a677992ca03d5f42e5ffd1
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested on T430s with an external screen connected to every one of the
DP ports (miniDP on mainboard, two DP ports on dock), the GRUB payload
can display on both the external screen and the internal LVDS screen.
This is a copy-paste of I8f270d55 "mb/lenovo/x230: Enable libgfxinit".
Change-Id: Ifb1471ecb18927c30c61c64011cbb0e20a465558
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/21070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Sync file with southbridge/amd/common/sleepstates.asl.
SSFG was meant to be used as a mask to enable sleepstates
_S1 thru _S4. However as a logical instead of bitwise 'and'
operation was used, all the states were enabled if only
one was marked available.
Change-Id: I674953f1a5add74e16ddd84c252e8d21501ffefd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Note that against the specs, these definitions repeat
the sleep type also in the reserved fields 3 and 4.
For consistency, don't fix it here now.
Entry for \_S3 is now masked off if HAVE_ACPI_RESUME=n.
Change-Id: Icdc4c81d07fe7a99d5b0f8fa23e9443f58a40ab9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
SSFG was meant to be used as a mask to enable sleepstates
_S1 thru _S4. However as a logical instead of bitwise 'and'
operation was used, all the states were enabled if only
one was marked available.
Note that all boards incorrectly had SSFG == 0x0D that previously
enabled ACPI S3 sleep state even when it was not available.
Change-Id: Ia948becff079383cbf861468da9e8a3ebbf213cb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
SSFG was meant to be used as a mask to enable sleep states
_S1 thru _S4. However as a logical instead of bitwise 'and'
operation was used, all the states were enabled if only
one was marked available.
State _S3 is now set conditionally if HAVE_ACPI_RESUME=y.
For pi/hudson this had been fixed already preprocessor.
Note that all boards had SSFG == 0x0D that previously
enabled ACPI S3 sleep state even when it was not available.
States _S1 and _S2 still appear enabled in ASL/AML
but may not actually work.
TEST: 'cat /sys/power/state' and notice choice 'mem' was
removed from the list of available sleep states.
Change-Id: I27d616871c1771f0c87d8fba23d4ce1569607765
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Kahlee has an ambient light sensor connected to the EC.
TEST=Can see the device in /sys/bus/iio
BUG=b:62030268
Change-Id: Id1138a0fc5270489a734bdf8b1f4ac02d358c0df
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/21146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch assigns the code of coral family, such that,
the 'mosys platform family' returns 'Google_Coral'.
BUG=b:64467244, b:64501879
BRANCH=none
TEST=Examine 'mosys platform family' w/ new firmware.
Change-Id: I1d8f8ca2166a1d80855608cf5b64b0cc7bf3dc93
Signed-off-by: Harry Pan <harry.pan@intel.com>
Reviewed-on: https://review.coreboot.org/21136
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Six mainboards with Winbond superios directly configure
them in romstage.c. All use the common Winbond romstage
code. Change them to use the common config entry code to
allow for code refactoring such as [1]. Build tested.
[1] https://review.coreboot.org/20988
Change-Id: Icecd52ec622b9da86edb07c52893f4db001e5562
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested:
- i5-3550 and DIMM configurations: 2+0+2+2, 0+2+2+2, 2+2+2+2, 4+2+4+2
- debug output from serial port, EHCI debug port not found
- Arch Linux (Linux 4.11.5) loaded from SeaBIOS, GRUB2, and Linux payload
- all PCI and PCI Express slots
Issues:
- sometimes the machine fails to boot, with serial debug output it can
be seen it stucks after SMM initialization, and more likely to fail
to boot when serial cable is attached
- no S3 resume (not tested in vendor firmware)
Change-Id: I94fbfcee06921538b32aa3c23efa642e7e405ef6
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/20227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Current coreboot does not create ACPI device for OS to recognize Raydium
touchscreen.
List the touch screen in the devicetree so that the correct ACPI device
are created.
BUG=b:64821783
BRANCH=reef
TEST=emerge-snappy coreboot
Change-Id: I8852e38f01f82b80c2c9718b93baf5894dbd745b
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/21083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Current coreboot does not create ACPI device for OS to recognize MELFAS
touchscreen.
List the touch screen in the devicetree so that the correct ACPI device
are created.
BUG=b:64779224
BRANCH=reef
TEST=emerge-snappy coreboot
Change-Id: If2bc910d641e0cf2b120ed883c5788542959f568
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/21067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
On this device libgfxinit successfully initializes textmode and
framebuffer mode on the device connected to the HDMI1 port.
VGA port is not tested, due to lack of VGA with valid EDID.
Every ports works on GNU/Linux with kernel version 4.9+80+deb9u1.
Due to limitations within the libgfxinit's current build system,
it needs "select NORTHBRIDGE_INTEL_IVYBRIDGE" to work, even it is
PCH instead of CPU for which libgfxinit should be configured here.
Change-Id: Ib1513fc57b79eebc5d047c2e24585731c44bc215
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/21071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Split `i2c.h` into three pieces to ease reuse of the generic defi-
nitions. No code is changed.
* `i2c.h` - keeps the generic definitions
* `i2c_simple.h` - holds the current, limited to one controller driver
per board, devicetree independent I2C interface
* `i2c_bus.h` - will become the devicetree compatible interface for
native I2C (e.g. non-SMBus) controllers
Change-Id: I382d45c70f9314588663e1284f264f877469c74d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The code is based on autoport. I'm using a machine with discrete GPU,
and gfx.* in devicetree.cb is from 2760p.
It can be debug with serial port on dock.
Tested:
- CPU and memory: i5-2540M, 4G+0
- Arch Linux (Linux 4.11.7, SeaBIOS payload, with ATOM BIOS extracted
from vendor UEFI firmware)
- USB ports
- SD card reader
- WLAN
- DP display
- S3
Change-Id: I9c42723ba240a2e9b46998c1a8a708aebc66c604
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/20501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The code is based on autoport. The EHCI debug port is the upper USB
port beside the battery.
Tested and working:
- CPU and memory: i7-3720QM, 4G+4G
- Linux Mint with Linux 4.4 (SeaBIOS payload)
- All USB ports
- ExpressCard
- WLAN
- AC and battery status
- S3
- Other devices detected: DVD drive, smartcard reader, fingerprint, bluetooth
Not tested:
- VGA and DP
- Ethernet and modem
- Dock
Change-Id: I9f3cd124fc676d49add59e9f0a07f70a6bb0fff0
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/20489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The code is based on the code generated by autoport.
The EHCI debug port is between the DP port and eSATA port.
The serial port on dock can also be used for debugging.
The model with discrete graphics is not tested.
Tested and work:
- memory: 0+4G, 4G+0, 4G+4G
- Linux (Arch Linux with kernel 4.10.6) boot from SeaBIOS payload
with native graphics init
- WLAN
- keyboard, trackpoint and touchpad
- USB
- serial port on dock
- fan control
- AC and battery status
(EC) blobs:
This laptop uses SMSC KBC1126 EC, and there are two blobs needed by it.
You can use the tools in util/kbc1126/ to extract them and insert them
to the coreboot image using the following configuration:
-> Chipset
-> Add firmware images for KBC1126 firmware
Change-Id: Icbc051e2272b8ea73627940db15a56901d737472
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/18985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The code is generated by autoport.
The flash chip is socketed beside the WLAN slot. The EHCI debug port
is on right side of the laptop beside the RJ11 connector.
Things that work:
- memory: 0+8G, 4G+8G
- Linux (Linux Mint 18.1 with Linux 4.4)
- native graphics init + SeaBIOS payload with SeaVGABIOS
- all 3 USB ports
- WLAN
- WWAN
- SD card reader
- expresscard
- S3 suspend and resume
- internal flashing after IFD is unlocked and coreboot is flashed
- keyboard, trackpoint and touchpad
- fan control
- AC and battery status
Issues:
- Wacom digitizer does not work (even after I add it in DSDT)
- GRUB payload will freeze (in all Elitebooks, including chainloading GRUB
from SeaBIOS)
Things that are not tested:
- smart card reader
- cable modem
(EC) blobs:
This laptop uses SMSC KBC1126-NU as EC. It needs two blobs in the
flash chip. You can use the tools in util/kbc1126 to extract them
from OEM firmware, and use the following configuration to insert
them to coreboot image:
-> Chipset
-> Add firmware images for KBC1126 firmware
Change-Id: I3ffdb9f9c71f6c9a84e896abc3c424c8dd4bed0e
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/18241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The Giantec semiconductor GT24C16S and ON semiconductor CAT24C16
are the industrial standard electrically erasable programmable
read only memory (EEPROM's) and this patch adds ACPI objects
and power resources for NVMEM device.
Update DOVD method to set sensor IO LDO voltage and remove repetitive
code from OVFI, VCMP and NVMP power resources.
BUG=b:38326541
BRANCH=none
TEST=Build and boot soraka. Dump and verify that the generated DSDT table
has the required entries. Read the NVMEM content via sysfs interface.
Change-Id: If49ed33b7e1de1eabf317b31ceed8568dfca0aae
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
BUG=b:64705535
BRANCH=master
TEST=emerge-coral coreboot chromeos-bootimage and verify the keyboard
backlight can be bright and alt+f6, alt+f7 function keys can be used.
Change-Id: I777247a6b58d3d50b72f12ca2fcab49a06ed5431
Signed-off-by: Pan Sheng-Liang <Sheng-Liang.Pan@quantatw.com>
Reviewed-on: https://review.coreboot.org/21027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
A decision has been made that boards with LATE_CBMEM_INIT
will be dropped from coreboot master starting with next
release scheduled for October 2017.
As existing implementation of CAR teardown in AGESA can only
do either EARLY_CBMEM_INIT or ACPI S3 support, choose the former.
ACPI S3 support may be brought back at a later date for
these platforms but that requires fair amount of work fixing
the MTRR issues causing low-memory corruptions.
Change-Id: I5d21cf6cbe02ded67566d37651c2062b436739a3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Romstages of many 440BX boards included headers that are redundant.
Remove them as part of a bigger cleanup effort.
This finishes off what began in https://review.coreboot.org/20693.
Change-Id: I102a4f6e492eb607b7f88d4c6e15072a8b7fdc46
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
BUG=b:64468585
BRANCH=none
TEST=with the other sku-id related patches applied, coreboot obtains the
right SKU ID from EC
Change-Id: I96a0e030bbc5f1c98165e70353340c413f8dc352
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/20947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add LPC common code to be shared across Intel platforms.
Also add LPC library functions to be shared across platforms.
Use common LPC code for Apollo Lake soc. Update existing Apollolake
mainboard variants {google,intel,siemens} to use new common
LPC header file.
Change-Id: I6ac2e9c195b9ecda97415890cc615f4efb04a27a
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/20659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Simplify funciton names and remove reference to hudson in stoneyridge.
The southbridge in Stoney Ridge is Kern and hudson naming is
no longer accurate.
BUG=b:62200157
BRANCH=none
TEST=Build and booted on Kahlee.
Change-Id: Ide7a72dae69b881997101f1e37a1ac739901744d
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20912
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a new Kconfig option to ignore memory fuses that limit the
maximum DRAM frequency to be used. The option is disabled by
default and should only enabled by experienced users as it
might decrease system stability or prevent a successful RAM
training.
Remove conflicting devicetree settings.
Change-Id: I35dd78a02bcaafce8ba522d253c795d7835bacae
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nicola Corna <nicola@corna.info>
Get rid of old hybrid graphics driver and use the new one.
1. Disable IGD and PEG in early romstage.
The PEG port will get disabled on devices that do not have a
discrete GPU. The power savings are around ~1Watt.
The disabled IGD does no longer waste GFX stolen memory.
2. Get rid of PCI driver
The Nvidia GPU can be handled by the generic PCI driver and allows
to use the ACPI _ROM generator for Switchable graphics.
3. Settings are stored in devicetree.
One driver for all Lenovo hybrid graphics capable devices.
4. Add support for Thinker1 GPU power handling.
Only boards that do use reference design 2012 are known to be
supported. Needs test on boards that do you use reference design 2013.
Should reduce idle power consumption when using IGD by ~5Watt.
Tested on Lenovo T430 without DGPU. PEG port is disabled.
Needs test on all devices.
Change-Id: Ibf18b75e8afe2568de8498b39a608dac8db3ba73
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This mainboard features is an G43 northbridge, ICH10 southbridge and
Winbond W83627dhg SuperI/O. This board is impossible to flash
internally with vendor bios (BIOS region is WP and other regions like
IFD and ME are read only and inaccessible respectively). Due to either
ICH10 or board layout it is also impossible to do ISP, which requires
desoldering flash chip. To make hacking more easy there is an empty
SPI header next to spi flash pads which can be hooked up to a SPI
flash.
What works:
* 2 DDR2 dimms per channel (tested with 1+2G in CH0 and 2+2G in CH1);
* SATA with AHCI
* Integrated GPU with option rom (extracted from a Gigabyte vendor
bios)
* VGA (on DVI) with NGI if patched to use DVI gmbus port for output
* PCI
* Reboot and S3 resume
* Descriptor mode with ME disable straps and ME region absent (no
working gbe in this configuration though)
* USB.
What does not work:
* GBE (probably requires working ME);
* Analog on DVI port out is shaking, which is not the case with vendor
BIOS (setting clockgen on smbus 0x69 like vendor fixes it).
* Booting with ME enabled (needs raminit patches for that)
Not tested:
* Sound;
* All the rest.
Not coreboot related problems:
* Flashing this board with vendor bios is a PITA and requires
desoldering flash chip;
* In situ programming is not possible.
TESTED with SeaBIOS and Linux 4.10.8
Change-Id: If27280feb7cbf0a88f19fe6a63b1f6dbcf9b60f4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Updating the common smihandler to handler gpi events which
originally were going to be left to each soc to handle. After
some more analysis the gpi handler can also be commonized.
Change-Id: I6273fe846587137938bbcffa3a92736b91982574
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/20917
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Each line of spd config overwriting the slot 0 instead
of appending it.
Change-Id: I0124aa34f1d4fcb30810fb7eef03d4828a7ac430
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Tested-on: lenovo x1 carbon gen 1 with elpida 8GB
Fixes: e9787ff61f ("mb/lenovo/x1_carbon_gen1: Add 4GiB SPD index 2")
Reviewed-on: https://review.coreboot.org/20918
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The schematics isn't available for the board, but other L*00 series boards
seem to use a different, compared to T*00 series, GPIO layout.
As it has never been tested, remove the broken driver.
Change-Id: I4bfa02fdbc5da5b556010c2f300faaf6dc845b80
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Configuring the clockgen like vendor bios fixes the issue where the
display wobbles from left to right on the analog VGA output.
Note: This seems to be common issue/requirement on Intel devices from
that generation (also happens on dg43gt).
TESTED on Intel D510MO.
Change-Id: I08449f0b8b90a1781e6dec91140bf219ea07aaf9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19595
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
some gpio irq need to set input pull initialization status
to guarantee to get the right irq trigger. let's add this argument
in gpio_input_irq() function
BRANCH=None
BUG=None
TEST=boot from bob
Change-Id: I9b8e6497f07146dafdb447a6ea10d039a2a2fa33
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/20866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Decrease the link-frequencies as recommended by Omnivision for OV13858
and OV5670 camera sensors.
BUG=b:38326541
BRANCH=none
TEST=Build and boot soraka. Dump and verify that the generated DSDT table
has the required entries. Verified that sensor probe is successful.
Change-Id: I78fb2d3527f66b5147123a9c8fc4cb95650f86b6
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
GPP_B8 acts as input to the inverter whose output controls PERST#
signal to wifi module. Out of reset, GPP_B8 is configured as
input by default. Since there is no external pull-down on it, this
line is floating and results in PERST# being asserted until ramstage
where the GPIO was originally configured. Because of this the wifi
chip is not ready during the PCIe initialization step. Move the
configuration of GPP_B8 to bootblock so that wifi device is taken out
of reset as early as possible.
BUG=b:64181150,b:62726961
TEST=Verified with warm reboot and suspend-resume stress test that
wifi is still functional.
Change-Id: I68e1bd67499262a17daade72e9a9fd32934a184d
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add gpio.c to bootblock so that the variant early_gpio_table can be
used for configuration in bootblock.
BUG=b:64181150,b:62726961
Change-Id: I77181334257f2fd19982ecafc1f58afe912f4280
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Use the genric GPIO library. Add the required functions.
Also, update the Kahlee mainboard dependency to match.
Change-Id: I2ea562b052401efff3101f736788ca77d21e6de6
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20543
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We define BINARYPI_LEGACY_WRAPPER a method of calling AGESA
via functions in agesawrapper.c file. The approach implemented
there makes it very inconvenient to do board-specific
customisation or present common platform-specific features.
Seems like it also causes assertion errors on AGESA side.
The flag is applied here to all boards and then individually
removed one at a time, as things get tested.
New method is not to call AGESA internal functions directly,
but via the dispatcher. AGESA call parameters are routed to
hooks in both platform and board -directories, to allow for
easy capture or modification as needed.
For each AGESA dispatcher call made, eventlog entries are
replayed to the console log. Also relocations of AGESA heap
that took place are recorded.
New method is expected to be compatible with binaryPI.
Change-Id: I2900249e60f21a13dc231f4a8a04835e090109d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We define AGESA_LEGACY_WRAPPER a method of calling AGESA
via functions in agesawrapper.c file. The approach implemented
there makes it very inconvenient to do board-specific
customisation or present common platform-specific features.
Seems like it also causes assertion errors on AGESA side.
The flag is applied here to all boards and then individually
removed one at a time, as things get tested.
New method is not to call AGESA internal functions directly,
but via the dispatcher. AGESA call parameters are routed to
hooks in both platform and board -directories, to allow for
easy capture or modification as needed.
For each AGESA dispatcher call made, eventlog entries are
replayed to the console log. Also relocations of AGESA heap
that took place are recorded.
New method is expected to be compatible with binaryPI.
Change-Id: Iac3d7f8b0354e9f02c2625576f36fe06b05eb4ce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In Scarlet pwm regulatoror minimum value and maximum value differs from
other board variants, Correct it so we can get the right voltage.
Change-Id: I1f722eabb697b3438d9f4aa29c205b0161eb442a
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/20831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
in Scarlet the Sdcard control gpio differs from other
board variants, So set the GPIO to high on Scarlet.
Change-Id: I5fa19b212a716213462eea58b6242392d32a2c5c
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/20803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Scarlet gpio4cd use 1.8V powerdomain, let's make a
correct register setting, otherwise even the uart
does not work.
Change-Id: Ib5a8b2a4d92502fb829688d0a3e1b645d53cd7fc
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/20802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add the Google mainboard GPIOs to the ACPI table.
Change-Id: I9b5952ed3934b938cb50650890a7b434e6306fd1
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The EC KBC controller was not initialized, so the EC wouldn't put
keys in the output buffer. With nothing in the buffer, vboot didn't
try to boot the USB stick. Add the driver to setup the KBC called by
EC init.
BUG=b:62066405
BRANCH=none
TEST=Boot Kahlee with USB stick and CTRL+U boots the stick.
Change-Id: If9346fda558e802536c7de38da5b21fd25320e40
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20480
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move mainboard_ec_init out of mainboard enable to the more
appropriate mainboard init phase.
Change-Id: Ieabcecf70e4de0b42fc639d031755b6d0b66f08a
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add ACPI support for the Google EC, which requires GNVS support
for passing information from the EC to firmware and OS.
Change-Id: I0a308bcd608a135cc9633273a05527f020b60743
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/20276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Set up the TPM decode to SPI prior to verstage.
Enable LPC TPM and remove the mock data.
Note, Kahlee TPM is on SPI, but decoded by the LPC block.
BRANCH=none
BUG=b:62103024
TEST=coreboot and Depthcharge reports TPM found.
Change-Id: Iab92259ebeaa40937309fad05cc45d9ca6d41357
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Store VBOOT NV data in CMOS. This allows VBOOT to save flags and data
to be used in multiple stages and depthcharge. Fixes developer mode
USB boot.
Change-Id: I50b45e687a1a1c71838bcc390212b28d7e634a19
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Set DDI port 2 type to Display Port.
Change-Id: Idc5e57e01d4f0073ac50533c1b04a95bcae67473
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Inform AGESA to setup an I2S codec instead of an Azalia codec.
This is step one for audio to work. ASL to connect the
driver and the hardware is in a follow-on patch.
Change-Id: I7ece5d8c317ddc76e0e6b2a005256bc384fe51e2
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/19841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Sync map_oprom_vendev() and autoport with the list of PCI ids in the
`gma.c` driver, remove one obsolete Kconfig default override.
Change-Id: I12f24f415b695c516fbb947114e09c873af2e439
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
All affected boards did the same USE_NATIVE_RAMINIT distinction or
actually selected USE_NATIVE_RAMINIT. Also update autoport.
Change-Id: I924c43cec1e36e84db40e4b8e1dd0e05cad2b978
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20813
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Add ASL for the Elan touchpad driver connection in ChromeOS.
This is based on the Auron and Rambi ASL. The AMD ACPI code
doesn't have the auto table generation the newer Intel
Chrome SOC use.
Device visible to OS: /sys/bus/acpi/devices/ELAN0000
Change-Id: Id3fc8c8855b0296f43a502e81143498d663468ec
Signed-off-by: Ivy Jian <ivy_jian@compal.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Clean up the ASL whitespace and formatting to match the iasl -d
style as other parts of coreboot.
Change-Id: I61689cb55dc26cbad160d45aa0a36c00b386fe0c
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The AMD internal A-link (AAHB device) doesn't support an IRQ,
so remove it. This solves a conflict with the GPIO IRQ required
for touchpad operation.
Change-Id: Iefaf33cfb2babc29d35b5372fc3a338a72c78a4a
Signed-off-by: Ivy Jian <ivy_jian@compal.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
WLAN_PE_RST control was moved from EC to SoC, it connected to GPP_B8.
Configure GPP_B8 to drive low.
TEST=Wifi card is detected and connect to an AP.
Change-Id: I6a6ea0ddefe8402284fe37665864c7a1961cbc15
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/20804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The Kahlee Nuvoton EC firmware doesn't support SERIRQ quiet mode, yet.
Set continuous mode until the quiet mode feature is available. This
allows keyboard and other EC based interrupts through.
Change-Id: If77c91fde2bd0f4da85413879fefb753ae6297de
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19840
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
GPIOs for I2C3 were being unset in amdinitmid if the GPIO
enable table wasn't passed. It had been initialy set in amdinitreset.
Pull the GPIO settings into their own file that can be used in
bootblock and later stages.
Change-Id: I41cd7873f8c8543c95ad8653e0a3887f7d0487a2
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The EC is a legacy 8042 device. Don't set LEGACY_FREE and correctly
report in the FADT.
Change-Id: I041ea4b44372178f3d6073b6ebc8003abc097703
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19836
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the basics for building as a ChromeOS device. ChromeOS
and ChromeEC are dependent on each other, so bring them in
together. The EC is a Nuvoton and you can find additional
details in the Chromium EC repo.
Add the Google HWID "Kahlee TEST 6421".
The chromeos.fmd for Kahlee takes advantage of the AGESA
located outside cbfs and includes typical RW, VPD, and
MRC areas.
There are some updates required to depthcharge, vboot, GPIOs,
and the ChromeEC before we have a complete-ish system.
Change-Id: Ifb0a6afc01dd80ef9e7bb81039d9152936043999
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Update GPIO settings based on the schematic.
Change-Id: Ic8a876198a3ba9029d1aabb273418923e40bfcc6
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Update for a single DIMM with an SPD at address A0.
Change-Id: I646f079c99cbaffd7094773243600c3030308325
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19833
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Kahlee does not use the AMD IMC. Remove the files and calls.
Change-Id: Ia837551b592b4f473eb38c06c516586fb6c95c88
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19832
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update for the Stoney Ridge FT4 package and the on chip UART.
Change-Id: I11468834a9ef03da084c156c74d55a19416d98c4
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19831
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Copied from amd/gardenia. Update the appropriate board name strings.
Uses the soc/ structure.
Change-Id: Ia68b16969518f4d63d5d2dea7658a472b2daca05
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add dedicated CAR setup and teardown functions and Kconfig
options to force their inclusion into the build. The .S files
are mostly duplicated code from the old cache_as_ram.inc file.
The .S files use global proc names in anticipation for use with
the Kconfig symbols C_ENVIRONMENT_BOOTBLOCK and POSTCAR_STAGE.
Move the mainboard romstage functionality into the soc directory
and change the function name to be compatible with the call
from assembly_entry.S. Drop the BIST check like other devices.
Move InitReset and InitEarly to bootblock. These AGESA entry
points set some default settings, and release/recapture the
AP cores. There are currently some early dependencies on
InitReset. Future work should include:
* Pull the necessary functionality from InitReset into bootblock
* Move InitReset and InitEarly to car_stage_entry() and out of
bootblock
- Add a mechanism for the BSP to give the APs an address
to call and skip most of bootblock and verstage (when
available) (1)
- Reunify BiosCallOuts.c and OemCustomize.c
(1) During the InitReset call, the BSP enables the APs by setting
core enable bits in F18F0x1DC and APs begin fetching/executing
from the reset vector. The BSP waits for all APs to also
reach InitReset, where they enter an endless loop. The BSP
sends a command to them to execute a HLT instruction and the
BSP eventually returns from InitReset. The goal would be to
preserve this process but prevent APs from rerunning early
code.
Change-Id: I811c7ef875b980874f3c4b1f234f969ae5618c44
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The mc_apl1 mainboard needs to disable the RAPL algorithm for a constant
power management of the processor package. An active RAPL algorithm
leads to negative effects with our real time software.
Change-Id: I09ca56a034fd3896a000e64cac35f12fb507a682
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/20760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Configure GPIO.1 and GPIO.2 as sensor SDA and SCL respectively
for TPS68470 PMIC in daisy chain mode.
* GPIO.1: Sensor SDA in daisy chain mode.
* GPIO.2: Sensor SCL in daisy chain mode.
BUG=b:38326541
BRANCH=none
TEST=Build and boot soraka. Dump and verify that the generated DSDT table
has the required entries. Verified that sensor probe is successful.
Change-Id: I7f9686427772a33c06e4cdaafee9b0349d700639
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch controls the camera devices power through ACPI power resource.
* Add Opregions for PMIC1 and PMIC2,
* TI_PMIC_POWER_OPREGION
* TI_PMIC_VR_VAL_OPREGION
* TI_PMIC_CLK_OPREGION
* TI_PMIC_CLK_FREQ_OPREGION
* Add power resources for sensors and VCM,
* OVTH for CAM0
* OVFI for CAM1
* VCMP for VCM
* Implement _ON and _OFF methods for sensor and VCM module's power on
and power off sequences.
BUG=none
BRANCH=none
TEST=Build and boot kblrvp. Dump and verify that the generated DSDT table
has the required entries. Verified that sensor probe is successful.
Change-Id: I02c4784ab3f4d6e1f0e657ad50b727ff11da8b9c
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Bind the camera sensor and CIO2 devices through the ports and endpoints
configuration available in _DSD ACPI object.
* Port represents an interface in a device.
* Endpoint represents a connection to that interface.
BUG=none
BRANCH=none
TEST=Build and boot kblrvp. Dump and verify that the generated DSDT table
has the required entries.
Change-Id: If328864dbb61586a4887c7fcae740a12eda7cc92
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch adds mipi_camera.asl and enables
I2C2, I2C3, CIO2 and IMGU devices,
* Add TPS68470 PMIC1 and PMIC2 related ACPI objects.
* Add OV cameras related ACPI objects.
* Add Dongwoon AF DAC related ACPI objects.
* SSDB: Sensor specific database for camera sensor.
* CAMD: ACPI object to specify the camera device type.
KBLRVP has two PMIC's sitting on I2C2 and I2C3. CAM0 and
CAM1 power requirements are handled by PMIC1 and PMIC2 respectively.
BUG=none
BRANCH=none
TEST=Build and boot kblrvp. Dump and verify that the generated DSDT table
has the required entries.
Change-Id: Ibaf26dad74ca1e7c9f415ae75c4ed8558ad99e2f
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add both Cannonlake U DDR4 RVP and Cannonlake Y LPDDR4 RVP support.
Implement SPD entry to FSPM for both platforms, seperated platform
specific DQ/DQS/Rcomp input to FSPM as well.
Change-Id: If71662353ddba89a9e831503a2d80dd5ebd65de3
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Sets RAPL PL1 power to ~6W.
Note: 7.5W setting gives a run-time 6W actual measured power.
Tested on GLK w/kernel 4.11.0 by reading MSR 0x610 at runtime
and comparing to measured power on an instrumented board.
Change-Id: I07caeb2895a579387025d3b0fb7f1d2c3d5e2665
Signed-off-by: Cole Nelson <colex.nelson@intel.com>
Reviewed-on: https://review.coreboot.org/19746
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GLKRVP is a reference board for GLK SOC
RVP1 has DDR4 and RVP2 has LPDDR4
RVP2 is enabled by default and CONFIG_IS_GLK_RVP_1 should be selected
if building for RVP1
GLKRVP can work with internal Intel EC or external Chrome EC AIC.
For internal EC, CONFIG_EC_GOOGLE_CHROMEEC will not be selected (
CONFIG_GLK_INTEL_EC should be selected for internal EC config)
By default, CONFIG_GLK_CHROME_EC is selected for external ChromeEC AIC
config.
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Change-Id: Iab688aca6a4f5c5e32801215ba3a1a440e50fbef
Reviewed-on: https://review.coreboot.org/19604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix the OEM settings for two ports. Fix and clarify comments to
reflect Rev. B of the board design.
Change-Id: I2812ea5945f67229872e78041c771606047bbbec
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20744
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It requires changes to match the hardware. Except for the weak
attributes that are now removed in coral's copy, the file is identical
to the baseboard version.
BUG=b:63876329
BRANCH=none
TEST=none
Change-Id: Ib0c5f0ecae9919f20631dacef0253416989fb011
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/20751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Fix regression introduced by commit 7ffb329f.
The default value for usb_always_on is no longer sane and is replaced
by the same default that is used on all other boards (disabled).
Change-Id: Ia8854a8491bc56507d01e08e1ca1e195a1d62bfc
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
The romstage for both is line-for-line identical.
Merge both into P2B-DS so it benefits from my
modernization efforts.
Change-Id: Idd964f4c5c4dfd9e2e0ac4a4f41e4ee9a84a729c
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The romstage for both is line-for-line identical.
Merge both into P2B-LS so it benefits from my
modernization efforts.
Change-Id: I2d1a46236f83a4955ceb5e98b576cce0560f28df
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Romstage of many 440BX boards included headers that are not used.
Remove them as part of a bigger cleanup effort.
Change-Id: I89ddeda3c90e1a4907c05851185b69f3b29e54ba
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
I am able to complete a board-status run over onboard ethernet
(ie. it works) without this entry, so it's not necessary.
Change-Id: Iabdf1a1ff3c904bea1b7b5eaefb1d23831dd2cb9
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Enable S0ix for poppy and soraka in their device trees respectively.
BUG=b:36630881
BRANCH=none
TEST=Verified S0ix and S3 operation on Poppy and Soraka (250+ iterations).
Change-Id: I9ba91499e54f729970448af6f71804ad5b3cb836
Signed-off-by: Rajat Jain <rajatja@google.com>
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
GPP_B7, GPP_D1 and GPP_D2 are not used going forward. Mark them as NC
in gpio table.
BUG=b:62322846,b:62240755
Change-Id: I7aee08314e6ce96d5913ae315bf75f5c04ab7370
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20672
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that soraka is starting to deviate from the baseboard w.r.t. gpio
settings, make a new copy of gpio table before we make any
variant-specific changes in it.
BUG=b:62240755,b:62322846
BRANCH=None
TEST=Verified with gpio_debug=1 in skylake/gpio.c that the gpio
configuration before and after this change remains same.
Change-Id: I448d18f18b63e9bfb739c518d599de3b9b602dc2
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This mainboard is equipped with DDR3L modules which support ECC. The
BWG says that for activating ECC the FSP-M parameter MemoryDown must be
set to 5.
Change-Id: Idc68df1e2bae2396c9b9788d4a026a75b7d9119b
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/20634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
The OS of this mainboard needs the _PIC method for the selection of the
type of interrupt routing.
Change-Id: Ic82ba1b368aff0030422d9602ebc882247a2191b
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/20618
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This patch adds the necessary changes to support Scarlet revision 1.
Since the differences to revision 0 are so deep, we have decided not to
continue support for it in the same image. Therefore, this patch will
break Scarlet rev0.
All the deviations from other Gru boards are currently guarded by
CONFIG_BOARD_GOOGLE_SCARLET. This should be changed later if we
introduce more variants based on the newer Scarlet board design.
Change-Id: I7a7cc11d9387ac1d856663326e35cfa5371e0af2
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/20587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
Our structure packing for Rockchip's gpio_t was chosen arbitrarily. ARM
Trusted Firmware has since become a thing and chosen a slightly
different way to represent GPIOs in a 32-bit word. Let's align our
format to them so we don't need to remember to convert the values every
time we pass them through.
CQ-DEPEND=CL:572228
Change-Id: I9ce33da28ee8a34d2d944bee010d8bfc06fe879b
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/20586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=none
BRANCH=reef
TEST=emerge-snappy coreboot chromeos-bootimage and verify the keyboard
backlight can be bright and alt+f6, alt+f7 function keys can be used.
Change-Id: I6d06f72e1ccc66292b4e5f867314d84c309af885
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/20633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We've just decided to remove the only known use of the VBSD_SW_WP flag
in vboot (https://chromium-review.googlesource.com/c/575389), since it
was unused and never reliable on all platforms anyway. Therefore, we can
now also remove the coreboot infrastructure that supported it. It
doesn't really hurt anyone, but removing it saves a small bit of effort
for future platforms.
Change-Id: I6706eba2761a73482e03f3bf46343cf1d84f154b
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/20628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
SDCARD is not used on this mainboard.
Change-Id: I28d23cdb3652bf736b19daf67c7057c396230e24
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/20611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The romstage for CS5536 platforms were including early_smbus.c and
early_setup.c. Build these into romstage from the makefile, and remove
the #includes.
Add a Kconfig option for platforms that do not use the
early smbus code.
Change-Id: I2e6a9cd859292b4dd4720b547d1ff0bbb6c319cf
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Calling disable_cache_as_ram() with valuables in stack is not
a stable solution, as per documentation AMD_DISABLE_STACK
should destroy stack in cache.
While we still preserve cache contents (there is wbinvd deep
inside AMD_DISABLE_STACK macro), we now actually do a stack
switch and much more closely meet the specification of CAR
teardown sequence in AGESA specifications.
We now somewhat incorrectly include files from agesa/ tree,
but the whole agesawrapper.c file removal will address the
issue of overall directory layout.
Change-Id: I2bac098099c1caffea181356c63924f4b5a93b54
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Set PL2 and SysPL2 for Fizz based on cpu id.
BUG=b:7473486, b:35775024
BRANCH=None
TEST=On bootup make sure PL2 and PsysPL2 values set
properly (through debug output)
Change-Id: I5c46667fdae9d8eed5346a481753bb69f98a071b
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/20420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
All other Sandy/IvyBridge google boards have this function,
which is required by nb/sandybridge/raminit_mrc.c. Without it,
compilation fails when using MRC vs native ram init.
Change-Id: I3318700c540e97baf0a75aafb73f160aaae6703f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
There will be more follow-up changes.
BUG=b:63537905
BRANCH=None
TEST=emerge-nefario coreboot libpayload
Change-Id: I6bb80723ea2573df617026a4a5740adb89331892
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/20522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tsai, Gaggery