Commit graph

11 commits

Author SHA1 Message Date
Marc Jones
938ae3ed18 Clean up AMD romstage.c serial output
This cleans up the strings in romstage.c, removing the ugly "got past".
Also, cleaned up comments and some spacing.

Change-Id: I0124df76eb442f8a0009a31a8632e4fd67ed7782
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/539
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-01-18 23:09:17 +01:00
Marc Jones
c9ea327a45 Clean up AMD romstage.c whitespace indent issues
Change-Id: I1713f1a3b548cb8e8ea5cf57eef95486ceb05ab9
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/538
Tested-by: build bot (Jenkins)
Reviewed-by: Vikram Narayanan <vikram186@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-01-18 20:08:49 +01:00
Kyösti Mälkki
2a830d0b98 Change AMD vendorcode build
Apply the normal method of recursively including subdirectories
for src/vendorcode. Remove redundant references under
mainboard and northbridge.

Change-Id: I914a6e262ed2abe83f407df36fe5c1af5eb4bcb0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/468
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-02 08:59:26 +01:00
Stefan Reinauer
5ff7c13e85 remove trailing whitespace
Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/364
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-01 19:07:45 +01:00
Patrick Georgi
914377efd6 Get rid of the old romstage-as-bootblock ROM layout
This change removes CONFIG_TINY_BOOTBLOCK, CONFIG_BIG_BOOTBLOCK, and
all their uses, assuming TINY_BOOTBLOCK=y, BIG_BOOTBLOCK=n.

This might break a couple of boards on runtime, but so far, fixes were
quite simple.
There's a flag day: Code that relies on CONFIG_TINY_BOOTBLOCK must be
adapted.

Change-Id: I1e17a4a1b9c9adb8b43ca4db8aed5a6d44d645f5
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/320
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-10-28 22:17:36 +02:00
Patrick Georgi
b0a9c5ccf3 mptable: Refactor mptable generation some more
The last couple of lines of every mptable function were mostly
identical. Refactor into common code, a new function mptable_finalize.

Coccinelle script:
  @@
  identifier mc;
  @@
  (
  -mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
  -mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
  -printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
  -return smp_next_mpe_entry(mc);
  +return mptable_finalize(mc);
  |
  -mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
  -mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
  -return smp_next_mpe_entry(mc);
  +return mptable_finalize(mc);
  )

Change-Id: Ib2270d800bdd486c5eb49b328544d36bd2298c9e
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/246
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13 01:11:08 +02:00
Patrick Georgi
c75c79bd02 mptable: Get rid of fixup_virtual_wire
As stated in some code files, fixup_virtual_wire was established
to avoid touching 200 invocations of the mptable code.

Let Coccinelle do it:
  @@
  type T;
  identifier v;
  @@
  -void fixup_virtual_wire(T v)
  -{ ... }

  @@
  expression A;
  identifier v;
  @@
  -v = smp_write_floating_table(A);
  +v = smp_write_floating_table(A, 0);

  @@
  expression A;
  identifier v;
  @@
  -v = smp_write_floating_table(A, 0);
  -fixup_virtual_wire(v);
  +v = smp_write_floating_table(A, 1);

Change-Id: Icad8a063380bf4726be7cebb414d13b574112b14
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/245
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-13 01:10:44 +02:00
efdesign98
2c66060169 AMD Torpedo platform updates
This update fixes warnings and supports as necessary
the Agesa infrastructure changes required to support
the AMD Family 14 cpu update to rev C0.

Change-Id: Ib08b49695b925b81f796bf299141fe6f845fdef8
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/138
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-15 17:30:07 +02:00
Kerry She
feed329a0c AMD F14 southbridge update
This change adds the southbridge related code to support
the update of the AMD Family14 cpus to the rec C0 level.
Some of the changes reside in mainboard folders but they
reference changed files in the southbridge folder so they
are included herein.

Change-Id: Ib7786f9f697eaf0bf8abd9140c4dd0c42927ec7e
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/135
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-07 01:08:57 +02:00
efdesign98
3ddb6b85f1 Add xhcbios and ahcibios rom handling
This change adds xhci and ahci bios rom handling that
is similar to the vgabios rom handling in the arch/x86
Makefile.inc to the Persimmon and Torpedo mainboards.
It also adds the basis for AHCI BIOS rom handling to
the Persimmon Kconfig.

Change-Id: I527a906323ae483cfa2ca0785f3adb43e88fd84b
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/109
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-22 20:02:22 +02:00
efdesign98
770b877796 Add the AMD Torpedo mainboard
The Torpedo mainboard is the reference platform for
the AMD Family 12 cpus and the AMD Hudson-2 (SB900)
southbridge.

Change-Id: Ifbf82fc4e4375a108a9d6068876b8ff612cfa8e1
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/54
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-28 23:09:37 +02:00