Commit Graph

4871 Commits

Author SHA1 Message Date
Arthur Heymans 1cffc55d35 util/amdfwutil: Fix adding microcode binaries
Change-Id: I726df4ff97688f4c48961e6e61672cef6c3b7aff
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-10-21 21:40:08 +00:00
Martin Roth 95b5b025a0 util/lint: Fix linting outside of git repos
If the coreboot code is not in a git repository, the linters switch
from using `git ls-files` to find.  This requires some changes to
prevent the linters from looking at the wrong files which are
automatically excluded by git.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I81d138760c29a7c476280bb9d963f6be99c75d6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-10-21 14:30:42 +00:00
Hsuan Ting Chen fec16a3574 util/elogtool: Add support for parsing CrOS diagnostics log
Remove the "_DEPRECATED_" tag from ChromeOS diagnostics event and add a
subtype: "ELOG_CROS_DIAGNOSTICS_LOGS" under it.

The data of "ELOG_CROS_DIAGNOSTICS_LOGS" (0x02) contains:
* An uint8_t of subtype code
* Any number of "ChromeOS diagnostics logs" events

Each "ChromeOS diagnostics log" represents the result of one ChromeOS
diagnostics test run. It is stored within an uint8_t raw[3]:
 * [23:19] = ELOG_CROS_DIAG_TYPE_*
 * [18:16] = ELOG_CROS_DIAG_RESULT_*
 * [15:0]  = Running time in seconds

Also add support for parsing this event. The parser will first calculate
the number of runs it contains, and try to parse the result one by one.

BUG=b:226551117
TEST=Build and boot google/tomato to OS,
localhost ~ # elogtool list
0 | 2022-09-26 04:25:32 | Log area cleared | 186
1 | 2022-09-26 04:25:50 | System boot | 0
2 | 2022-09-26 04:25:50 | Firmware vboot info | boot_mode=Manual recovery
  | recovery_reason=0x2/0 (Recovery button pressed)
  | fw_tried=A | fw_try_count=0 | fw_prev_tried=A
  | fw_prev_result=Unknown
3 | 2022-09-26 04:25:50 | EC Event | Keyboard Recovery
4 | 2022-09-26 04:26:01 | Memory Cache Update | Normal | Success
5 | 2022-09-26 04:26:06 | System boot | 0
6 | 2022-09-26 04:26:07 | Firmware vboot info | boot_mode=Diagnostic
  | fw_tried=A | fw_try_count=0 | fw_prev_tried=A
  | fw_prev_result=Unknown
7 | 2022-09-26 04:26:07 | Diagnostics Mode | Diagnostics Logs
  | type=Memory check (quick), result=Aborted, time=0m0s
  | type=Memory check (full), result=Aborted, time=0m0s
  | type=Storage self-test (extended), result=Aborted, time=0m1s

Change-Id: I02428cd21be2ed797eb7aab45f1ef1d782a9c047
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-10-14 16:06:39 +00:00
Fred Reitberger 9049dfdb68 util/cbfstool: Wrap logging macros in do - while
Wrap the console logging macros with do { ... } while (0) so they act
more like functions.

Add missing semicolons to calls of these macros.

TEST=compile only

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I721a4a93636201fa2394ec62cbe4e743cd3ad9d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-10-13 17:07:02 +00:00
Michał Żygowski b33ee1da7d util/superiotool/nuvoton.c: Add NCT6687D-W register definitions
Based on public NCT6686D hardware datasheet revision 0.5 which should
be similar to NCT6687D.

TEST=Dump NCT6687D, GPIO and EC registers on MSI PRO Z690-A WIFI DDR4

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I38db1de0f3d3b6de14bcb758afc9804c072c1895
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2022-10-12 09:07:21 +00:00
Arthur Heymans ee0f5d794d util/amdfwread: Fix cookie error message
Change-Id: I580675fcbf8c5058ade371c6b9edb7b7070a78a3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-10-11 14:45:09 +00:00
Arthur Heymans aafbe136a9 util/amdfwutil: Order enum and use hex consistently
This makes it easier to match the code to the datasheet (55758, NDA
only).

This also removes the duplicate lines:
"{ .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 1, .level = PSP_BOTH |
PSP_LVL2_AB },
{ .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH |
PSP_LVL2_AB },"

TESTED: google/vilboz still boots.

Change-Id: I1c959a0fbbf16cc65be34b79f68ec7f92fd4368f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marvin Drees <marvin.drees@9elements.com>
Reviewed-by: ritul guru <ritul.bits@gmail.com>
2022-10-11 14:44:31 +00:00
Fred Reitberger 7e9801171e util/amdfwtool: Add Mendocino to usage
Add missing Mendocino soc to usage print.

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I8b995fccc23dcca87d45cc13fbb1ebbc1f0e2add
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68226
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-10 21:50:44 +00:00
Martin Roth 134908381f util/amdfwtool: Add preliminary code for morgana & glinda SOCs
This allows amdfwtool to recognize the names for the upcoming morgana
and glinda SoCs.  It does not yet do anything for those SoCs, but this
allows the morgana SoC to build.

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I766ce4a5863c55cbc4bef074ac5219b498c48c7f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68193
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-10 21:45:07 +00:00
Fred Reitberger 743c1c0894 util/lint/lint-stable-003-whitespace: Fix shell variable name
Fix shell variable "LINTDIR" so that helper_functions.sh can be found.

TEST=`./util/lint/lint lint-stable --junit` no longer prints "cannot
open /helper_functions.sh: No such file"

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I68f2e65fa1c9297ad6b58b77576deaeef8bd76e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-10-10 21:43:47 +00:00
Angel Pons f007ab7b43 util/inteltool: Add support for (non-ULT) Broadwell
Add support for traditional (non-ULT) Broadwell.

Change-Id: Ibe0ed9badd580e28060fe8df14a01352d4c1e11e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-10-08 21:04:43 +00:00
Angel Pons aa4cd73409 util/inteltool: Add 9 series PCH support
Add the PCI device IDs for 9 series PCHs.

Change-Id: Id216cd071b09c93ee6a4792944c6fad39254aa3b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-10-08 21:03:58 +00:00
Sean Rhodes 3c3516b874 util/coreboot-configurator: Update the README
Update the README with new instructions for Debian 11 and MX Linux.

Also add the build dependencies.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I6942b9532e8d82f7fc5d6455c96913bcba6e983e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-10-07 22:06:06 +00:00
Kacper Stojek fb9110b9e4 util/inteltool: Add support for Alderlake P in inteltool
TEST=Dump registers on Clevo NS70PU with Intel® Core™ i7-1260P

Document number: 626817, 630094, 655258

Change-Id: I2ba4ef7eee33d4dd762a05dd755de5e4d2e566dd
Signed-off-by: Kacper Stojek <kacper.stojek@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66825
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-07 21:18:22 +00:00
Kangheui Won 5b84dfd1c1 util/amdfwtool: Generate hashes for signed AMDFW components
Generate SHA256/SHA384 hash of the signed firmware so that PSP verstage
can pass it to PSP. The PSP will use these hashes to verify the
integrity of those signed firmwares.

BUG=b:203597980
TEST=Build Skyrim BIOS image.

Change-Id: I50d278536ba1eac754eb8a39c4c2e428a2371c44
Signed-off-by: Kangheui Won <khwon@chromium.org>
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60290
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-02 22:13:38 +00:00
Kangheui Won 3c164e13e7 util/amdfwtool: Add options to separate signed firmwares
Add support for separating signed firmwares into another CBFS. If
sig_opt flag in AMD/PSPFW file header is 1, it means that the firmware
is signed against AMD chain of trust and will be verified by PSP. If
those firmware binaries are put outside FW_MAIN_[AB], vboot can skip
redundant verification, improving overall verification time.

BUG=b:206909680
TEST=Build amdfwtool. Build Skyrim BIOS image and boot to OS.

Change-Id: I9f3610a7002b2a9c70946b083b0b3be6934200b0
Signed-off-by: Kangheui Won <khwon@chromium.org>
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59866
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-02 22:11:13 +00:00
Karthikeyan Ramasubramanian 236245ec7d util/amdfwtool: Include the header with __packed definition
Checkpatch script recommends to use __packed instead of
__attribute__((packed)). Currently the build rule for amdfwtool does not
include the required header file with __packed definition. Update the
compiler flag to include the required header file.

BUG=None
TEST=Build amdfwtool.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I448cbad533608dd5c2bd4f2d827fcc5db5dee5cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67384
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-02 22:09:01 +00:00
Tom Hiller 520c8c070b util/docker/coreboot-sdk: add graphicsmagick-imagemagick-compat
edkII requires ImageMagick's `convert` to compile.  The
`graphicsmagick-imagemagick-compat` package provides `convert` without
the full ImageMagick library.

Change-Id: I8fc01526842eb408b0015c0652043c20f826a015
Signed-off-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-10-02 22:07:56 +00:00
Martin Roth d81debd946 util/lint: Update tools that use git to use a library
Each of the tools that used git had similar functionality. This combines
all of that into a single script that gets sourced by each.  This makes
maintenance much easier.

By doing this and updating each of the scripts to do the correct thing
if the script isn't being run in a git repository, it makes them work
much better for the releases, which are just released as a tarball,
without any attached git repository.

Change-Id: I61ba1cc4f7205e0d4baf993588bbc774120405cb
Signed-off-by: Martin Roth <martin@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-30 19:19:53 +00:00
Martin Roth 7726a7f272 util/lint: Update spelling.txt, add makefile to sort it
- Update spelling.txt with Lintian changes
- Remove words that are going to mess up code
- Add comments to the header about what words should be removed, along
with where the files
- Add Makefile to sort the list

Note that this undoes some of the sorting that Patrick introduced in
commit CB:38632 - ID: 805b291830
I just cannot reproduce his sort order, even using the script he put
into the commit message.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic131d5b08409f43eb700dcc8f125af00cff53d71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64893
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-30 19:07:02 +00:00
Felix Held 3dfb485334 util/amdfwtool/data_parse: fix PMU subprogram/instance ID handling
The parsing of the PMU binary subprogram and instance numbers only
worked correctly for the cases where the ID in the name in the fw.cfg
file was between 0 and 9, but returned wrong results if it was between a
and f. Switch to using strtol with a base of 16 instead of subtracting
the char '0' from the char in the filename in
find_register_fw_filename_bios_dir to fix this.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic5fd41daf9f26d11c1f86375387c1d7beac04124
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-09-30 18:03:50 +00:00
Robert Zieba de6ecd0101 util/spd_tools: Change Mendocino to use 0x13 for LP5x memory type
Mendocino supports LP5x but currently doesn't support SPDs that use the
LP5x memory type, 0x15. This commit updates set 1 SPDs, which are
currently only used for mendocino, to use 0x13 for their memory type.

BUG=b:245509394
TEST=Generated SPDs, verified that only set 1 have changed to 0x13

Change-Id: I46606cb5ff871296d0214e1f781c3b22e93d24ea
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67747
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-09-29 17:12:00 +00:00
Denis 'GNUtoo' Carikli b82486496d intelmetool: Add PCI ID for Bay Trail
Tested on a Dell Venue 8 Pro tablet

Change-Id: Ic8f162ea82b910082af4b4e05fa1408fd24f2c88
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@cyberdimension.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-28 18:22:27 +00:00
Ritul Guru a2cb3400a6 util/amdfwtool: Add support for PSP NVRAM base addr and size
Add parameters to support adding the location and size of
the PSP NVRAM area to the PSP directory table.

Verified this change on PCO based Bilby platform.
Change-Id: I1664893db6f6dcdc588aeaf9448c2d81390af5fa
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67137
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-22 17:10:46 +00:00
Sean Rhodes 3c43301185 util/coreboot-configurator: Update legacy_8254_timer description
The help text and label for legacy_8254_timer is inverted, so update
this so that it is correct.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I866a15886d1cfd2b77094742787dee7a36a54e85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65348
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-22 15:13:22 +00:00
Sean Rhodes 914f50552f util/coreboot-configurator: Add RPM spec file
Add RPM spec to allow building RPMs, for both coreboot-configurator
and nvramtool, for Fedora.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I80a77d0f2246409c06e22abb229d63c4611a9fb5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65346
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-22 15:13:07 +00:00
Sean Rhodes ed0c7f53eb util/coreboot-configurator: Update Debian dependancies
Change the control file to allow either libyaml-cpp0.6 or
libyaml-cpp0.7.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I754d3e2018ab78fcb657d313c8662313738b190a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2022-09-22 15:12:59 +00:00
Jakub Czapiga a0e36d8cba tests: Add support for tests build failures detection
This patch introduces new target: junit.xml-unit-tests, which builds and
runs unit-tests. It also creates build log containing build logs. This
feature allows for one to see build failures in Jenkins dashboard.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I94184379dcc2ac10f1a47f4a9d205cacbeb640fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67372
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-21 14:06:42 +00:00
Elyes Haouas c8870b1334 crossgcc: Upgrade llvm from version 14.0.6 to 15.0.0
Test build for QEMU x86 i440fx/piix4.

Change-Id: I3144a83fcbd92eec51d70e9be33ff2fcb2821731
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67416
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-18 17:14:10 +00:00
Elyes Haouas 035e9f9f0c crossgcc: Upgrade cmake from 3.23.2 to 3.24.2
Change-Id: I81a8371190513ca34d3c5efb0e3770ac3d873b03
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-09-18 17:14:04 +00:00
Yidi Lin 0811a6492d cbmem: use aligned_memcpy for reading lb_cbmem_entry information
The lbtable contains the memory entries that have fields unnaturally
aligned in memory. Therefore, we need to perform an aligned_memcpy() to
fix the issues with platforms that don't allow unaligned accesses.

BUG=b:246887035
TEST=cbmem -l; cbmem -r ${CBMEM ID}

Change-Id: Id94e3d65118083a081fc060a6938836f6176ab54
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-09-18 03:24:16 +00:00
Patrick Georgi f0d5f67e46 riscv: Enable the newfangled way of selecting instruction sets
gcc12+ will require riscv architecture selection to come not only with
featurei suffixd charactersa, it also comes with feature_ful suffix_ed
words_mith. Much creative, very appreciate.

To accommodate for this madness, enable the already existing (but off by
default) support for that in our gcc11 build, support using by detecting
the compiler's behavior in xcompile and pass that knowledge along to our
build system.

Then cross our fingers and hope for the best!

Change-Id: I5dfeed766626e78d4f8378d9d857b7a4d61510fd
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-17 05:56:34 +00:00
Elyes Haouas 3541c31add util/kconfig/regex.c: Remove leftover
coreboot doesn't support the MIPS architecture anymore.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I404d034949a7786d7971117081537baf27ff2e22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-09-16 14:52:44 +00:00
Elyes Haouas a3c287d7a3 crossgcc [binutils]: Remove 'enable-plugins' option
unneeded 'enable-plugins' option sneaked in..., so remove it.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Id1d7f2c7e6b70c28e1060c6ee915363ffe412ef6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-09-16 13:06:22 +00:00
Elyes Haouas b8e5baf2f2 crossgcc [binutils]: Remove invalid enable-interwork option
'enable-interwork' is not a binutils configure option.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I29cd6137c700ff6871868a723daf33909aa218ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65609
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-09-16 13:05:44 +00:00
Nico Huber c0fc38eed8 sconfig: Allow to specify device operations
Currently we only have runtime mechanisms to assign device operations to
a node in our devicetree (with one exception: the root device). The most
common method is to map PCI IDs to the device operations with a `struct
pci_driver`. Another accustomed way is to let a chip driver assign them.

For very common drivers, e.g. those in soc/intel/common/blocks/, the PCI
ID lists grew very large and are incredibly error-prone. Often, IDs are
missing and sometimes IDs are added almost mechanically without checking
the code for compatibility. Maintaining these lists in a central place
also reduces flexibility.

Now, for onboard devices it is actually unnecessary to assign the device
operations at runtime. We already know exactly what operations should be
assigned. And since we are using chipset devicetrees, we have a perfect
place to put that information.

This patch adds a simple mechanism to `sconfig`. It allows us to speci-
fy operations per device, e.g.

  device pci 00.0 alias system_agent on
          ops system_agent_ops
  end

The operations are given as a C identifier. In this example, we simply
assume that a global `struct device_operations system_agent_ops` exists.

Change-Id: I2833d2f2450fde3206c33393f58b86fd4280b566
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-15 13:06:47 +00:00
Jeremy Compostella e1465e2157 util/ifittool: Error out if microcodes do not fit the FIT table
parse_microcode_blob() returns success when it reaches max_fit_entries
microcode. It makes the FIT table size verification in
fit_add_microcode_file() useless. This patch makes
parse_microcode_blob() error out if max_fit_entries is reached.

Note that this size verification is critical as a FIT table only
partially listing the microcode patches can lead to boot failures as
recently observed on Raptor Lake-P.

BRANCH=firmware-brya-14505.B
BUG=b:245380705
TEST=compilation errors out when trying to stitch more than
     CONFIG_CPU_INTEL_NUM_FIT_ENTRIES microcode patches.

Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: Id9c5fb6c1e264f3f5137d29201b9021c72d78fde
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67454
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
2022-09-15 13:01:42 +00:00
Matt DeVillier 275a9a3d7e util/lint: Add a check for touchpads using the "probed" flag
As of commit 2cf52d80a6 ("mb/*/{device,override}tree: Set touchpads to
use detect (vs probed) flag") all touchpads in the tree have been
switched from using the 'probed' flag to 'detect.' Add a lint check to
ensure no touchpads are added with the probed flag.

TEST=manually change one touchpad to use 'probed' flag and ensure lint
check catches it.

Change-Id: Ie0aee2e3778fc56c6c21c97995738a147a1fa0d4
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67486
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-09-14 20:52:02 +00:00
Elyes Haouas 8de4d27810 crossgcc: binutils: Remove invalid enable-multilibs option
Looks like somewhere after the original implementation it was renamed to
--enable-multilib without the s.
'enable-multilibs' is not a valid option for binutils.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I105cc9fa489aed24905dedb785c70bc69ed18970
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65608
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-09-14 17:13:02 +00:00
Maxim Polyakov 593b0f1f23 intelp2m: Add Go Managing Dependencies System support
Add go.mod containing the full name of the project according to the
docs [1]: review.coreboot.org/coreboot.git/util/intelp2m, and also,
based on this, rename the internal packages to point to the absolute
path. This will allow Go Managing Dependencies System to integrate
packages from intelp2m to third-party Go written on the Go language [1].
This also requires fixing the Golang compiler version in go.mod: use
go1.18 [2], the latest up-to-date version.

[1] https://web.archive.org/web/20220910100342/https://go.dev/doc/modules/managing-dependencies
[2] https://web.archive.org/web/20220910100206/https://tip.golang.org/doc/go1.18

[ TEST ]
1) Import the coreboot project into some go project:

$cd path/to/go-project
$go get review.coreboot.org/coreboot.git
go: downloading review.coreboot.org/coreboot.git v0.0.0-20220903004133
-39914a50ae16
go: added review.coreboot.org/coreboot.git v0.0.0-20220903004133
-39914a50ae16

Thus, 'go get' correctly downloaded the contents of the repository.

2) Import intelp2m:

$cd path/to/go-project
$go get review.coreboot.org/coreboot.git/util/intelp2m
review.coreboot.org/coreboot.git/util/intelp2m imports
	./config: "./config" is relative, but relative import paths are
not supported in module mode
review.coreboot.org/coreboot.git/util/intelp2m imports
	./parser: "./parser" is relative, but relative import paths are
not supported in module mode

Thus, the problem is in the package names, but after this patch, the
import should be without errors.

3) Import a repository with an incorrect url:

$cd path/to/go-project
$go get review.coreboot.org/coreboot/test
go: unrecognized import path "review.coreboot.org/coreboot/test":
reading https://review.coreboot.org/coreboot/test?go-get=1:
404 Not Found

This has not happened in previous cases.

Change-Id: I12efae31227129b8c884af10fb233f398c4094e7
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2022-09-12 12:55:05 +00:00
Jeremy Compostella 46ffccd753 util/ifittool: Fix buffer overflow with padded microcode patches
Some microcode patches are padded with zeros, which make
parse_microcode_blob() read beyond the end of the buffer.

BRANCH=firmware-brya-14505.B
BUG=b:245380705
TEST=No segmentation fault with a padded microcode patch

Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: Id9c5fb6c1e264f3f5137d29201b9021c72d78fdd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67460
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-09-12 12:33:36 +00:00
Martin Roth 38bbff47a7 util/lint/lint: Add -I option to invert test results
To test the linters, we want to invert the results so that any test that
passes shows up as a failure. This will allow us to verify that all of
the linters are working correctly.

This will be tested nightly as well as on changes to the lint tools.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ia8024c6ab0c91fd9f630f37dc802ed3bc6b4608c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-09-07 22:35:02 +00:00
Caveh Jalali c762e231da util/spd_tools: Update LP5X support for ADL/RPL/MTL
This updates the SPD utility and generated SPDs for LP5X to use memory
type code 0x15 (LPDDR5X) instead of 0x13 (LPDDR5). This is done based on
Intel Tech Advisory Doc ID #616599 dated May 2022, page 15.

SPDs were regenerated with:
  "util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5"

This only affects the SPDs for 2 memory parts for Intel SoCs and the
only board referencing these is rex.

BUG=b:242765117
TEST=inspected SPD hex dump

Change-Id: Iadb4688f1cb4265dab1dc7c242f0c301d5498b83
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-09-07 22:19:21 +00:00
Elyes Haouas 0d42db666b lint/checkpatch: Fix incorrect camelcase detection on numeric constant
This reduce the difference with linux v6.0-rc3.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I15e1a935665c38b8a2109d412b1d16f935cbb402
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-09-06 17:59:55 +00:00
Martin Roth f6ba75c736 util/lint/lint-stable-019-header-files: add test
Add a test to make sure that the linter fails correctly.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I971951d4248dd10abe4c622025fdaf86e014c6cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-06 17:58:57 +00:00
Martin Roth cd9110b6d2 util/lint: Add rules.h & compiler.h to 019-header-files linter
The rules.h & compiler.h includes were removed in previous commits, so
add the checks to keep them out to the linter.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If4964ff26f5e83abbbdd26c2b1cd9a2eab5a0a0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-06 17:58:31 +00:00
Martin Roth 8a3f5a1d0b util/lint: ignore util/goswid, a new submodule
git submodules should be ignored when parsing the coreboot tree for
lint errors. Those should be handled in their own commit checks.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I62b58f0c536312fe4677855bca8f44bc7d3ebc85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-05 19:38:12 +00:00
Karthikeyan Ramasubramanian 0dd3cf4534 util/amdfwtool/amdfwread: Fix incorrect option index
index I/O argument to getopt_long is not the index to argv. Instead it
is an index into the optlong array corresponding to the parsed option.
Also getopt() uses a global variable optind to track the index of the
next argument to be processed. Use the optindex variable as an index to
extract the filename from argv.

BUG=None
TEST=Build and use amdfwread to read the Soft-fuse bits from Guybrush
BIOS image. Observed no changes before and after the changes.

Change-Id: I33c74a0c8e12c5af76954524cf7294b7541d286b
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66553
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-04 17:06:21 +00:00
Caveh Jalali 7dd42da9a0 util/spd_tools: Rebuild utils when source changes
This adds source file dependencies to utilities so that they are rebuilt
when the source is changed. Previously, binaries were only built if they
did not already exist and never rebuilt to reflect source file changes.

BUG=none
TEST=verified binaries are rebuilt when source files are touched.

Change-Id: I4775fe0e00e0f5d4f8b4b47331d836aba53c0e69
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-09-04 16:57:33 +00:00
Martin Roth d12e4f5088 util/lint: Add lint tests to make sure they fail correctly
Change-Id: I1ff3302acdd5bc5d17a5d394d953b6877750b6a6
Signed-off-by: Martin Roth <martin@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-09-04 16:43:50 +00:00
Martin Roth 8b45c1244e util/lint/lint: Reformat usage
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I684d374bd02a42e178383c26936e137e173f8f7e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-09-03 23:50:15 +00:00
Martin Roth 8ea8d856f3 util/lint/lint: Add command line parsing
The lint script just did very basic argument parsing and required the
sub-command and --junit argument to be in specific locations.  I'm
adding additional commands, so the first step is to add true command
line parsing.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I7118c29e6c5d785b35a7ae12cf5984c43ebc3ab9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67191
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-03 23:49:53 +00:00
Julius Werner d96ca24652 cbfs/vboot: Adapt to new vb2_digest API
CL:3825558 changes all vb2_digest and vb2_hash functions to take a new
hwcrypto_allowed argument, to potentially let them try to call the
vb2ex_hwcrypto API for hash calculation. This change will open hardware
crypto acceleration up to all hash calculations in coreboot (most
notably CBFS verification). As part of this change, the
vb2_digest_buffer() function has been removed, so replace existing
instances in coreboot with the newer vb2_hash_calculate() API.

Due to the circular dependency of these changes with vboot, this patch
also needs to update the vboot submodule:

Updating from commit id 18cb85b5:
    2load_kernel.c: Expose load kernel as vb2_api

to commit id b827ddb9:
    tests: Ensure auxfw sync runs after EC sync

This brings in 15 new commits.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I287d8dac3c49ad7ea3e18a015874ce8d610ec67e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2022-09-02 23:51:29 +00:00
Felix Singer b45b48de73 util/docker/coreboot-jenkins-node: Install cmocka
flashrom uses cmocka for unit testing. Install it so that the CI can
use it.

Change-Id: I5c168e480d6f4cbfbbd175ecb035c88bfcbac00b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67272
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-02 18:48:13 +00:00
EricKY Cheng 20f092d339 util/spd_tools: Add AMD Mendocino (MDN) platform
This patch adds support for MDN platform to the spd_tools.
This change replaces SBR with MDN.

BUG=b:243337816
TEST=Able to generate SPD for LP5 DRAM part.

Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: If099af36de8a64e96fbfde32eaf15990f4b330c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
2022-08-30 14:53:05 +00:00
Zheng Bao c88f2b5be7 amdfwtool: Fix indentation
Change-Id: I4c57c9bade318d54315f9692cd37edb694e33aa9
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58320
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-29 22:52:59 +00:00
Martin Roth 2dd74906e4 util/futility: Ignore deprecated declarations in OpenSSL 3.0
Building futility with OpenSSL 3.0 (default in latest Debian sid)
results in a number of warnings that various declarations have been
deprecated.  Since we (and futility) have warnings as errors enabled,
this causes the building of futility to fail, killing the entire
coreboot build.

To work around this until futility is updated, turn off the warnings
about deprecated declarations.

Bug 243994708 has been filed to get futility updated.  This workaround
can be removed when futility builds cleanly with the latest libsssl-dev.

BUG=b:243994708
TEST=Futility build doesn't fail with libssl-dev > 3.0

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I54e27e09b0d50530709864672afe35c59c76f06e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tom Hiller <thrilleratplay@gmail.com>
2022-08-29 18:34:18 +00:00
Felix Singer feab41b030 util/docker/coreboot-sdk: Install GNAT 12
For some reason GNAT 11 is not able to build GNAT 12, since there are
some Ada errors during the compilation. However, it works with GNAT 12.
So use GNAT 12 for the host toolchain instead.

Change-Id: If00a05a0c8564e624809268a12fae28261e380a2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-08-27 16:01:52 +00:00
Felix Singer acbdc4d72e util/docker/coreboot-sdk: Replace package qemu with qemu-system
The qemu package doesn't exist anymore or it was renamed. Instead of
installing QEMU for all available architectures, install only the
packages which ship architectures that are supported by coreboot.

  * qemu-system-arm
  * qemu-system-misc (for RISC-V)
  * qemu-system-ppc
  * qemu-system-x86

Change-Id: Ifc46a8c9fcb1ab3c38dc8cbbc906882e93a719d7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-27 16:01:12 +00:00
Tom Hiller a0eb855ef4 util/docker/coreboot-sdk: Remove doxygen
Doxygen was removed at the project level.  Remove the doxygen Debian
package and make target.

Change-Id: Ib82ba7890e7f53357eeca318b5f844164747aecd
Signed-off-by: Tom Hiller <thrilleratplay@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67039
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-27 15:50:50 +00:00
Ritul Guru 9a321f31c8 util/amdfwtool: Add changes to reserve BIOS SIG
changes to reserve space for AMD_BIOS_SIG when
BIOS image is signed with RTMSignature.

Change-Id: Ia832fe83a3e29279c029fefc934c3ef4d335e2ea
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-26 16:04:51 +00:00
Robert Zieba 65fe21f1c9 util/apcb/apcb_v3_edit: Add support for LP5X SDRAM
This commit adds support for LP5X SDRAM.

BUG=b:242765117
TEST=Ran with LP5X SPDs and manually patched APCB

Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I2d3cb9c9a1523cb4c5149ede1c96a16c3991a5d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66840
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-25 00:49:52 +00:00
Robert Zieba c4d77128c5 util/spd_tools: Add support for LP5X SPDs
This commit adds support for LP5X SPDs. The SPD format is identical to
LP5 except that the memory type is set to 0x15 instead of 0x13. Since
they are essentially the same, LP5/5X parts share the same parts JSON
file and SPD directory. LP5X parts are distinguished by the optional
`lp5x` attribute. This commit also updates two existing LP5X memory
parts with the correct attribute.

BUG=b:242765117
TEST=Generated SPDs, verified that SPDs generated from LP5X parts match
their LP5 counterparts except for memory type byte.

Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I67df22bc3fd8ea45fe4dad16b8579351eb4d0d8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-08-25 00:48:46 +00:00
Felix Singer bbe0a99d66 lint-000-license-headers: Add src/sbom/TAGS to exception list
Commit 6dac0c54cd makes the linter checking for license headers on all
files from the src directory. Since this TAGS file doesn't have one,
it's causing a linter error and it makes the QA system complain.
However, the TAGS file doesn't need a license header and thus add it to
the exception list.

Usually the build tests detect such issues, but commit 1d7a9debf2,
which introduced that file, was merged independently from the other
commit, which modifies the linter. Also, the patch that is introducing
this file was based on an older commit at which the patch modifying the
linter wasn't merged yet and so this issue was hidden.

Change-Id: I78da3fa70c39b709478a384da8769fc058ca18ce
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66938
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-22 20:51:32 +00:00
Felix Singer 88ffed3df8 util/crossgcc: Remove binutils related MIPS patch
coreboot doesn't support the MIPS architecture anymore. So remove the
MIPS patch.

Change-Id: I62a2bca141b42ac33b628c48c84422570f4dda10
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-08-22 16:18:35 +00:00
Maximilian Brune 1d7a9debf2 Add SBOM (Software Bill of Materials) Generation
Firmware is typically delivered as one large binary image that gets
flashed. Since this final image consists of binaries and data from
a vast number of different people and companies, it's hard to
determine what all the small parts included in it are. The goal of
the software bill of materials (SBOM) is to take a firmware image
and make it easy to find out what it consists of and where those
pieces came from. Basically, this answers the question, who supplied
the code that's running on my system right now? For example, buyers
of a system can use an SBOM to perform an automated vulnerability
check or license analysis, both of which can be used to evaluate
risk in a product. Furthermore, one can quickly check to see if the
firmware is subject to a new vulnerability included in one of the
software parts (with the specified version) of the firmware.
Further reference:
https://web.archive.org/web/20220310104905/https://blogs.gnome.org/hughsie/2022/03/10/firmware-software-bill-of-materials/

- Add Makefile.inc to generate and build coswid tags
- Add templates for most payloads, coreboot, intel-microcode,
  amd-microcode. intel FSP-S/M/T, EC, BIOS_ACM, SINIT_ACM,
  intel ME and compiler (gcc,clang,other)
- Add Kconfig entries to optionally supply a path to CoSWID tags
  instead of using the default CoSWID tags
- Add CBFS entry called SBOM to each build via Makefile.inc
- Add goswid utility tool to generate SBOM data

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Icb7481d4903f95d200eddbfed7728fbec51819d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-08-22 14:48:46 +00:00
Felix Singer 61b90b173d util/nixshell/toolchain: Update GNAT to version 12
Change-Id: I308dc7640e16b7cfb7679d81099d8896f3f454fc
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-08-18 17:03:10 +00:00
Martin Roth 957fde633b util/lint: Check files of all sizes for licenses
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Ib97d009c056b487136f20e5341b31183c65ef761
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-08-17 19:44:08 +00:00
Martin Roth 6dac0c54cd util/lint: Update to check all of src for license headers
This wasn't done previously because not all files in the
src directory had the correct headers.  Doing this earlier
would have broken the build.

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Ia6d7a7a17116e4c8e55354783085355fd45ff87a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66505
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2022-08-17 19:43:30 +00:00
Martin Roth eb80d8da88 util/release: Update genrelnotes with the latest version
This is the version of genrelnotes that was used to help with the
4.16 release.

- Fix shellcheck issues.
- Send messages for the user to STDERR.
- Add recent platforms
- Handle symbolic links to the git repo.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I2204793a5d1cc5792d0720d2bbfb172bb6020dd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-08-13 19:39:35 +00:00
Sean Rhodes 38c99b5659 payloads/tianocore: Rename TianoCore to edk2
coreboot uses TianoCore interchangeably with EDK II, and whilst the
meaning is generally clear, it's not the payload it uses. EDK II is
commonly written as edk2.

coreboot builds edk2 directly from the edk2 repository. Whilst it
can build some components from edk2-platforms, the target is still
edk2.

[1] tianocore.org - "Welcome to TianoCore, the community supporting"
[2] tianocore.org - "EDK II is a modern, feature-rich, cross-platform
firmware development environment for the UEFI and UEFI Platform
Initialization (PI) specifications."

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I4de125d92ae38ff8dfd0c4c06806c2d2921945ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65820
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-08-13 16:35:18 +00:00
Altamshali Hirani 8915abe115 amdfwtool/amdfwtool.h: Allow 16 additional PSP entries to be supported
Consolidate MAX_BIOS_ENTRIES and MAX_PSP_ENTRIES definitions into one
file

Signed-off-by: Altamshali Hirani <al.hirani@amd.corp-partner.google.com>
Change-Id: Ie3c64a1875010e7fb368967283df6baf1cc7ba8d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62911
Reviewed-by: ritul guru <ritul.bits@gmail.com>
Reviewed-by: Bao Zheng <fishbaozi@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-12 14:16:18 +00:00
Jon Murphy 05208b50c5 util/spd_tools: Rename Sabrina to Mendocino
'Mendocino' was an embargoed name and could previously not be used.
Update amdfwtool for consistency with the correct naming convention.

BUG=b:239072117
TEST=Builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I404fcf59e89b75cd2488bcb51981aee2eb4ff0df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66468
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-12 13:46:48 +00:00
Jon Murphy 9969f4b609 util/amdfwtool: Rename Sabrina to Mendocino
'Mendocino' was an embargoed name and could previously not be used.
Update amdfwtool for consistency with the correct naming convention.

BUG=b:239072117
TEST=Builds

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I673a9b99d207603b605756fc7d277c54c5d0f311
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66467
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-11 19:45:20 +00:00
Martin Roth 251e26683e util/lint: Add .gitignore files to list that don't need a license
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I568a357b40e8bb69b2b26752d241f06adfbe029e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2022-08-11 17:53:48 +00:00
Martin Roth f67a1aa76a util/lint & LICENSES: Add PDDC as a "license" for coreboot
The Creative Commons Public Domain Dedication and Certification is not
a license in the common sense in that it's stating that the associated
file is already in the public domain (having no copyright), and is not
actually putting it in the public domain like the CC-C0 license does.

The use for this in coreboot is for unlicensable files - either blank
files or files with no creative content.  This allows these files to
have the SPDX identifier to identify them as having no known copyright
for open source license compliance.

If CC-PDM-1.0 is ever included in the list of SPDX licenses, that would
probably fit better, but because the public domain mark isn't actually
a license, and because "public domain" isn't well defined, CC-PDM was
rejected as a SPDX identifier.

For further information:
https://web.archive.org/web/20201018194411/https://github.com/spdx/license-list-XML/issues/988

Change-Id: Ibb300ecd066cde2a016195c2beca76a460c588e3
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66496
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-08-10 19:07:20 +00:00
Martin Roth afa3e5aa49 util/lint & LICENSES: Add GCC-exception-3.1 to license exceptions
The gcov files in the lib directory are licensed GPL 3.0 with the GCC
runtime library exception.

Add this as a valid license so that the files can get a correct SPDX
identifier.

Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I1cf9c3125592741923c9b4481038055f24fe6ab1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-08-10 19:07:02 +00:00
Martin Roth 298b00776a utils: Add initial version of "remove_unused_code" script
This script creates a patch to remove all of the coreboot code that a
platform doesn't use.  This is useful for auditing the codebase for an
individual platform or releasing a platform's code.

Unlike the script that Sage used that did something similar, this keeps
the entire Kconfig tree (Though in a single file), all makefiles that
are required to build, and the standard build tools can still be used.
This will allow for much easier re-integration back into the coreboot
codebase if code is released after running this.

This is just the initial version and more features needed to be added to
make it fully functional.
- It should be able to build multiple configurations to retain the code
for all of those configurations.
- Flag to remove submodules files as well
- Additional variable flags to replace hardcoded values.
- The list of makefiles that need to be kept is pretty long, and could
be updated so that they aren't needed by the top level makefiles.
- Add flag to show changed files
- Show number of files before and after script is run

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Iec69db2ad1358846d649db627b6d60ac8c2204e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-08-09 19:22:31 +00:00
Karthikeyan Ramasubramanian e5af14ace6 util/amdfwtool: Fix ISH_B directory offset
On boards which use both PSP recovery A/B layout as well as VBOOT A/B
layout, ISH_B directory entry is pointing directly to PSP Level2
directory. This is not correct and either ISH_B should be marked as not
present or it should point to the ISH_A directory itself which in turn
point to PSP L2 directory. Fix it by choosing the latter option.

BUG=None
TEST=Build and boot to OS in Skyrim with PSP verstage.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I0a7a56e98de3f85669ff8ec2fcd1687aa33576a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-08-09 16:44:47 +00:00
Subrata Banik 151dcf49a6 util/elogtool: Mark redundant boot mode event type as `deprecated`
This patch adds `_DEPRECATED_` tag to ChromeOS boot mode related event
logging types as below:

* ELOG_TYPE_CROS_RECOVERY_MODE <---- to record recovery boot reason
                                     while booting into recovery mode
* ELOG_TYPE_CROS_DEVELOPER_MODE <--- if the platform is booted into
                                     developer mode.
* ELOG_TYPE_CROS_DIAGNOSTICS <---- if the platform is booted into
                                     diagnostic mode.

Drop static structure `cros_deprecated_recovery_reasons` as it has been
replaced by vb2_get_recovery_reason_string() function.

ELOG_TYPE_FW_BOOT_INFO event type is now used to record all those
related fw boot info along with ChromeOS boot mode/reason etc.

BUG=b:215615970
TEST=Build and boot google/kano to ChromeOS.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I932952ce32337e2d54473667ce17582a90882da8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-08-06 14:06:33 +00:00
Jakub Czapiga aa41563483 util/cbfstool: Fix truncate command error handling and cbfs_image_from_buffer()
Check return value of cbfs_truncate_space() in cbfs_truncate().
Remove return from cbfs_image_from_buffer() to inform about invalid
image region when incorrect offset header was provided.
Also change header offset provided to mentioned function in
cbfs_expand_to_region() and cbfs_truncate_space() from zero
to HEADER_OFFSET_UNKNOWN, as they do not support images with cbfs master
header.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ib009212692fb3594a826436df765860f54837154
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-08-03 23:24:49 +00:00
Subrata Banik 8b468400f1 util/cbfstool/elogtool: Support logging FW vboot info in elog
List of changes:
1. Add support for new elog event type to log vboot info (type 0xB7).
2. Add support string for fw_slot name, boot status and boot mode.
3. Print fw slot information like FW try count, FW current slot,
    previous FW slot, previous FW boot result and boot mode.

BUG=b:215615970
TEST=Able to build and boot google/kano to OS.
localhost # elogtool list
0 | 2022-07-01 11:10:27 | Log area cleared | 4088
1 | 2022-07-01 11:10:27 | Memory Cache Update | Normal | Success
2 | 2022-07-01 11:10:42 | System boot | 360
3 | 2022-07-01 11:10:42 | Power Fail
4 | 2022-07-01 11:10:42 | SUS Power Fail
5 | 2022-07-01 11:10:42 | ACPI Wake | S5
6 | 2022-07-01 11:10:42 | Wake Source | Power Button | 0
7 | 2022-07-01 11:10:42 | Chrome OS Developer Mode
8 | 2022-07-01 11:10:42 | Firmware vboot info |
                          boot_mode=Developer |
                          fw_tried=B | fw_try_count=0 |
                          fw_prev_tried=B | fw_prev_result=Unknown
9 | 2022-07-01 11:11:42 | System boot | 361
10 | 2022-07-01 11:11:42 | System Reset
11 | 2022-07-01 11:11:42 | Firmware vboot info |
			  boot_mode=Developer |
			  fw_tried=B | fw_try_count=0 |
			  fw_prev_tried=B | fw_prev_result=Success

localhost # crossystem recovery_request=1
localhost # elogtool list
41 | 2022-07-13 12:13:48 | Firmware vboot info |
			  boot_mode=Manual recovery boot |
		          recovery_reason: 0x1/0 (Recovery requested
			  from legacy utility) | fw_tried=A |
			  fw_try_count=0 | fw_prev_tried=A |
			  fw_prev_result=Unknown

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I48b5d54723683cef51e416fc6f58da000507fbcc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65562
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-02 07:06:52 +00:00
Karthikeyan Ramasubramanian 0b4f49c792 util/spd_tools/spd_gen/lp5: Remove maxSpeed for Sabrina
Firmware component that does memory training already limits the memory
controller to train at 5500 Mbps for all memory parts in Sabrina. Hence
removing this interim SPD change to limit the speed.

BUG=b:238074863
TEST=Build and boot to OS in Skyrim.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I2bc82c7407a97aac282708c3e0bd56ae99a8fc31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66290
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-01 20:30:39 +00:00
Karthikeyan Ramasubramanian 51f914d4a4 util/amdfwtool: Support PSP whitelist file on recovery A/B layout
This is required to enable PSP verstage on SoCs with recovery A/B
layout.

BUG=b:217414563
TEST=Ensure that the concerned type 0x3a PSP entry is present in PSP L2
directory. Build and boot to OS in Skyrim with both PSP and x86
verstage.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I5fae2b5dbcc95a99af3df9f59bb8516280ec1281
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-08-01 12:34:46 +00:00
Elyes Haouas ae157d38e3 crossgcc: Upgrade LLVM from 13.0.1 to 14.0.6
Test build for QEMU x86 i440fx/piix4.

Change-Id: I97d059947f7049b2491a98985795a4655891c3b3
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-07-30 18:27:30 +00:00
Felix Singer dca8583f17 util/liveiso/common: Install devmem2 and pcimem
devmem2 and pcimem are useful tools which allow working (reading and
writing) with memory mapped IO.

Change-Id: Ifda547b44af3c8e11cd4171a1dfbce3713455303
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66171
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-28 18:28:24 +00:00
Karthikeyan Ramasubramanian 234e37099a util/amdfwtool: Update the location of PSP verstage and signing key
On SoCs which use A/B recovery layout, PSP verstage and signing keys are
expected to be present only in PSP L2 directory. Update amdfwtool to
include the PSP verstage and signing key only in PSP L2 directory.

BUG=b:239519603, b:238938623
TEST=Build and boot to OS in Skyrim with PSP verstage.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ieeb415be800b7ccf10d6983eb0b567e0a5eaa955
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-07-26 20:36:04 +00:00
Patrick Georgi a284a36535 util/kconfig: Add README.md documenting the uprev procedure
Change-Id: I2e74f1c5cb1657e11d4f7ea101549329274102db
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-07-22 19:27:32 +00:00
Karthikeyan Ramasubramanian d5ea355c73 util/spd_tools: Limit memory speed to 5500 Mbps for Sabrina
In Sabrina platform, memory speed is limited to 5500 Mbps. Update the
SPD generation tool to limit to that speed.

BUG=b:238074863
TEST=Build and boot to OS in Skyrim.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ie3507898167012e0d812c9b1aacba72e9055fcd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2022-07-19 15:11:53 +00:00
Elyes Haouas 50eef6566b lint/checkpatch: Add check for used comma where semicolon could be
This reduce the difference with linux v5.19-rc7.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I6d3a49378008bad61b2a18bd8cb28be952a18006
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19 01:48:35 +00:00
Elyes Haouas f9a3554a4a lint/checkpatch: Add a check for use of self-assignments
This reduce the difference with linux v5.19-rc7.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: If47a7826ee67a2be25a4caa2a447484e5f11411b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19 01:48:24 +00:00
Elyes Haouas e83e090b05 lint/checkpatch: Add a check for existence of a commit log
This reduce the difference with linux v5.19-rc7.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I4e3b98140d900c5717f4badde71c7be88fd1e23a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19 01:48:13 +00:00
Elyes Haouas 6e84c2ca70 lint/checkpatch: Update 'Check patch "separator" and "signoff"'
This reduce the difference with linux v5.19-rc7.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Id3d7375216af5bf75ed7ce61fa8ea2dfebe8ac77
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19 01:47:59 +00:00
Elyes Haouas cb346842ad lint/checkpatch: Update 'check for unwanted Gerrit info'
This reduce the difference with linux v5.19-rc7.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I856bfa0f0d39fda549671b1029cccdc39f831bab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19 01:47:49 +00:00
Elyes Haouas e235a0de18 lint/checkpatch: Update 'uncoalesced string fragments'
This reduce the difference with linux v5.19-rc7.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I21b2a0d87cbf610fc48e273ed78ab779ad4a6932
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19 01:47:34 +00:00
Elyes Haouas 71bfcf528d lint/checkpatch: Update 'concatenated string without spaces between elements'
This reduce the difference with linux v5.19-rc7.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I04e58aca4a30e82f3da0cda08403d0daf3b5fb10
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19 01:47:17 +00:00
Elyes Haouas a59a87ca17 lint/checkpatch: Update 'check indentation of a line with a break'
This reduce the difference with linux v5.19-rc7.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I79170a45cd8184ebc816b4f16656a3cfdc257f60
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19 01:46:40 +00:00
Elyes Haouas d92fcf448f lint/checkpatch: Update 'check for logical continuations'
This reduce the difference with linux v5.19-rc7.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I222e3378ded4cd73d0141cd1e38ac3282d311cc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19 01:46:22 +00:00
Elyes Haouas 86e4a3ae05 lint/checkpatch: Update 'check for adding lines without a newline'
This reduce the difference with linux v5.19-rc7.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1bd68e9a6609a3dfa7dc856f24e4b616714d9990
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19 01:46:09 +00:00
Elyes Haouas c5ede53ba8 lint/checkpatch: Update 'check for assignments on the start of a line'
This reduce the difference with linux v5.19-rc7.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ia7d4b0176bad849e79f037f74c3d99ce9eb061c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-07-19 01:45:55 +00:00
Yu-Ping Wu fcfc572947 util/xcompile/xcompile: Define GCOV_${TARCH}
When payloads analyze the coverage using gcov (or lcov), the gcov
version must match the CC version. Otherwise gcov would fail to parse
the .gcno files.

Therefore, define GCOV_${TARCH} in xcompile, so that payloads don't need
to do tedious string manipulations to find the right gcov path.

Change-Id: If2fc329810c463a3d2c56deaf4e4a3fc3c0a3ed9
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2022-07-15 05:59:38 +00:00
Bill XIE ac136250b2 commonlib: Substitude macro "__unused" in compiler.h
Since there are many identifiers whose name contain "__unused" in
headers of musl libc, introducing a macro which expands "__unused" to
the source of a util may have disastrous effect during its compiling
under a musl-based platform.

However, it is hard to detect musl at build time as musl is notorious
for having explicitly been refusing to add a macro like "__MUSL__" to
announce its own presence.

Using __always_unused and __maybe_unused for everything may be a good
idea. This is how it works in the Linux kernel, so that would at least
make us match some other standard rather than doing our own thing
(especially since the other compiler.h shorthand macros are also
inspired by Linux).

Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I547ae3371d7568f5aed732ceefe0130a339716a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-07-14 23:08:09 +00:00
Jack Rosenthal f77fa2f7a9 util/spd_tools: Add support for 7500 MT/s lp5 modules
spd_tools does not support LP5x modules yet, and the easiest way to do
this is to add support for 7500 MT/s in lp5.go (reference the comments
on CB:65063).

BUG=b:238674174
BRANCH=firmware-brya-14505.B
TEST=With follow-on CL, run:
     util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I1558d69bc6f28c02c20aa9cd87d4543c1cf52afd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
2022-07-14 21:27:01 +00:00
Subrata Banik 123bcb702a util/spd_tools: Add Intel Meteor Lake (MTL) platform
This patch add support for MTL platform to the `spd_tools`.
This would be useful to create dynamic SPD for rex variants.

BUG=b:224325352
TEST=Able to generate SPD for LP5 DRAM part.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1db6e3a63d2842c12ef0f256ba1d32b9258670f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-07-14 12:50:10 +00:00
Petr Cvek 61f3f33311 Remove executable flag from source codes and text files
Markdown, definition file and sconfig source codes don't need to be
executables. This patch fixes that.

Signed-off-by: Petr Cvek <petrcvekcz@gmail.com>
Change-Id: Ic97d684318c689259f7895e3dfbd552434c3882e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-07-14 12:46:07 +00:00
Tim Crawford 5c2b5fcf2f util: Allow installing to a build root
Modify util Makefiles to allow installing to a build root specified by
DESTDIR. Allows using the `install` target for packaging.

Change-Id: I3a31ea0fde9922731e1621dcc8f94b2c1326c93c
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60540
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-07-12 22:11:35 +00:00
Paul Menzel 1ff6125af7 util/release/build-release: Use `git log … -1` over `|head -1`
Avoid piping to `head` to print the top line, and do it in `git log`
directly.

Change-Id: Id9b99b06c5bdd9c381bd039fc1914a9a2f332aa6
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-07-06 19:21:35 +00:00
Jon Murphy c4e90454f4 treewide: Unify Google branding
Branding changes to unify and update Chrome OS to ChromeOS (removing the
space).

This CL also includes changing Chromium OS to ChromiumOS as well.

BUG=None
TEST=N/A

Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-07-04 14:02:26 +00:00
Fred Reitberger f36b0138c4 util/amdfwtool: Initalize all variables before use
Not all of the fields of the amd_cb_config structure were properly
initialized. Rather than initialize each field individually, initialize
the entire structure to 0.

TEST: Boot chausie

Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ia343f01bce3956d66d01ce485b43963193c9df31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-06-30 19:08:14 +00:00
Elyes Haouas f6abb9ef8d crossgcc: Upgrade CMake from 3.23.0 to 3.23.2
Change-Id: I3613522fa2a958d2a42674f17aa794bdda4ca74a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63123
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-27 22:21:50 +00:00
Evgeny Zinoviev c3566b67f6 nvramtool: Fix building on Linux systems with musl libc
Current implementation only supports glibc (by looking for __GLIBC__)
and fails to build on systems with alternative libc implementations,
such as musl; sys/io.h is never included, there are no outb/inb
functions which results in undefined references at linking stage.

Using __linux__ instead of __GLIBC__ to test whether the system is Linux
seems to be a more proper way to detect Linux and it also fixes
nvramtool compilation on musl systems.

Tested on Gentoo Linux with musl 1.2.2 (builds and works fine) and Void
Linux with glibc (still builds and works fine).

Change-Id: Idcdc3a033b40f16a6053209813f1e06209ee459a
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48757
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-23 12:19:52 +00:00
Arthur Heymans 0424a2c59f util/ifdtool: Fix printing or setting PCH straps
When printing or setting the PCH straps use the PSL directly instead
of multiplying it by 4.

Change-Id: Ia91697fdf0c6d80502e8611b259c444f39c6cd57
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2022-06-23 12:17:54 +00:00
Martin Roth 93333cb34e util/lint: Add coreboot specific dictionary file
This is a wordlist that I've compiled to use in spellcheckers to ignore
all of the coreboot specific terms.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I718519000eaf31786380474eb71b99ca442e3bed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-06-22 21:40:19 +00:00
Arashk Mahshidfar e607ddc5c9 util/inteltool: Add an additional Device ID for Intel HD 4400 GPU
Add 0x0A16 as a Device ID for Intel HD 4400

Change-Id: I0129376c0ce005c1bfabaa9dbd8d8dfc6c92e5d3
Signed-off-by: Arashk Mahshidfar <arashkmahshidfar@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2022-06-22 00:51:30 +00:00
Angel Pons bb58c1e438 util/cbfstool: Set `USE_FLASHROM=0` to build vboot
cbfstool does not need to build vboot with flashrom support.

TEST=./util/abuild/abuild -a --timeless -y -c $(nproc) -Z -t hp/280_g2
     no longer fails due to missing libflashrom.h header.

Change-Id: I57edcb1b67baa4c458874b11e9ca0238b4419c46
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-06-19 18:46:04 +00:00
Edward O'Callaghan 01dbba5e3d util/cbfstool/common.c: Deduplicate buffer_create() logic
BUG=b:207808292,b:231152447
TEST=builds with vboot_ref uprev.

Change-Id: Id7d9b6f5254b08720eebb37151e12ee68ed7f8d7
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65145
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-06-16 20:38:53 +00:00
Edward O'Callaghan 774dcffc36 util/cbfstool: Decouple elogtool from vboot_ref flashrom code
Currently elogtool sub-proccesses flashrom as calling libflashrom
requires a missing function from the previous flashrom release.
Pending a new release of flashrom we must continue to use subprocess.

However the current subprocess wrapper implementation lives in
vboot_reference which is a git sub-module of coreboot. This causes
all sorts of grief keeping a subprocess ABI stable from vboot_reference
when the rest of vboot_reference builds of HEAD of the flashrom tree
(i.e., using unreleased libflashrom functions). In order to not keep
finding ourseleves in a bind between the two separately moving trees
with different build environments, decouple elogtool with its own
mini copy of flashrom subprocess wrapping logic.

Squash in,
 util/cbfstool/elogtool.c: Convert args into struct in flashrom helper

  vboot signatures for flashrom r/w helpers changed in the upstream
  commit bd2971326ee94fc5. Reflect the change here to allow vboot ref
  and coreboot to realign.

BUG=b:207808292,b:231152447
TEST=builds with vboot_ref uprev.

Change-Id: I04925e4d9a44b52e4a6fb6f9cec332cab2c7c725
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-06-16 20:38:41 +00:00
Shou-Chieh Hsu 446bacd2f4 util/mb/google: add support for nissa
Add the file template for creating a new variant of Nissa.

BUG=b:229550821

Signed-off-by: Shou-Chieh Hsu <shouchieh@google.com>
Change-Id: I04f75ff91f9851b82641f703ba950b04c22e2e72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-06-14 00:53:14 +00:00
Felix Singer 3e94068508 util/liveiso: Update to NixOS 22.05
Update configs for NixOS 22.05.

pulseaudio-modules-bt has been abandoned, and is superseded by
pulseaudio's native Bluetooth functionality. Thus, remove it.

Change-Id: Ic3b1dbc3c2ab092b576ba2151c93c74d4f298efc
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-06-13 20:12:33 +00:00
Nico Huber f9b5665d28 crossgcc/gnat.patch: Add additional gnatlib object files
Newer host versions of gnatbind miss these when building the cross
gnat1 and gnatbind.

Tested with the following host compilers with and without bootstrapping
that the resulting coreboot images of three boards stay the same:
* GCC 4.9.2 (Debian)
* GCC 6.3 (Debian)
* GCC 7.4 (Debian)
* GCC 8.3 (Debian)
* GCC 9.4 (Debian)
* GCC 10.2 (Debian)
* GCC 12.1 (ArchLinux)

Change-Id: I09c6b3cc7b15f1c505acd3ec2c1959b101d6dfb7
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65000
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-10 14:09:32 +00:00
Nico Huber 0b2a632005 crossgcc/gnat.patch: Never treat warnings as errors
We used to disable individual warnings that are expected when building
our GCC version with a newer one. Not all warnings can be disabled
indvidually, though, and it's much easier to simply allow warnings.
As a plus, we get the warnings in the log (in case anybody would ever
look into it).

Partially fixes building with host GCC 12.1.

Change-Id: I8fafec4fc49db73b6dba311c775eea2cc92a9b48
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-10 14:08:57 +00:00
Martin Roth 124c418ccf util/util_readme: update to give additional information
Add a note to the top of the util.md document saying not to edit it.

The Documentation/util.md file had been updated to contain additional
information at the bottom.  This copies that information into the file
after it's been created.

Change-Id: I4b08439420ceb706df62e3949406585ea34c1514
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-06-07 15:49:56 +00:00
Martin Roth 56846091f1 util, Documentation: Run util_readme.sh to regen util.md
Change-Id: Ie14204d0637bb5081e2fae4a9a0e2590bf7abeeb
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-06-07 15:49:27 +00:00
Julius Werner 423cd06fa6 cbfstool: Expand CBFS verification validity check
This patch adds a new line to `cbfstool print -v` output that records
the overall CBFS verification health of the image. While this info was
already visible from individual fields before, it's nice to have a
one-stop location to see "this is a good image" without having to
carefully parse a lot of output manually.

Also add a few lines to the Makefile that check whether this field is
valid for the final image (it always should be, but hopefully this check
will allow us to catch regressions like the one fixed by CB:64547 sooner
in the future).

BUG=b:233263447

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I1b74b01a55b22294556007aaee835d0fdb9e1c63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-06-07 12:57:25 +00:00
Michał Żygowski de91780c30 inteltool/gpio_names/tigerlake.h: Fix HVMOS pad count
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I344fd2db9d53ad5e82240aaa2b766ac0d8a2045d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64464
Reviewed-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-06-03 20:06:01 +00:00
Patrick Georgi 7310789085 util/scripts/cross-repo-cherrypick: Modify output format
As far as I know the Chromium OS team is the only user of this script,
so align its output with that of other tools used there:

- Replace "Original-Commit-Id" with "GitOrigin-RevId"
- Reuse Change-Id instead of moving it to the Original- prefix, which
  leads to the creation of a new Change ID.

Change-Id: I8c39c512901c83a64f00aa48a539e6621f827242
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-06-03 18:44:51 +00:00
Martin Roth 8da4bfe5b5 util/release/build-release: Use short git hash for .coreboot-version
Builds were suddenly failing when the release was done, because the
coreboot version was overflowing a 64 character limit.  We don't need
or use the full hash in other places, so limit the hash to just what's
needed to identify the commit.

Change-Id: I57c535ca251792cae2c9a9c951e6b44bb61e4e78
Signed-off-by: Martin Roth <martin@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-06-03 03:10:05 +00:00
Julius Werner af20fd748b cbfs: Add CBFS_TYPE_INTEL_FIT and exclude it from CBFS verification
The Intel Firmware Interface Table (FIT) is a bit of an annoying outlier
among CBFS files because it gets manipulated by a separate utility
(ifittool) after cbfstool has already added it to the image. This will
break file hashes created for CBFS verification.

This is not actually a problem when booting, since coreboot never
actually loads the FIT from CBFS -- instead, it's only in the image for
use by platform-specific mechanisms that run before coreboot's
bootblock. But having an invalid file hash in the CBFS image is
confusing when you want to verify that the image is correctly built for
verification.

This patch adds a new CBFS file type "intel_fit" which is only used for
the intel_fit (and intel_fit_ts, if applicable) file containing the FIT.
cbfstool will avoid generating and verifying file hashes for this type,
like it already does for the "bootblock" and "cbfs header" types. (Note
that this means that any attempt to use the CBFS API to actually access
this file from coreboot will result in a verification error when CBFS
verification is enabled.)

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I1c1bb6dab0c9ccc6e78529758a42ad3194cd130c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-06-01 19:45:22 +00:00
Julius Werner 0057262b38 cbfs: Rename TYPE_FIT to TYPE_FIT_PAYLOAD
There are too many "FIT" in firmware land. In order to reduce possible
confusion of CBFS_TYPE_FIT with the Intel Firmware Interface Table, this
patch renames it to CBFS_TYPE_FIT_PAYLOAD (including the cbfstool
argument, so calling scripts will now need to replace `-t fit` with `-t
fit_payload`).

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I826cefce54ade06c6612c8a7bb53e02092e7b11a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-06-01 19:45:08 +00:00
Martin Roth b3f91b7941 util/docker: Update dockerfiles
- Remove deprecated "MAINTAINER" lines
- Add Sphinx tools to coreboot-jenkins-node to check documentation.
- Add mdl to check markdown
- Alphabetize packages in docs Dockerfile
- Add jinja2 version 3.0.3 to the docs Dockerfile - The latest version
breaks with the error:
"exception: cannot import name 'contextfunction' from 'jinja2'"

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ia1de62621a6aef4ecd055a1a3afbebad34448002
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-05-31 13:41:56 +00:00
Martin Roth 74129e5141 util: Update description files
- Spelling fix
- Add languages
- Update formatting
- Move notes that shouldn't be in the description file to a README

Change-Id: I4af37327d5834f8546a3f967585658fb5686f17a
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-05-30 13:05:21 +00:00
Martin Roth e44a3d2842 util: Fix a few spelling mistakes
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ib6f0232292c9e289ee1e87998493ea70beea8e78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-05-30 04:25:07 +00:00
Martin Roth 81e0d689c0 Documentation: Move intelp2m from description.md to Documention
The description.md file for the intelp2m utility wasn't the description
that was needed - just a subject, and what language it was written in.
It was instead a set of more full documentation, so move it into the
Documentation directory and create a new description file.

Change-Id: Ia180ae41f91f8b8eb408351a9e44e899edc031d3
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-05-30 04:19:39 +00:00
Elyes Haouas 709fdb1995 util/lint/checkpatch: Add alloc functions to alloc with multiplies check
This reduce difference with linux v5.18.

Change-Id: Id9412f7b6c0b9f76b39a094142aaded5c2aa1059
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-29 14:55:38 +00:00
Elyes Haouas 069dfe33a3 util/lint/checkpatch: Update 'Check for compiler attributes'
This reduce difference with linux v5.18.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I817630321587dec515cd94aa7b73a17819526190
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-29 14:55:21 +00:00
Elyes Haouas a7b0d38964 util/lint/checkpatch.pl: Use 'allocFunctions'
This reduce difference with linux v5.18.

Change-Id: I1fc71b9cb6a4e4f8b27fbe6d45f4fa4e2c236157
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-29 14:55:02 +00:00
Michał Kopeć 2d8edebc97 util/inteltool: Add support for Alder Lake chips detection and GPIOs
Add PCI IDs for Alder Lake H devices and their GPIO tables.

PCI IDs as per Intel PCH-H EDS Vol1 (doc #619362).

TEST=dump GPIOs on i5-12600K with Z690 chipset

Change-Id: I0001395517e1e7977b0f808d5d74cf85c52298d6
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2022-05-28 14:36:50 +00:00
Arthur Heymans c2eb9e6e81 abuild: Build with clang only when supported
This changes the behavior of '-L/--clang' to only buildtest when a
target has ARCH_SUPPORTS_CLANG set.

Change-Id: I362fcd0f795d27f13dde793a79774f08c497bd38
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-28 05:23:21 +00:00
Martin Roth 97e7eea976 util/lint/checkpatch: Warn on period at the end of commit subject
This gives a warning when there's a period at the end of the commit
subject line.

Change-Id: If95bef3ba01e0ac13ce18045928081040abef4fd
Signed-off-by: Martin Roth <martin@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-05-28 01:26:03 +00:00
Martin Roth 341a53d1c5 util/lint: Subtract the patch format string from subject length
Checkpatch was looking for a 65 character length, but format-patch adds
the text "Subject: [PATCH] " before the actual subject.  Checkpatch
needs to account for that when looking at the line length.

Lines 2863 & 2864 have their indentation fixed as well.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I2f2ee6e0f1b14ae6393ed7e64ba1266aa9debc7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-05-28 01:25:48 +00:00
Martin Roth 9e33723d9b util/lint: Add commit message parsing to checkpatch_json script
The commit message wasn't being parsed because there's no filename
associated with it in the patch output.  This change adds the "filename"
for the commit message in Gerrit for any errors that have a line number
but no filename.

calculations is intentionally misspelled as cacluations as a test.

Change-Id: Ie7a2ef06419c7090c8e44b3b734b1edf966597cc
Signed-off-by: Martin Roth <martin@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-05-28 01:25:37 +00:00
Michał Kopeć d3b550d47c util/intelp2m: Add support for Alder Lake macro generation
Add support for Alder Lake as a separate parsing profile, copying the
existing 'Cannon' profile and adjusting for differences in reset mapping
and GPIO macro generation.

TEST=Generate GPIO macros for MSI PRO Z690-A

Change-Id: I5871394bcb0636c2c803607ffb129441aa934417
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2022-05-25 23:25:25 +00:00
Elyes Haouas 26e0b94614 util/lint/checkpatch.pl: Reduce difference with linux v5.18
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Id5eb4823399088746a34721a9855bbaf5f97b7b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-24 12:57:48 +00:00
Maximilian Brune 94223c4165 Allow trailing whitespaces in .md files
Two trailing whitesspaces have an actual meaning in Markdown files (a new line).

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ibdb92ee857ee4ad32b6afb84ace427b27b41bb7c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16 19:58:31 +00:00
Robert Zieba 4098ecf5bd util/testing: Remove amdfwread from makefile
amdfwread was added to the testing makefile but ended up not becoming a
separate tool. This commit removes it from the makefile so that `make
distclean` works again.

Fixes: 29bc79fddb ("util/amdfwtool: Add
amdfwread utility")

TEST=Ran `make distclean`

Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I2c8b920bc69d6c20558a28515c52a1e9cecebe27
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64348
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-16 15:56:50 +00:00
Sean Rhodes 645dde7794 util/inteltool: Add support for Gemini Lake
Tested on:
* StarLite Mk III (N5000)
* StarLite Mk IV (N5030)

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I0ef7619c04db66ea0c6e179bdf0a58ed1ab61a48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-05-16 07:04:22 +00:00
Martin Roth af06e9adea util/lint/lint-stable-019: Update grep '\s' to [[:blank:]]
For some reason, the '\s' syntax is causing an error for me under
freebsd.  It's entirely possible that I'm doing something wrong, but
this change should be fine regardless.

Freebsd's grep, GNU grep, and git grep all handle posix regex classes,
so this change should be transparent.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I489ec13b4ea2e9c17692888e42b8741763b1a2c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-05-16 05:18:09 +00:00
Elyes Haouas 14c49e3646 util/lint/checkpatch.pl: Fix "uninitialized value" error message
Change-Id: I74807f240779060158c6769f63a6e9438a6e5fbe
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16 02:28:44 +00:00
Elyes Haouas 0014bce46b util/lint/checkpatch.pl: Fix "Invalid color mode" error message
Remove duplicated code:
"if ($color =~ /^[01]$/) {
	$color = !$color;
} elsif ($color =~ /^always$/i) {
	$color = 1;
} elsif ($color =~ /^never$/i) {
	$color = 0;
} elsif ($color =~ /^auto$/i) {
	$color = (-t STDOUT);
} else {
	die "$P: Invalid color mode: $color\n";
}"

Change-Id: I5713c364edea806e58df26c3a37b4bba7603ed0a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
2022-05-16 02:28:02 +00:00
Robert Zieba 29bc79fddb util/amdfwtool: Add amdfwread utility
Amdfwtool creates AMD firmware images however there is currently no way
to get information from an existing image. This commit adds amdfwread to
support that functionality. At the moment only reading PSP soft fuse
flags is supported. Example usage: `amdfwread --soft-fuse bios.bin`,
example output: `Soft-fuse:0x400000030000041`.

BUG=b:202397678
TEST=Ran amdfwread and verified that it correctly reads the soft fuse
bits, verified that built AMD FW still boots on DUT

Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I15fa07c9cad8e4640e9c40e5539b0dab44424850
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-05-13 15:51:37 +00:00
Arthur Heymans a0595759f6 xcompile,clang: increase the number of bracket-depth for CPP
Clang has a limit for the number of nested brackets in CPP.
For soc/intel/common/block/include/intelblocks this is a problem as it
largely exceeds the default limit of 256.

Change-Id: I93038f918e07f735394fc495a8ed7371cc5b1569
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62175
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-13 11:03:16 +00:00
Karthikeyan Ramasubramanian 0ab04d2851 util/amdfwtool: Add IKEK key for Trusted Application
This binary file is required for use by Trusted Applications that
execute in PSP.

BUG=b:229947314
TEST=Build and boot to OS in Skyrim.

Change-Id: I2d05792cfd98fa9c38f5deef1ac3282625983eeb
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-05-05 14:48:31 +00:00
Yu-Ping Wu f1a8dde147 cbfstool: MediaTek: Hash bootblock.bin for CBFS_VERIFICATION
MediaTek's bootROM expects a SHA256 of the bootblock data at the end of
bootblock.bin (see util/mtkheader/gen-bl-img.py). To support CBFS
verification (CONFIG_CBFS_VERIFICATION) on MediaTek platforms, we need
to re-generate the hash whenever a file is added to or removed from
CBFS.

BUG=b:229670703
TEST=sudo emerge coreboot-utils
TEST=emerge-corsola coreboot chromeos-bootimage
TEST=Kingler booted with CONFIG_CBFS_VERIFICATION=y

Change-Id: Iaf5900df605899af699b25266e87b5d557c4e830
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63925
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-05 14:18:38 +00:00
Martin Roth 3201e1e68c util/scripts: Add options to update_submodules
This extends and adds various options to the update_submodules script.

Extensions:
- Add help text
- Add all options, but specifically allow a single repo to be specified,
along with a minimum number of changes instead of being fixed at 10.
- Make it a more formal script with main() and functions
- Show changes in commit message, unless there are > 65 commits.

Options:
-c | --changes <#>     Specify the minimum number of changes to update a repo
-h | --help            Print usage and exit
-R | --repo <dir>      Specify a single repo directory to update
-s | --skipsync        Assume that repos are already synced
-V | --version         Print the version and exit

This does not fix style issues in the original, which will be fixed in
a follow-on commit.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I222103babff7d5f4f8eb02869c598a4e06748a17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-05-04 13:12:23 +00:00
Manoj Gupta dfb8d80c1a utils/cbfstool: Disable Wstrict-prototypes warning
As recommended on crrev.com/c/3612466 lz4 code is not supposed
to be modified. Since both gcc and clang complain about
functions without explicit void in argument with Wstrict-prototypes,
just disable it instead instead of enabling.

BUG=b:230345382
TEST=llvm tot test
BRANCH=none

Signed-off-by: Manoj Gupta <manojgupta@google.com>
Change-Id: I9f3ae01821447f43b4082598dd618d9f8325dca2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63936
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-05-02 21:02:57 +00:00
Nick Vaccaro 946e29258c util/cbmem: fix an unused parameter issue in timestamp_get
Fix an unused parameter error when building on devices where __i386__
and __x86_64__ are not defined.

BUG=none
TEST=none

Change-Id: I6c04c8e7b931565c87d358aac1025ebcb7617b13
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63880
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-27 00:32:29 +00:00
Zheng Bao 993b43f2be amdfwtool: Use command line option use-combo to decide if use combo
The macro PSP_COMBO is removed and instead use the flag use_combo. As
long as this flag is false, the amdfwtool behaves the same way as the
macro does.

Change-Id: Ief0d78ae1e94b8183d6cf3195935ff9774fee426
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-25 14:48:16 +00:00
Zheng Bao 96a3371a72 amdfwtool: Change the name of macros for 'BHD'
Use BHD instead of BDT as the name of cookie macro. Use L2 to make it
clear it is for level 2. The 'BHD2' is misleading, which is going to
be used for combo entry. The definition in psp_verstage is also changed.

Change-Id: Ia10ac5e873dab6db7d66e63773a7c63f504950b2
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-04-25 14:46:12 +00:00
Arthur Heymans 597b9e9d71 cpu/x86/64bit: Generate static page tables from an assembly file
This removes the need for a tool to generate simple identity pages.
Future patches will link this page table directly into the stages on
some platforms so having an assembly file makes a lot of sense.

This also optimizes the size of the page of each 4K page by placing
the PDPE_table below the PDE.

Change-Id: Ia1e31b701a2584268c85d327bf139953213899e3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-25 14:00:41 +00:00
Elyes Haouas 43529c8b20 util/lint/checkpatch.pl: Update lines related to CONST_STRUCT
Update to v5.18-2 version.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I0fe2ec6a74a4b8c70452fbf05d534a37e1ea2c26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-24 21:19:40 +00:00
Elyes Haouas f0e150c35a util/lint/checkpatch.pl: Add strlcpy check
Update to v5.18-2

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ic4eaa3f26bcd60ea509a52d5715c7ce1f43b6d3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-24 21:18:55 +00:00
Elyes Haouas 8f59960fb2 util/lint/checkpatch.pl: Update C99_COMMENT_TOLERANCE lines
Update to v5.18-2 version.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: If230fa5cd01ab3ce91d8c910667c3d609cf978b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-24 21:18:11 +00:00
Elyes Haouas 00d8ffdada util/lint/checkpatch.pl: Update TYPECAST_INT_CONSTANT lines
Update to v5.18-2 version.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I8ed89e53f647b1b071abff33a434fb3b8dbb1de1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-24 21:17:34 +00:00
Elyes Haouas 84083a27aa util/lint/checkpatch.pl: Update the check of repeated words
Update to v5.18-2 version.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I7f5e597bb76e1b9feeb2d6ea290626f45e9fe6c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-24 21:17:00 +00:00
Elyes Haouas f62a98939d lint/checkpatch.pl: Update to v5.18-2 lines related to "CONFIG_"
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I8589d053871ad9ac64ae2f8fc380710be8e4556b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-24 21:16:14 +00:00
Elyes Haouas 0b1a03cd18 util/lint/checkpatch.pl: Update lines related to max_line_length
Upadate to v5.18-2 version.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ib9927bfa98e20d4b621bf7abecec234b4754ee9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-24 21:16:04 +00:00
Elyes Haouas 41d43f5eeb util/lint/checkpatch.pl: Update lines related to tabsize
Update to v5.18-2 version.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I6651a3f8e79beca2e1235fe8de3217875f81ba2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-24 21:15:33 +00:00
Elyes Haouas 46b07e53f5 util/lint/checkpatch.pl: Update to v5.18-2 lines related to verbosity
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I66f38cb01e58ee241bf58c4db83693029ddebcfa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
2022-04-24 21:14:24 +00:00
Mattias Nissler ecc165b789 util/cbmem: add an option to append timestamp
Add an option to the cbmem utility that can be used to append an entry
to the cbmem timestamp table from userspace. This is useful for
bookkeeping of post-coreboot timing information while still being able
to use cbmem-based tooling for processing the generated data.

BUG=b:217638034
BRANCH=none
TEST=Manual: cbmem -a 1234 to append timestamp, verify that cbmem -t
shows the added timestamp.

Change-Id: Ic99e5a11d8cc3f9fffae8eaf2787652105cf4842
Signed-off-by: Mattias Nissler <mnissler@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-22 22:43:36 +00:00
Jianjun Wang b2537bdad5 coreboot_tables: Replace 'struct lb_uint64' with lb_uint64_t
Replace 'struct lb_uint64' with 'typedef __aligned(4) uint64_t
lb_uint64_t', and remove unpack_lb64/pack_lb64 functions since it's no
longer needed.

Also replace 'struct cbuint64' with 'cb_uint64_t' and remove
'cb_unpack64' in libpayload for compatible with lb_uint64_t.

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: If6b037e4403a8000625f4a5fb8d20311fe76200a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-14 22:27:50 +00:00
Karthikeyan Ramasubramanian 4bdc2320a4 util/apcb/apcb_v3_edit.py: Edit APCB based on different SPD magic
APCB edit tool edits APCBs with LP4 specific SPDs. Introduce an option
to support different SPD magic so that the tool can be used to edit
APCBs with LP5 specific SPDs.

BUG=None
TEST=Build Skyrim board with LP5 specific SPDs. Build Guybrush board
with LP4 specific SPDs.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I8e96c89e4e5ce8e0567a17bf7685b69080fa1708
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63598
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-14 22:24:09 +00:00
Karthikeyan Ramasubramanian 58d75f80b4 util/spd_tools/part_id_gen: Support Sabrina SoC
Add support to generate DRAM part ID for boards using Sabrina SoC.

BUG=None
TEST=Generate DRAM part ID for Skyrim mainboard.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ica57b12239019831f7bf93982be3c93b7f8b6986
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-14 22:23:51 +00:00
Karthikeyan Ramasubramanian ad06bae7b1 util/amdfwtool: Maintain one copy of PSP Level2 entries
AMDFWtool maintains 2 copies of PSP Level2 entries - one in primary slot
A (Type 0x48) and another in backup slot B (Type 0x4A). On boards which
use VBOOT with 2 RW firmware slots, maintaining 2 copies of PSP Level2
entries in each FW slot is redundant and space-consuming. Introduce
option to maintain only one copy of PSP Level2 entries and point to it
from both slots A & B.

BUG=None
TEST=Build and boot to OS in Skyrim. Ensure that only one copy is added
to each FW slot. This achieved a space saving of 1.5 MB in each FW slot.
Before:
apu/amdfw                      0x415fc0   raw           3043328 none
After:
apu/amdfw                      0x415fc0   raw           1556480 none

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I06eef8e14b9c14db1d02b621c2f7207188d86326
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-14 15:39:15 +00:00
Zheng Bao c3007f3877 amdfwtool: Add a flag to record the second gen instead of romsig
This is for future feature combo, which gets the soc id from fw.cfg in
a loop instead of the command line, and the romsig is not set until
fw.cfg is processed.

Change-Id: Id50311034b46aa1791dcc10b107de4af6c86b927
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-13 23:25:00 +00:00
Elyes Haouas 84ef4fb15b util/lint/checkpatch.pl: Update to v5.18-2 lines related to "codespell"
Change-Id: I55cc4255ea88723c813a04d87e4c028c64f92dbd
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2022-04-11 13:59:59 +00:00
Michał Kopeć bd656b4e4c superiotool/ite: add IT8625E EC registers
Add support for dumping ITE IT8625E Environmental Controller registers.

Values as per "IT8625E Preliminary Specification V0.3 (For D Version)".

Change-Id: I68aad90097206c6b8ef40075530c00809d9511e2
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-04-06 16:28:53 +00:00
Zheng Bao 487d04540b amdfwtool: Add a macro to set explicitly second gen for old SOCs
It is more reasonable than getting the value from memset.

For the reserved bits, keep them as they were for old SOCs.

Change-Id: I65caa11e835d2ff52bec4b8904057bbced434891
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-04-05 17:45:58 +00:00
Robert Zieba 255b1fb38b util/spd_tools: Add ability to override SPD file for parts
This commit adds the ability to override the SPD file that is used for a
specific part.

BUG=b:224884904
TEST=Verified that generated makefile uses specified SPD file and that
it remains unchanged when this capability is not used

Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: I078dd04fead2bf19f53bc6ca8295187d439adc20
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-04-05 14:50:56 +00:00
Elyes Haouas 9a8d0a03db crossgcc: Upgrade IASL from 20211217 to 20220331
"REDUNDANT_OFFSET_REMARK" to ignore redundant offset remarks is
not needed any more as it’s included upstream.

Changes: https://acpica.org/node/199

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ice7f9a10051f7f62c53098161fd2f498d724c17d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-04-04 13:54:49 +00:00
Elyes Haouas 6d976919d0 crossgcc: Upgrade CMake from 3.22.2 to 3.23.0
Release Notes:
  https://cmake.org/cmake/help/v3.23/release/3.23.html

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ib31124baa3cae65211ad361a7d41c9504105be91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-04-04 13:54:20 +00:00
Felix Held 11b0d360ba util/amdfwtool/data_parse: fix SPL table handling regression
Use the SPL table binary from the config file if no override is
specified via the spl-table command line argument. This fixes a
regression caused by commit 6c5ec8e31c
(amdfwtool: Add options to support mainboard specific SPL table).

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I93419a878b41b1dfcbf58d930740aaae553120f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-04-03 17:06:48 +00:00
Paul Fagerburg ac68384c0c util/cbmem: add type cast
arch_convert_raw_ts_entry returns a uint64_t, which needs to be cast
on ARM systems to avoid a type error.

BUG=b/227871959
TEST=no build errors in downstream

Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: I87a83758b7f122b77f9631c669c7cd8df66f8d1b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63317
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-02 16:12:28 +00:00
Arthur Heymans 8b82c6b91b util/ifittool: Fix clearing FIT when setting the pointer
When setting the FIT pointer, the FIT table is only known later in the
codeflow.

Change-Id: I658f4fffa997d1f7beaf6d6ae37d2885ae602e5c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63035
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-01 09:29:19 +00:00
Jakub Czapiga 48f6c2b46f util/cbmem: Add FlameGraph-compatible timestamps output
Flame graphs are used to visualize hierarchical data, like call stacks.
Timestamps collected by coreboot can be processed to resemble
profiler-like output, and thus can be feed to flame graph generation
tools.

Generating flame graph using https://github.com/brendangregg/FlameGraph:
  cbmem -S > trace.txt
  FlameGraph/flamegraph.pl --flamechart trace.txt > output.svg

TEST=Run on coreboot-enabled device and extract timestamps using
     -t/-T/-S options

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I3a4e20a267e9e0fbc6b3a4d6a2409b32ce8fca33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-31 23:04:58 +00:00
Felix Held f8e2e47e2b util/amdfwtool: use ISH support for Sabrina SoC
The PSP in the Sabrina SoC uses the image slot header to find the second
level PSP directory table, so it needs the ISH to be generated.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9e6308854147c9f6f72d722215c833ee86ee4f94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63186
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30 23:42:14 +00:00
Felix Held b18a4c7d0d util/amdfwtool: add Sabrina SoC type
Add PLATFORM_SABRINA to the enum of supported platforms and integrate it
into the existing code.

Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibe52b44395619f697686bd900a522562abbe7646
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-30 23:41:53 +00:00
Felix Held 830add6e27 util/amdfwtool: select A/B recovery when ISH is used
In newer AMD SoCs, the image slot header is used in the AMD A/B recovery
scheme, so set recovery_ab to true when need_ish is true. Also move the
block of code before the process_config call, since that call will
already use the recovery_ab field of the cb_config struct.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I65903765514f215bf5cc9b949d0b95aff781eb34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63184
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30 23:41:48 +00:00
Felix Held 21a8e381ea util/amdfwtool: use table-relative addressing in ISH case
When the image slot header (ISH) is used, the addresses in the PSP and
BIOS directory tables need to be relative to the beginning of the table.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia61f7c8313d5a1af95c68b9177a53a2f5443552a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-30 22:20:04 +00:00
Idwer Vollering 70f3d43854 util/genbuild_h: micro-adjust the regexp used to set COREBOOT_MAJOR_VERSION
On FreeBSD, every build target would show warnings from its
builtin printf().
Change the regexp to be compatible with BSD sed.
This will avoid noise like "printf: 4.14-1278-g5d74ccf1c3: not
completely converted".

Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com>
Change-Id: I1c0c260fd8d42e23a612a353a288e472cc068c8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-03-30 20:06:57 +00:00
Zheng Bao 3a6ab474e0 amdfwtool: Clear the whole byte of EFS_GEN
Change-Id: I434e031e906f73362b1e920e034fa15a8d078ab2
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-29 15:41:20 +00:00
Zheng Bao fdd47ef1e6 amdfwtool: Add ISH header support for A/B recovery layout
Image Slot Header (ISH) is a new feature.
The rom layout for A/B recovery with ISH:
EFS -> PSP L1 0x48 -> ISH A -> PSP L2 A -> BIOS L2 A
              0x4A -> ISH B -> PSP L2 B -> BIOS L2 B

The newer 55758 will updated about the boot priority and update retry
in ISH header.

Change-Id: Ib0690cde1dce949514c7aacebe13096b7814ceff
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-27 15:24:15 +00:00
Felix Held 5f18bb75fb util/amdfwtool: add MSMU, SPIROM_CFG and DMCUB PSP FW types
Compared to Cezanne, the Sabrina SoC has a 3 additional PSP firmware
table entries, so add those as a preparation for Sabrina support.

Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iaa5aacd53b3c7637f6d5e94b1a8d92bba57ddb9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-27 15:21:21 +00:00
Martin Roth 10d34b7818 util/lint/checkpatch: Update commit message & subject line limits
The commit message has a (soft) line length limit of 72 characters and
the subject has a (soft) line limit of 65 characters. This change
updates checkpatch to warn at those limits.

Note that neither of these are hard limits because git & gerrit can both
handle longer lines, it just doesn't look good.

Change-Id: I4ef131a65254e2b184b05e0215969aef97e12712
Signed-off-by: Martin Roth <martin@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2022-03-25 19:23:59 +00:00
Zheng Bao fb9b784ca2 amdfwtool: Change the some FW's level for A/B recovery
The Pubkey(0), PSP bootloader(1) and IKEK(0x21) should be put to
level 2 only for A/B recovery for Sabrina, which is going to be the
long term and A/B recovery layout only. So the amdfwtool should be
changed for Sabrina.

The old levels of these 3 FWs are for Cezanne, which doesn't use AB
recovery now. Just set the specific field levels in generic Cezanne
folder for demo. Leave the fw.cfg in Guybrush unchanged.

Change-Id: I11092b52927b2c526a5be719104ba39a790b6fa8
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-03-23 20:17:45 +00:00
Robert Zieba a6425f170c util/spd_tools: Add support for exclusive IDs
Currently memory parts that use the same SPD are assigned the same ID by
spd_tools. This commit adds support for exclusive IDs. When given an
exclusive ID a memory part will not share its ID with other parts unless
they also have the same exclusive ID.

BUG=b:225161910
TEST=Ran part_id_gen and checked that exclusive IDs work correctly and
that the current behavior still works in their abscence.

Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: Ife5afe32337f69bc06451ce16238c7a83bc983c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2022-03-22 16:17:06 +00:00
Bora Guvendik c79da5f211 util/cbmem: Keep original Total Time calculation when no negative timestamps
"Total time" calculation changed after CL 59555 to include
"1st timestamp" value in the calculation. This patch restores original
Total Time calculation where "1st timetamp" is subtracted from
"jumping to kernel". If pre CPU reset timestamps are added (negative
timestamps), "Total time" calculation still includes the pre-reset time
as expected.

1) Before https://review.coreboot.org/c/coreboot/+/59555:
   0:1st timestamp                                     225,897
1101:jumping to kernel                                 1,238,218 (16,316)

Total Time: 1,012,281

2) After https://review.coreboot.org/c/coreboot/+/59555:
   0:1st timestamp                                     225,897
1101:jumping to kernel                                 1,238,218 (16,316)

Total Time: 1,238,178

3) After this patch:
   0:1st timestamp                                     225,897 (0)
1101:jumping to kernel                                 1,238,218 (16,316)

Total Time: 1,012,281

BUG=none
TEST=Boot to OS, check cbmem -t on Redrix board

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I0442f796b03731df3b869aea32d40ed94cabdce0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-03-21 20:30:05 +00:00
Zheng Bao 52a1898d44 amdfwtool: Check the length of matching string before accessing
If AB recovery is enabled and get a "Lx" in fw.cfg, wrong character
is got or access violation happens.

Change-Id: Ibd8ffe34fd44d860ec2115cd36117da7b02169cd
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2022-03-21 16:55:46 +00:00
Felix Singer 9bd35ddb35 util/liveiso: Remove coreboot toolchain from todo
The coreboot toolchain is a huge blob and increases the size of the
build a lot. If needed, the specific toolchain can be added before
building the ISO or with `nix-shell` later in the live system, as shown
below.

  $ nix-shell -p coreboot-toolchain.i386

Thus, remove this from the todo list.

Change-Id: Ia24ceb84f202828f1c97d3ba5bafbf6af0361bdb
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-03-17 18:51:35 +00:00
Subrata Banik ca82e6161a util/ifdtool: Add Meteor Lake platform support under IFDv2
BUG=b:224325352
TEST=Able to build ifdtool.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3564efa27d0271286435284e745458aada987008
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-15 19:22:49 +00:00
Julius Werner ce87832c66 cbmem: Fix console banner matches
Since the new loglevel markers were added, there will now be a marker
character at the beginning of the coreboot banner string, and this will
make the existing regular expressions meant to find it fail to match.
This patch fixes the problem by just allowing for a single extra
character there (any character to avoid the hassle of having to match
the marker explicitly). The extra character is optional so that we will
still continue to match banners from older versions of coreboot as well.

Since the `?` glyph is not available in basic POSIX regular expressions,
we have to switch to REG_EXTENDED syntax (should otherwise make no
difference). (Also, move side effects out of assert() while I'm here,
that's not actually safe for the standard libc implementation.)

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I99fb347eb1cf7b043a2113dfda7c798d6ee38975
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62720
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-10 23:42:53 +00:00
Martin Roth d5f45d0a9e util/futility: Don't echo the warning message unless it fails
Currently, all of the commands for building futility are printed as they
are run.  This change skips printing the check for libcrypto unless the
check actually fails.  This prevents the error from being displayed when
there isn't actually a problem.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I9ef36c0b64f7cd69d19b8faabd165ef6651c838e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-09 16:16:55 +00:00
Arthur Heymans efdcb4634a cbfstool/linux_trampoline: Fill the ACPI RSDP entry
With LinuxBoot Linux relied on the legacy method of fetching the RSDP
pointer to get ACPI. This uses a more modern approach available since
2018 on the Linux kernel, which involves filling in the zero page.

This method takes precedence over any other method of fetching the
RSDP in Linux (UEFI, Kexec, Legacy/BIOS). Some UEFI zealots are
threatening that legacy code will be removed from Linux so it's best
to already adapt to that possibility.

Tested on Qemu:
- With qemu the RSDP is always in the EBDA, so checking if Linux uses
  the provided pointer is better done with a forced bad entry
- With a fake bad pointer Linux correctly does not find RDSP

Change-Id: I688b94608b03b0177c42d2834c7e3beb802ae686
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-09 14:21:26 +00:00
Zheng Bao 4df5af87be amdfwtool: Clear struct match before regular expression matching
If it is not cleared and the number of strings is fewer than last
iteration, the match[3] will keep the last value, which actually
should be empty.

Add assert to make sure the level is a legal value.

BUG=b:222038278

Change-Id: If14e0923fbb1648d83784eb5dc1411c93227db5a
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-09 14:02:21 +00:00
Julius Werner 69cc557cfb commonlib/bsd: Remove cb_err_t
cb_err_t was meant to be used in place of `enum cb_err` in all
situations, but the choice to use a typedef here seems to be
controversial. We should not be arbitrarily using two different
identifiers for the same thing across the codebase, so since there are
no use cases for serializing enum cb_err at the moment (which would be
the primary reason to typedef a fixed-width integer instead), remove
cb_err_t again for now.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Iaec36210d129db26d51f0a105d3de070c03b686b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-09 02:18:21 +00:00
Karthikeyan Ramasubramanian f53214677c util/spd_tools: Encode SDRAM min cycle time (TCKMinPs)
ADL encodes CK cycle time as tCKMin whereas Sabrina encodes WCK cycle
time. Encode tCKMin as per the respective advisories.

BUG=None
TEST=Generate the SPD and ensure that tCKMin is encoded accordingly.
Minimum CAS Latency time is also impacted and is encoded accordingly.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I99ada7ead3a75befb0f934af871eecc060adcb26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-03-08 23:46:50 +00:00
Jeff Daly abd4b96eb4 util/ifdtool: Add support for Denverton SoC
Denverton is a special version of IFD2 flash layout.  It defines
10GbE firmware regions (11/12) and the IE (10) region which
other IFD2 platforms do not have.  Denverton does not include the
legacy GbE region (3) or the EC region (8) which other IFD2
platforms do have.

TEST='ifdtool -p dnv coreboot.rom' and verify correct output

Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
Change-Id: I15939ce4672123f39a807d63c13ba7df98c57523
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-08 15:03:39 +00:00
Martin Roth 1fcf78cc8e util/docker/coreboot-jenkins-node: Alphabetize installed tools
It's easier to read and to add new packages when each package is on its
own line and they're sorted alphabetically.

Indenting them also makes it easier to see what's getting installed and
what's a command.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ibfe297bd408ed0783fcff09c1ecb5672fe785c48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62446
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-02 13:09:55 +00:00
Martin Roth c8a1195b77 util/docker/coreboot-jenkins-node: add linkchecker
The linkchecker tool is now being used to find broken links in our
websites.  Since it's not needed for building anything, just add it to
the jenkins-node Dockerfile instead.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Iac2246b5378e556b5cd9f2107fc5a7e51d583b5b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62445
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-02 13:09:40 +00:00
Felix Singer 2060bff9c0 utils/cbfstool: Fix building with `make test-tools`
The variable `RM` is empty and thus set it to `rm`. While
executing the `clean` rule, run each `rm` command with the -f flag
to ignore non-existing files.

Also, disable the objutil feature locally fixing another build issue.

Change-Id: Icb17e2c924ef480f8ac6195f96cf495709a0a023
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62415
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-27 18:29:24 +00:00
Martin Roth e61e7789c2 util/testing: Add cbfstool tools to tested utils
Previously, cbfstool was tested as part of the coreboot build, but not
tested individually. This let a change that broke elogtool slip through.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I9e7b7a01d4a77ffdac932ba5af12cbd1ba96628b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-02-27 02:21:23 +00:00
Martin Roth e3e965b13d Revert "util/cbfstool: Port elogtool to libflashrom"
This reverts commit d74b8d9c99.

This change breaks the 'make all' build of the cbfstool tools
from the util/cbfstool directory unless libflashrom-dev is
installed, complaining that flashrom is not installed.

Even with libflashrom-dev installed, it breaks building
elogtool with the public version of libflashrom-dev.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I572daa0c0f3998e20a8ed76df21228fdbb384baf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62404
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-26 01:24:17 +00:00
Elyes HAOUAS a0b8032279 crossgcc: Upgrade LLVM/clang from 12.0.0 to 13.0.1
Build/run not tested on board.

Change-Id: I8c550d3528a5b1c891b318c08ecfba3a9255e69c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59400
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-02-25 00:44:10 +00:00
Zheng Bao fdb0294846 amdfwtool: Check the real length of PMU string
The length should be checked before the PMU_STR_INS_INDEX(th) character
is accessed, otherwise it is going to an access violation.

Change-Id: I8b59eb34e1cb01fd6e2571fcebc28ef2084b6ec4
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-24 00:41:45 +00:00
Felix Singer 88ccd4863c util/nixshell: Add a Nix shell for building documentation
Add a Nix shell config allowing to build the coreboot documentation.

Change-Id: I1c9715c677342241b78fbdef0afeb4536f48d50f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-02-22 10:31:41 +00:00
Zheng Bao e220faa18a amdfwtool: Add entries for PMUI & PMUD with instance 2
Change-Id: I69c4b3cdd2473655064d1329d5319cffdba2425a
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
2022-02-21 23:48:57 +00:00
Zheng Bao 990d154898 amdfwtool: Add support for AMD's BIOS A/B recovery feature
The rom layout for A/B recovery:
EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A
              0x4A -> PSP L2 B -> BIOS L2 B

The coreboot doesn't implement the AMD's A/B recovery. This is only
for the ROM layout. To save some flash space, the entire B section can
be eliminated.

To enable A/B recovery in PSP layout, add "--recovery-ab" to
amdfwtool.

TEST=Majolica(Cezanne)

Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-21 23:47:20 +00:00
Zheng Bao 1a9e54302b soc/amd/*/fw.cfg: Remove the misleading name for PMUI and PMUD
Add the information of substance and instance in the string for PMUI
and PMUD. It is amdfwtool's job to extract the number from the string.

Change-Id: I43235fefcbff5f730efaf0a8e70b906e62cee42e
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-02-21 21:29:50 +00:00
Felix Singer 3a5e6f529c util/liveiso: Use programs.flashrom.enable
NixOS 21.11 introduced the option `programs.flashrom.enable`. The option
allows installing flashrom and hooking up its udev rules. Thus, set it
to `true` and add the user `user` to the `flashrom` group allowing it to
use the programmers.

Change-Id: I017ddb4314702a5252dfc0d05cd1e4961043d23b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-02-21 15:25:18 +00:00
Elyes HAOUAS e854b0b5e7 crossgcc: Upgrade CMake to 3.22.2 version
Change-Id: I4272f72dd6ed686dbad5615a0ab44c8c632b5930
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-02-21 08:05:48 +00:00
Karthikeyan Ramasubramanian e1d6f5b80d util/spd_tools/spd_gen/lp5: Encode Bank Architecture
ADL supports 8B Bank Architecture, whereas Sabrina supports either BG or
16B Bank Architectures depending on the speed. This influences SDRAM
Density and Banks, SDRAM Addressing bytes in SPD. Encode them as per the
individual SoC advisories.

BUG=b:211510456
TEST=Generate SPDs for Sabrina.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ic854ccccb2b301e75d0f28cd36daf87fd41e07e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-17 21:43:29 +00:00
Karthikeyan Ramasubramanian 3248db0e5a util/spd_tools/spd_gen/lp5: Encode Optional SDRAM features
ADL and Sabrina provide different advisories to encode Optional SDRAM
features (byte indices 7 & 9). Encode those bytes as per the respective
advisories.

BUG=b:211510456
TEST=Generate the SPD binaries for Sabrina.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Icac8ae148458162768a919d9690d7bf96734e6c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-17 21:43:10 +00:00
Matt DeVillier 1dc1a56a5d util/chromeos/crosfirmware: format with shfmt
Clean up formatting using shfmt

Change-Id: I46ce84668bfb4ea3df179317e2848b6bb75d8d5c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2022-02-15 23:43:55 +00:00
Felix Held 72236b475f util/amdtools/README,description.md: add update_efs_spi_speed docs
This change is mostly from CB:56644 patchset 3.

Signed-off-by: Martin Roth <martin@coreboot.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Idece950bab260a099c9790485805cbe8ea641666
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-15 23:32:52 +00:00
Felix Held f57bf3f994 util/amdtools/description.md: add description for the different tools
This change is mostly from CB:56644 patchset 3.

Signed-off-by: Martin Roth <martin@coreboot.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4cb9bbb3d7fd5d7c9e33fbf656301c0beb2f1b47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-15 23:32:37 +00:00
Felix Held 6198a8213a util/amdtools/README: convert to markdown
This change is mostly from CB:56644 patchset 3.

Signed-off-by: Martin Roth <martin@coreboot.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Idcee9de9bc409a4dfe7d2f8c18ec5132f2747c33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-15 23:32:09 +00:00
Michał Żygowski 8ac40f3ea7 util/inteltool: Add support for Tiger Lake chips detection and GPIOs
Add PCI IDs for Tiger Lake LP and Tiger Lake H devices and their GPIO
tables.

TEST: dump GPIOs on i5-1135G7, Tiger Lake H untested

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I6071a999be9e8a372997db0369218f297e579d08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-02-15 19:44:08 +00:00
Zheng Bao 6c5ec8e31c amdfwtool: Add options to support mainboard specific SPL table
For the generic board which uses Cezanne, we use the generic SPL
table. For the Guybrush Chromebook, we need to use a customized SPL
file.

BUG=b:216096562

Change-Id: I385b0fe13cb78a053c07127ec3ea1c61dc42c7e4
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-12 16:36:07 +00:00
Benjamin Doron 39cf79900f util/inteltool: Actually read SATA init data from SIRD
Fix issue where registers always seem to contain their own offset.

After writing the desired register into SIRI, the requested data is
returned in SIRD. This register is 4 bytes after SIRI, commonly 0xA4.

Tested on TGL-H (SATA SIR registers are common), genuine data is
returned.

Change-Id: I322b11d53178e5b64e353c1b4e576548592c16c3
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2022-02-12 11:29:33 +00:00
Matt DeVillier b0844490db util/chromeos/crosfirmware: Handle "broken" recovery images
Several recovery images for newer ChromeOS boards fail in
extract_partition() due to parted detecting that there are overlapping
partitions, and therefore failing to print the partition layout
(this is potentially a parted bug; requries further investigation).

To work around this, fall back to using fdisk, making the assumption
that ROOT-A is always partition #3, and calculate the partition
start and size using the sector size.

Test: successfully extract coreboot firmware images from recovery
images which previously failed to extract (fizz, octopus, volteer).

Change-Id: I03234170ba0544af9eb0879253f0a8e0e7bf33f5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2022-02-11 23:57:03 +00:00
Matt DeVillier e42731603e util/chromeos/crosfirmware: Fix handling of newer boards
Wile historically there was a unique recovery image for each Chrome OS
board/HWID (with matching names), this is no longer the case. Now,
multiple boards share a single recovery image, so adjust how the proper
recovery image is determined, and how the coreboot image is extracted from it.

Test: successfully extract coreboot images for older 1:1 boards (e.g. CAVE)
and newer 1:N boards (e.g. DROBIT)

Change-Id: If478aa6eadea3acf3ee9d4c5fa266acd72c99b7a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2022-02-11 23:56:47 +00:00
Julius Werner b8258bd2b9 util/cbmem: Add --loglevel option to restrict console printing by level
This patch adds a new --loglevel option to the CBMEM utility which can
be used either numerically (e.g. `cbmem -1 --loglevel 6`) or by name
(e.g. `cbmem -c --loglevel INFO`) to restrict the lines that will be
printed from the CBMEM console log to a maximum loglevel. By default,
using this option means that lines without a loglevel (which usually
happens when payloads or other non-coreboot components add their own
logs to the CBMEM console) will not be printed. Prefixing a `+`
character to the option value (e.g. `--loglevel +6` or
`--loglevel +INFO`) can be used to change that behavior.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I8458027083246df5637dffd3ebfeb4d0a78deadf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-11 23:56:13 +00:00
Wonkyu Kim 3922aa5c2c util/ifdtool: add generic `PLATFORM_IFD2` for early SoC development
`PLATFORM_IFD2` macro is more generic tag that can be associated with
early next SoC platform development which using IFDv2.

The current assumption is that newer SoC platform still uses the same
SPI/eSPI frequency definition being used for latest platform(TGL, ADL)
and if the frequency definition is updated later, `PLATFORM_IFD2' will
use latest frequency definition for early next SoC development.
And once upstream is allowed for new platform, platform name will be
added in tool later.

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I14a71a58c7d51b9c8b92e013b5637c6b35005f22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-09 14:19:47 +00:00
Karthikeyan Ramasubramanian 55ba8df28c util/spd_tools/spd_gen/lp5: Update BusWidth Encoding
ADL and Sabrina have different advisory regarding encoding the bus
width. Encode the bus width as per the respective advisories.

BUG=b:211510456
TEST=Build spd_gen and ensure that the bus width is encoded as expected.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ia12a5bd8f70a70ca8a510ecf00f6268c6904ec25
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-02-08 17:37:18 +00:00
Julius Werner 984d03c492 console: Add loglevel marker codes to stored consoles
In order to provide the same loglevel prefixes and highlighting that
were recently introduced for "interactive" consoles (e.g. UART) to
"stored" consoles (e.g. CBMEM) but minimize the amont of extra storage
space wasted on this info, this patch will write a 1-byte control
character marker indicating the loglevel to the start of every line
logged in those consoles. The `cbmem` utility will then interpret those
markers and translate them back into loglevel prefixes and escape
sequences as needed.

Since coreboot and userspace log readers aren't always in sync,
occasionally an older reader may come across these markers and not know
how to interpret them... but that should usually be fine, as the range
chosen contains non-printable ASCII characters that normally have no
effect on the terminal. At worst the outdated reader would display one
garbled character at the start of every line which isn't that bad.
(Older versions of the `cbmem` utility will translate non-printable
characters into `?` question marks.)

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I86073f48aaf1e0a58e97676fb80e2475ec418ffc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-07 23:28:37 +00:00
Zheng Bao ab84fd7605 amdfwtool: Add SPL support
SPL: Security Patch Level
The data in SPL is used for FW anti-rollback, preventing rollback of
platform level firmware to older version that are deemed vulnerable
from a security point of view.

BUG=b:216096562

Change-Id: I4665f2372ccd599ab835c8784da08cde5558a795
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-02-07 18:38:40 +00:00
Karthikeyan Ramasubramanian d5ae3f908a util/spd_tools/spd_gen: Add support for Sabrina SoC
Add support to generate SPD binary for Sabrina SoC. Mainboards using
Sabrina SoC are planning to use LP5 memory technology. Some of the SPD
bytes expected by Sabrina differ from the existing ADL. To start with,
memory training code for Sabrina expects SPD Revision 1.1. More patches
will follow to accommodate additional differences.

BUG=b:211510456
TEST=make -C util/spd_tools.
Generate SPD binaries for the existing memory parts in
lp5/memory_parts.json and observe that SPDs for Sabrina is generated as
a separate set without impacting the ADL mainboards.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I2a2c0d0e8c8cbebf3937a99df8f170ae8afc75df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-02-07 14:09:52 +00:00
Jeff Daly 3623eca525 util/ifdtool: Add additional regions for platforms that support them
Some Intel SoCs such as Denverton support additional SPI regions for
things like Innovation Engine firmware or 10GbE LAN firmwares

Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
Change-Id: Ia5a450e5002e9f8edee76ca7c2eede9906df36c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-02-04 20:11:10 +00:00
Martin Roth 1039d27856 util/crossgcc: Update this for normailze_dirs()
Currently, the function normalize_dirs() fails if the directories lib32
and lib64 don't exist.  That can be fixed by using an rm -rf on it
instead of rmdir.

The cmake build doesn't create those directories, so was showing a
failure message after the build was already completed.  That's fixed by
removing normailze_dirs() from the build_CMAKE() function.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Iea6e3ca57fb91ff1234be875861b27a78972d9ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-02-03 13:50:16 +00:00
Elyes HAOUAS f2a9c8d57c util/lint/checkpatch.pl: Use "git_command"
This is to reduce difference with linux v5.16.

Change-Id: I7abd4d8eed856eee841422515db2ff7f50ecd0a4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2022-02-01 17:34:28 +00:00
Elyes HAOUAS 18ef52083d util/lint/checkpatch.pl: Use "gitroot"
This is to reduce difference with linux v5.16.

Change-Id: I3bdf880c8b6068467665865b7cf1249d1047e833
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2022-01-31 17:46:49 +00:00
Elyes HAOUAS 249c4044c2 util/lint/checkpatch: Update "check for missing blank lines after declarations"
This is to reduce difference with linux v5.16.

Change-Id: I1b7bc2b4ec832f0abeda215c381856a5ec153883
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2022-01-31 17:46:40 +00:00
Elyes HAOUAS ac69049030 util/lint/checkpatch.pl: Update 'commit message line length limit'
Also add "coreboot" comment on our modification.

Change-Id: Ida58a92457e25bac7fb89bb5882e7647f388ec01
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2022-01-31 17:46:31 +00:00
Elyes HAOUAS 919b0c7d4d util/lint/checkpatch.pl: Remove unneeded whitespaces and fix some typos
This is to reduce difference with linux v5.16.

Change-Id: I4aa7abce83b41ccd5129717cd3bf85be19ec4807
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2022-01-31 17:46:22 +00:00
Elyes HAOUAS 48cb78b6d9 util/lint/checkpatch.pl: Use "perl_version_ok"
Also use '$minimum_perl_version'.
This is to reduce difference with linux v5.16.

Change-Id: I7c2f5d5c9853dc8ddc8f89a5e2edd6c8613ba790
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2022-01-31 17:46:13 +00:00
Elyes HAOUAS 96771bf92c util/lint/checkpatch.pl: Use "tabsize"
This is to reduce difference with linux v5.16.

Change-Id: Ifeb9c4406737fa24f9bd803af48d8b8d17654940
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2022-01-31 17:45:44 +00:00
Martin Roth 38c7314137 util/lint: Remove SuperIO from checkpatch spellcheck
Patch 423e9e0fc0: Documentation/lint: Use Super I/O instead of SuperIO
added the word SuperIO to the checkpatch spelling list.

There were unfortunately some issues with this.

1) This introduced a problem because the comparison is used in different
cases in different places.  The misspelled word is compared ignoring
the case, but when looking for the correct word, it looks through the
list for the misspelling in all lowercase.  When it couldn't find the
word "superio" in the list, the variable came back uninitialized.

2) The spellcheck feature isn't enabled in checkpatch unless the option
--strict is enabled, so this wasn't getting reported anyway.

3) SuperIO (or superio) will match the KCONFIG options such as
CONFIG_SUPERIO_NUVOTON_NCT5104D, and suggest "Super I/O" which doesn't
make any sense.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I464305af539926ac8a45c9c0d59eeb2c78dea17a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2022-01-31 03:34:30 +00:00
Fred Reitberger bfdc132436 util/lint/lint-stable-003-whitespace: add exception for gif files
Adding gif files to the whitespace exclude list, to prevent issue where
commits were failing due to binary files.

Change-Id: I56679780348579d01c81c6f1677e4ea456315c9e
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61460
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-01-28 20:36:38 +00:00
Elyes HAOUAS ad3828e3ce crossgcc: Update acpica from 20210331 to 20211217
Changes:
 Version 20211217: https://acpica.org/node/197
 Version 20210930: https://acpica.org/node/196
 Version 20210730: https://acpica.org/node/195
 Version 20210604: https://acpica.org/node/193

Change-Id: I3a03b74e95f910b50aa2f7ce502b1e9ad5b6df37
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2022-01-28 16:35:13 +00:00
Matt DeVillier 648a44acbc util/chromeos: Update extract_blobs script
- Handle older CrOS firmware which lacks a COREBOOT FMAP region
- Add support for all blobs used in CrOS firmware 2013 to current
- Put extracted blobs in their own directory

Change-Id: Idaa39eca3be68a9327cead9b21c35a6c7a3a8166
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2022-01-27 22:06:10 +00:00
Sean Rhodes 0015df5927 util/coreboot-configurator: Add contrib files
Add contrib files for:
* debian (Tested on Ubuntu 20.04, 21.10, MX Linux 21 and Debian)
* PKGBUILD (Tested on Manjaro 21)
* flatpak (Untested)

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie9f0193ed28c0842661426204fc88ec00091fbae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2022-01-27 16:17:42 +00:00