Update intel-sec-tools to commit of BootGuard support.
Remove --coreboot argument in src/security/intel/cbnt/Makefile.inc:
was removed as argument for cbnt
Change-Id: Iaf34bdb65a5f067d1d632e35d340b8fc49aaf318
Signed-off-by: Christopher Meis <christopher.meis@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55013
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Newest master includes these changes:
1. Introduce the FSP package for Elkhart Lake SKUs
2. Introduce the FSP package for Tiger Lake IoT SKUs
3. Update the FSP package to latest version for Apollo Lake,
Comet Lake and Tiger Lake (client SKUs)
You can get further 3rdparty/FSP commit history here:
https://github.com/intel/FSP/commits/master
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I96d147fec82d0fcd5c7748c277deb0672a975ceb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55228
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating from commit id e681c37:
change node locked version expectations
to commit id b38e3a63:
cros_ec: Use boot mode to check if EC can be trusted
Change-Id: Id6de185af85a61a3843b302fef6fa0d4d3c17aef
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55026
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit updates the vboot submodule from commit 57c0c5b:
cgpt: Move all GPT on SPI-NOR infra behind a flag
to e681c37:
change node locked version expectations
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Change-Id: Ifd130e3f66f1819f59f00703f0ad0c2278b544bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Updating from commit id 7ad39818b:
2020-10-12 09:16:21 +0000 - (Merge "mediatek: mt8192: add GIC600 support" into integration)
to commit id 96404aa27:
2021-05-13 18:27:27 +0200 - (Merge "build(hooks): update Commitizen to ^4.2.4" into integration)
This brings in 861 new commits.
Change-Id: I912545022e4320b86ab8a382144c02e315d0c835
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Now that Boot blobs have landed, need to uprev the qc_blobs.
Change-Id: I510de2d1e4334612c81f35a082dea92d445da0bb
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Some changes:
- bg-prov got renamed to cbnt-prov
- cbfs support was added which means that providing IBB.Base/Size
separatly is not required anymore. Also fspt.bin gets added as an
IBB to secure the root of trust.
Change-Id: I20379e9723fa18e0ebfb0622c050524d4e6d2717
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52971
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating from commit id 9d4053df:
2020-11-20 01:51:08 +0000 - (Revert "Reland: Clean up implicit fall through.")
to commit id 57c0c5be:
2021-04-09 11:45:39 +0800 - (cgpt: Move all GPT on SPI-NOR infra behind a flag)
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Id50a892f12ff3c4147c422c98b640ac047143128
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52453
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
mb/google/guybrush: Update APCB - disable debug
mb/google/guybrush: Add APCB to get through memory training
soc/mediatek/mt8192: Add EMI Settings of 8GB Normal Mode
soc/mediatek/mt8192: Update MCUPM firmware
soc/mediatek/mt8192: Add version info for SSPM
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I445d753c712670fe80efcdf29459736df2b76666
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Updating from commit id 3a9d7cd:
2021-03-03 15:37:08 -0700 - (picasso: Update Dali SMU firmware)
to commit id dded82f:
2021-03-23 15:36:36 -0600 - (picasso: Update Dali SMU firmware)
This brings in 2 new commits.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: If71e52a2a3e50aeb8599798de7b49bc71ed26a04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This includes the bg-prov tool.
Change-Id: Iba8efe3bcb67694da76ef78abaa0562d47f7850b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Updating from commit id a2390f3c5:
2020-12-01 08:35:44 +0000 - (servo_v4/usb_pd_policy: Reject SNK->SRC power swap if CC_ALLOW_SRC not set)
to commit id 1e800ac83:
2021-03-01 22:59:54 +0000 - (docs: point md files in master to main/HEAD)
This brings in 188 new commits.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I5c276d7839e0bdbf14ac56f16c231d75a6ea4c3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Updating from commit id 3b1a734:
2021-03-02 11:51:18 -0700 - (picasso: Update FSP to build 0x26)
to commit id 3a9d7cd:
2021-03-03 15:37:08 -0700 - (picasso: Update Dali SMU firmware)
This brings in 1 new commits.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Iff3b4ff667f97d3804bc66477f8a95a60e23b1a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51459
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating from commit id 4fdfa1c:
2021-03-05 13:10:22 -0600 - (mb/amd/majolica: Update to use proper APCBs built for Majolica)
to commit id fc2d4e2:
2021-03-12 10:31:48 -0700 - (mb/google/guybrush: Add initial APCB)
This brings in 1 new commit.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I3003fdb8ba0bcfbc33452999c35a9a21775ecc10
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Some of the previous binaries were incorrect and should not be used
for Majolica because they are templates instead of APCBs specifically
built for the board. This APCB update also places the UMA region under
4G and size 32 MB which is essential for video output.
TEST=Boot with UEFI BIOS and verify we can get to OS. Also verify memory
region size, base and alignment.
Change-Id: Id797e2ad5bd67815c09752aedc19dad7dcf8ad12
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Avoid a Secure OS Abort. This prevents coreboot timing out on C2P
mailbox commands and allows HDT unlocking.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I358530a1ba959ee1896e26a47853c9918ee124b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This adds the apcb binary for Bilby.
Change-Id: I1487369bc72734e875c5a701f27ed2d6af41cd01
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Updating from commit id a1afae4:
2019-10-02 11:47:45 +0000 - (juniper: initial setup)
to commit id a2390f3:
2020-12-01 08:35:44 +0000 - (servo_v4/usb_pd_policy: Reject SNK->SRC power swap if CC_ALLOW_SRC not set)
This brings in 4022 new commits.
Change-Id: Ib13921aa78a60f88455223eff602296abc424ca8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48212
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update submodule pointer to include microcode for CML-H and others.
Change-Id: Ide211b0b163f824a3cfa6500a73aea1e2176c652
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47914
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This pulls in the following changes:
* Drop geode_lx
* cpu/amd/model_fxx: Drop unused microcode
* cpu/amd/model_10xx: Drop unused microcode
* soc/mediatek/mt8192: Add dram.elf for DRAM full calibration
* soc/mediatek/mt8192: Add dpm binary
* soc/mediatek/mt8192: Add 4266Mbps flag for dpm & dram blob
* soc/mediatek/mt8192: add SPM firmware
* soc/mediatek/mt8192: Support 26M clock off in SPM
* soc/mediatek/mt8192: Add SSPM firmware
* soc/mediatek/mt8192: Add MCUPM firmware
* soc/mediatek/mt8192: Update MCUPM firmware
* soc/mediatek/mt8192: Support discrete DRAM modules
* mb/amd/majolica: Add APCB configuration files
Change-Id: I5c18349307421707fac71f392b785f3e2bef3acb
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
We missed that Cannon Point, the PCH usually paired with Coffee, Whiskey
and Comet Lake, differs a bit from its predecessors. Hence, libgfxinit
now has a new Kconfig setting for the PCH.
Change-Id: I1c02c0d9abb7340aabe94185ee5e17ef4c2b0d36
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add blobs from the 1.0.0.1 release of CezannePI-FP6.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Iebfbe819ed429a7aed1882964061e1bc98f3bc39
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add the newest SMU firmware and FSP blobs for the picasso project.
This supports Picasso, Dali, and Pollock devices.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I75e6f3d2a59ed8b2e42afba3a6978574373ec4e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Updating from commit id 9d4053d:
2020-11-20 01:51:08 +0000 - (Revert "Reland: Clean up implicit fall through.")
to commit id 48195e5:
2020-11-24 10:23:45 +0000 - (Makefile: Test for warning flags before using them)
This brings in 3 new commits.
Change-Id: I64f27f346df264cb6eeeb4e3203fcca7d35f7e83
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Updating from commit id 4c523ed1:
vboot2: Add support for modexp acceleration
to commit id 9d4053df:
Revert "Reland: Clean up implicit fall through."
This brings in 32 new commmits. Among the changes are restored support
for older GCC/clang versions that do not support
__attribute__((fallthrough)).
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I1110664bf71b4376bcdd9ba934a95031ba872c1d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This now tracks a recently created upstream repository located at
https://github.com/amd/firmware_binaries
BUG=b:166107781
Change-Id: Ib193d646bb51cbf7b86f46828033e619c3f70e16
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46594
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The 3 commits commits from the blob repository this patch pulls in
remove executable flags from files in the repo that shouldn't have those
flags set:
* pi/amd/00660F01/FP4/AGESA.bin: Remove execute file mode bit
* Remove execute permission from all binaries
* Remove execute permission from plaintext files
Change-Id: I9c2b7c69f07e46bac466bfbfb277595c9fbc5a5a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Updating from commit id 4bb06cc1:
COIL: Change denylist to blocklist
to commit id 4c523ed1:
vboot2: Add support for modexp acceleration
This brings in 10 new commmits.
Change-Id: Iff6eb99c8ed3046b6fdb6c1e2892aab956f3b562
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The patch incorporates the STM build as a part of the coreboot
build. A separate patch lists and documents the options that
the developer can use. In most cases the default options will
suffice.
Change-Id: I8c6e0c85edd4e2b0658791553bd9947656e8c796
Signed-off-by: Eugene D Myers <cedarhouse@comcast.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Updating from commit id fefcaa65:
vboot: adjust VB2_SECDATA_KERNEL_FLAGS in non-recovery path
to commit id 4bb06cc1:
COIL: Change denylist to blocklist
This brings in 20 new commmits.
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Change-Id: I0efef2f0ab6ecb89c8132cca2bd4ab7f71e85ced
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45299
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating from commit id ace23683b:
2019-09-27 Merge changes from topic "ld/stm32-authentication" into
integration
to commit id a4c979ade:
2020-08-26 Merge changes I6bf1db15,I8631c34a,Id76ada14 into integration
This brings in 1825 new commits.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Id26301dae421eec61c10a2d18842053f3228c557
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44885
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating from commit id 3932b1c:
2020-08-19 02:09:04 +0000 - inclusive: change usage of
blacklist/whitelist
to commit id fefcaa6:
2020-08-24 04:32:03 +0000 - vboot: adjust VB2_SECDATA_KERNEL_FLAGS in
non-recovery path
This brings in 2 new commits.
Change-Id: Ia3ff764537b91f76ba6fa3ba2646638964800510
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
This also includes https://chromium-review.googlesource.com/2318026
which fixes an issue with duplicate symbols.
Change-Id: Icf450616b3bcd8b7c01261c913cd172625dbd6ba
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Raul E Rangel