So far all group and community definitions live in one big c file.
This 2500 line file slowly grows to a size, where readability is lost.
Also the definitions are not reusable in a potential libinteltool.
This commit moves the Cannon Lake definitions into its own header.
Change-Id: I5991c3cebba0e05504940ae66fa7bb63bf280ab1
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38626
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christoph Pomaska <github@slrie.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
So far all group and community definitions live in one big c file.
This 2500 line file slowly grows to a size, where readability is lost.
Also the definitions are not reusable in a potential libinteltool.
This commit moves the Ice Lake definitions into its own header.
Change-Id: I5735f12480091a9b6c5e5c103a1ca7b7b1f3f997
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38625
Reviewed-by: Michael Niewöhner
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christoph Pomaska <github@slrie.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This GPIO dumping was implemented using the
Document Number: 341080-001
Intel® 495 Series Chipset Family On-Package Platform Controller Hub
Volume 1 of 2
datasheet. The GPIO community ports can be found in table 36-1, while
the community and pin descriptions are taken from
linux/pinctrl/intel/pinctrl-icelake.c .
This commit was tested on the late 2019 Razer Blade Stealth with 1065G7
and Chipset 495 PCH and the output manually compared against
linux/pinctrl-intel.
Change-Id: Ib40f1dbae57169678e92ea9ad0df60ff91b5b22c
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Sunrise Point-LP is used on Skylake and KabyLake platforms,
but the PCH IDs differ.
This commit adds the PCH IDs for Skylake mobile platforms
and renames the Kabylake macros to distinguish them.
Used Intel documents:
- 332995-001EN (I/O datasheet vol. 1)
- 332996-002EN (I/O datasheet vol. 2)
Change-Id: Id46224fcc44b06c91cbcd6c74a55c95e1de65ec6
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Values from
- Intel doc 337347 rev4
- coreboot soc/intel/cannonlake/include/soc/gpio_soc_defs_cnp_h.h
On Coffeelake H (using Cannonlake / Cannonpoint PCH) p2sb is not
accessible. Using a static value instead. 0xfd000000 is a common value
chosen by coreboot and non-coreboot firmware.
Change-Id: Id637f703ab0a99eb0908ecdc3da27ba80db1c6b8
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Apollo Lake has four GPIO communities each with a single group named
after the physical location of the pads (I guess): North West, North,
West and South West.
Also add some logic to be able to tag the default function of a pad
(with an asterisk before its name). This seems easier to review in the
tables, but we could also encode the number of the default explicitly
instead.
Used Intel documents:
- 334817-001 (datasheet vol. 1)
- 334819-001 (datasheet vol. 3)
Change-Id: I5cd687fdc1d2ae81f2e948178bf319897b47f031
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Johanna Schander