If mmu_init is called more than once then, free_idx should be reset to
1. Here, the assumption would be that mmu_init will not be called more than
once. However, this is not necessarily true. Thus, free_idx should be reset to 1
every time we are initializing ttb from scratch.
BUG=None
BRANCH=None
TEST=Compiles sucessfully and boots to kernel
Change-Id: I5ac0af43346a492583380b0f15101390fc98d182
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 398a68c3b08d82cfa521d235af2c1922629bdf56
Original-Change-Id: Idb7424df7dd577f263f12d1527dbd7fb89216d40
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/216906
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9068
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Rush builds were throwing a _sync_sp_el0 exception due
to commit 65af2f3d (tegra132: support arm64 SMP bringup).
Fixed by copying over the rush_ryu devicetree.db, which
adds all the CPUs to the device tree. Basically the same
as commit 8f61ca2da but for rush.
BUG=None
BRANCH=None
TEST=Booted rush OK, brought up rush kernel from USB.
Change-Id: Ia91260ed36364ae1cfdd28932f09df9486c7e638
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 649391a402527cef1465d5a948323ad95c77917d
Original-Change-Id: Ic9e34494ec8e6ad82e6020df6ad6fecd8763ac7e
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/217792
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9067
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
If there are no devices underneath a device in a devicetree the
bus pointer in a struct device is NULL. Check for this condition
before proceeding in walking through the children devices.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Ran through coreboot w/o any devices under the cpu_cluster device.
No more exceptions.
Change-Id: I9aedbc0dffc638b878bd0ffacfa318b6eb30d504
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d21e181077eba3c5ee03afca1738a24c21a8fc19
Original-Change-Id: I891aeb36319dce67ce9e431156c85c74177c7ab7
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/217511
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9066
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Instead of relying on config variables to determine the current el, use
{read/write}_current macros for accessing registers.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Compiles successfully and boots to kernel login prompt
Change-Id: I6c27571fa65e06e28b71fee3e21d6ca93542e66b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 96aed53b2879310f6f979d5aa78b8d1df7f04564
Original-Change-Id: If4a5d1e9aa50ab180c8012862e2a6c37384f7f91
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/217148
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9065
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Allow read/write to registers at a given el. Also, make read/write registers at
current el call this newly added function.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Compiles successfully
Change-Id: I98f35b8d3eb5e292ac895102ad91b675325c08c7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 11d90df1fd92e03c25bfc463429a5f6a8d9d411d
Original-Change-Id: I17de4c4f3bc1ee804422efe5f4703b4dd65b51f2
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/216904
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9063
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In order to ease the process of reading and writing any register at current EL,
provide read_current and write_current assembly macros. These are included in
arch/lib_helpers.h under the __ASSEMBLY__ macro condition. This is done to allow
the same header file to be included by .c and .S files.
BUG=chrome-os-partner:30785
BRANCH=None
TEST=Compiles successfully
Change-Id: I51749b6e4ae7b1ffbaae28d915cd100a28959f26
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c11c7287f507fa398cbbee75abc2bd11140ef19b
Original-Change-Id: I1258850438624abfe3b1ed7240df0db0e7905be6
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/216373
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9062
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Nvidia tracks their MTS versions using decimals. Update
the format so there isn't an extra step in communicating
versions while debugging things.
BUG=chrome-os-partner:31864
BRANCH=None
TEST=Booted and confirmed decimal print out.
Change-Id: I8d8b8a6e9b80548509dd8a30abb17c9970afdead
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b7deb04a1deed41e1a54713320a29f6731401b35
Original-Change-Id: Ia7d0bc49318a4b4c969ee37e762e084ec65de543
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/217260
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9061
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Now that there is cpu devicetree support retire the
bring_up_secondary_cpu option as the devicetree is the
way going forward to do other CPU bring up.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built and booted with 2nd core.
Change-Id: I3e8812cd2183f2126c11c36ff4844c15b3cbfc1b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7eab33b763d33d6be210ddb69e3c67411bad0fd0
Original-Change-Id: Ic213fbf56a1846e73462886f876a0a70e48b3158
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216929
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9060
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Now that arm64 and tegra132 has cpu devicetree support stop
using the bring_up_secondary_cpu option.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built and brought up 2nd core.
Change-Id: I3ffca6c1fa0932d8aafea30a160608b5593ae154
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c45b22ce9fd0345c3e599fd814993db66e2b96cc
Original-Change-Id: I210bea73f8249de15f99d0c062600e789184eefd
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216928
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9059
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Two weak functions were added so that architecture specific operations
on each segment of payload or stage can be performed.
Each architecture must define its own operations, otherwise the
behavior will default to do-nothing functions.
This patch has been updated by to fit more in line with
how program loading is currently being done. The API is the
same as the original, but all call sites to stages/payloads
have been updated. This is known to break any archs that use
rmodule loading that needs cache maintenance. That will be fixed
in a forthcoming patch. Also, the vboot paths are left as is
for easier upstreaming of the rest of the vboot patches.
Original-Change-Id: Ie29e7f9027dd430c8b4dde9848fa3413c5dbfbfa
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/239881
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
(cherry picked from commit c82c21ce87a4c02bd9219548a4226a58e77beef0)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ifcee5cd9ac5dbca991556296eb5e170b47b77af7
Reviewed-on: http://review.coreboot.org/8837
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This change also depends on mrc due to changes in pei_data.h
Report smbios type 17 for each memory
CQ-DEPEND=CL:210005
BUG=None
BRANCH=None
TEST=Compiles successfully
See smbios type17 in OS by dmidecode
Original-Change-Id: If83c99364726cd17c719a59ed8ac993736c63b9a
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/210399
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
(cherry picked from commit 6da6b4ffb3a45fdd766b88220c2adb168b3c5e10)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I39ea9ef9b342239fe26846ab0a928f6a680c21e8
Reviewed-on: http://review.coreboot.org/8956
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add smbios type 17 which can optionally be implemented
at the platform or mainboard level
In order to create SMBIOS type17, you will need to fill
memory_info data
BUG=None
BRANCH=None
TEST=Compile successfully on rambi and samus
Boot to chromeOS on samus and rambi
Original-Change-Id: Ie4da89135c879d7a687305d423103fcfcbb96e3f
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/210005
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
(cherry picked from commit 634b899ba41242caa800d7b570f3a339c738db77)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I61d1e8b1d32d43f0011b0f93966d57646ea0eb63
Reviewed-on: http://review.coreboot.org/8955
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Commit f69a99db (coreboot: x86: enable gc-sections) overrides
CFLAGS_x86_32, which looses (among other things) -m32, which
in turn breaks the build with the standard distro gcc on a
x86_64 machine.
Fix it by appending the new flags instead.
Change-Id: Ic3409a1aaa5b26139847258a7eb5c3468efdc6a3
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/9053
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
The static gpio_t initializers are stylish, but they are still a little
too annoying to write and read in day-to-day use. Let's wrap that in a
macro to make it a little easier to handle.
BUG=None
TEST=None
Change-Id: If41b2b3fd3c3f94797d314ba5f3ffcb2a250a005
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 102a5c0a800f43d688d11d1d7bbc51e360341517
Original-Change-Id: I385ae5182776c8cbb20bbf3c79b986628040f1cf
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220250
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9052
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This updates timer.h to #include the header necessary for u32,
and to change the one instance of uint32_t to u32 to be uniform.
BUG=none
BRANCH=none
TEST=compiled
Change-Id: I4d67045206fd94985774b8d46a307bbb2e337f30
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4ff2629fdf3c69c203fa61ec894bb4895990cb5e
Original-Change-Id: Ie406fb1f518af5d1fd1e623630b2bcbbef35622c
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220612
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9051
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This adds a mainboard-specific bootblock function that will be used
to set up some board-specific parameters which are currently set up
in the SoC bootblock function.
BUG=none
BRANCH=none
TEST=built and booted on Pinky
Change-Id: I86c90f7ade824fb9d6b71ca3349d1ce9eb4772fe
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 03e0bb2eaca7a54c3df95b21d856ef4114d3c833
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: Ibee7076ebd6080f04b0697067e85ce8b6b2230e4
Original-Reviewed-on: https://chromium-review.googlesource.com/220399
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9050
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The Serial Peripheral Flash Interface (SPFI) block allows
communication with various devices over the SPI bus.
It uses a configurable transaction interface and it clocks
the bus according to the configured command, address, gap (aka
dummy) and data lengths.
This controller requires the SPI_ATOMIC_SEQUENCING flag set
(write and read done in the same transaction) as it cannot
directly control CS and will assert/de-assert CS at the
beginning/end of a transaction itself.
Note that the size of any transfer cannot be greater than
64KB - 1, as this is configured in a 16-bit field.
The SOC has 2 SPFI interfaces each of them providing 5 slave select
lines. SPFI 0 supports single and dual modes, SPFI 1 supports
single, dual and quad modes.
For SPFI interface 0:
- The block needs the system PLL and the following top level
SPI clock registers to be set:
- CR_cr_top_spi0clkinternal_CTRL[2:0] with division value
- CR_MIPS_CLOCK_GATE[19]: bit cr_top_SPI0CLKOUT_MIPS set
- CR_cr_top_SPI0CLKOUT_CTRL[6:0] with division value
- The following MFIO configuration parameters are also required:
Signal name Pad name MFIO mode
spim0_d0_txd MFIO_MIPS_10 0
spim0_d1_rxd MFIO_MIPS_9 0
spim0_mclk MFIO_MIPS_8 0
spim0_cs0 MFIO_MIPS_2 1
spim0_cs1 MFIO_MIPS_1 1
spim0_cs2 MFIO_MIPS_55 1
MFIO_MIPS_28 1
spim0_cs3 MFIO_MIPS_56 1
MFIO_MIPS_29 1
spim0_cs4 MFIO_MIPS_57 1
MFIO_MIMPS_30 1
For SPFI interface 1:
- The block needs the system PLL and the following top level
SPI clock registers to be set:
- CR_cr_top_spi1clkinternal_CTRL[2:0] with division value
- CR_MIPS_CLOCK_GATE[20]: bit cr_top_SPI1CLKOUT_MIPS set
- CR_cr_top_SPI1CLKOUT_CTRL[6:0] with division value
- The following MFIO configuration parameters are also required:
Signal name Pad name MFIO mode
spim1_d0_txd MFIO_MIPS_5 0
spim1_d1_rxd MFIO_MIPS_4 0
spim1_mclk MFIO_MIPS_3 0
spim1_d2 MFIO_MIPS_6 0
spim1_d3 MFIO_MIPS_7 0
spim1_cs0 MFIO_MIPS_0 0
spim1_cs1 MFIO_MIPS_1 0
MFIO_MIPS_58 1
spim1_cs2 MFIO_MIPS_2 0
MFIO_MIPS_55 2
MFIO_MIPS_31 1
spim1_cs3 MFIO_MIPS_56 2
spim1_cs4 MFIO_MIPS_57 2
BUG=chrome-os-partner:31438, chrome-os-partner:32441
TEST=Tested as bare-metal driver on Pistachio FPGA
Change-Id: I3b3e4475976e6fba58cef93b12d997ec5cb26341
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 621849942e27f7d6cf2c8ade7f2c4d18d2318b91
Original-Change-Id: Ib257eb6236bd2895281175871b4ab979660f1239
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/217320
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/9049
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Danube has become Pistachio, let's rename all instances where this SOC
is mentioned.
BUG=none
TEST=board urara still builds
Change-Id: Iea91419121eb6ab5665c2f9f95e82f461905268e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 58696cc7c77a70dca2bfd512d695d143e1097a78
Original-Change-Id: Ie5ede401c4f69ed5d832a9eabac008eeac6db62d
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/220401
Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: http://review.coreboot.org/9048
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Not much is happening yet, when the board is enabled (in the next
patch), all three components build successfully, the map files show
them placed where expected and the bopotblock is wrappeed in a BIMG
header.
BUG=chrome-os-partner:31438
TEST=when config is enabled, emerge-urara coreboot succeeds. more
extensive testing to come later
Change-Id: Ib7396189f4bee0fdd6a8ce5c9ab1277806cb5dcc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1ca9efe59a7fcb99412410d509a7f9a91b6ef3ec
Original-Change-Id: I573cfb70f5c1e612dfa0a55d3d22d92f00584c66
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214600
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9047
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The original purpose of soc_secondary_cpu_init() was to provide
a way for the SoC to run code on the secondary processors as
they come up. Now that devicetree based bringup is supported
there's no need to have this functionality.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Booted SMP into linux.
Change-Id: I6fa39b66a8b728d9982b0721480b7fae45af7c6e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1356ec527e2bc61043ccd7dea4a7ff5182b16f3e
Original-Change-Id: Ie5c38ef33efadb2d6fdb2f892b4d08f33eee5c42
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216927
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9044
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Use the formal devicetree way for bringing up each of
the cpus. This includes providing a cpu_driver as well
as calling arch_initialize_cpus() with the proper
operations to start the cores.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Booted SMP on ryu.
Change-Id: I276fe08916bc0c46c8f4dd30e47c7d9b135e2bbd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 038daec1b74f4c414ab7ad153d34e48d4644183a
Original-Change-Id: I13d8bfd645abf66f270d56d48eff4331c4ea1200
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216926
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9043
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
There are some ARMv8/ARMv4 SoC where the ARMv8 part needs to be
SMP aware but the ARMv4 part does not.
Until we need real SMP on ARMv4, work around that situation
with stub defines.
Change-Id: Iec5b4302b19c17fe2b3f677b84a8edf4b4902946
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9046
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This adds SMP bring up support for arm64 cpus. It's
reliant on DEVICE_PATH_CPU devices in the devicetree.
Then for each enabled device it attempts to start then
initialize each CPU. Additionally, there is a cpu_action
construct which allows for running actions on an individual
cpu.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Booted both cores on ryu into linux.
Change-Id: I3e42fb668034c27808d706427a26be1558ad2af1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a733fd566a8e5793da5ff28f9c16c213f411372e
Original-Change-Id: I407eabd0b6985fc4e86de57a9e034548ec8f3d81
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216925
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9042
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Provide a simple spinlock implentation for arm64. A value
of 0 is unlocked and a value of 1 is locked.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built and ran SMP bringup on ryu.
Change-Id: Ie88a715a6b51cd38a5fdd830583dae528cc49d67
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 14dab94610c96d6b1530c64d661833f8e613101c
Original-Change-Id: I3bf2d80b91112d04442455ff0fa3f16900b7327f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216923
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9040
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The spinlock header file was not residing in the correct place.
It needs to live under 'arch/smp'.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built with SMP. spinlock.h found.
Change-Id: Ie0e974674a6ea8ec769ca0ce64eb888c4d094652
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 50079befdc3d43306e4ae9e543f7266f1ac99aa0
Original-Change-Id: I0e594cacfafcd6f30802c9563785ca09a2f7a2af
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216922
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9039
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The load-acquire/store-release operations (including exclusive
variants) form a basis for atomic operations. Also remove
the dmb, dsb, and isb functions from lib_helpers as barrier.h
already included these. Lastly, utilize barrier.h.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built and ran SMP bringup using barriers.
Change-Id: I6304a478d769dc2626443005b4eec4325d8a06f4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8fac8d46b09d449d59f1b4f492d363392dcc4118
Original-Change-Id: I77ff160c635297a2c7cab71cb0d3f49f2536f6ff
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216921
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9038
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
printk() shouldn't be called until the consoles have been
initialized. This just so happened to work by luck. Once
CONFIG_SMP is enabled that breaks because of spinlock
usage in uncached memory.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built with CONFIG_SMP and ramstage doesn't hang early.
Change-Id: I54231db3c811c0d19c5c7fbaa406cacd1ff019ec
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 31c3f972ac5c89472009b5b2cb7dbc0f02cfd9a0
Original-Change-Id: I6091b1e949e648b3435231946e5924260bf1807f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216920
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9037
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
printk() shouldn't be called until the consoles have been
initialized. This just so happened to work by luck. Once
CONFIG_SMP is enabled that breaks because of spinlock
usage in uncached memory.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built with CONFIG_SMP and ramstage doesn't hang early.
Change-Id: I4bf5d98e409840cf07a7759e9273d770f3bbf8bb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6ec672e52eda69f2b5abb747807a496bb973088f
Original-Change-Id: I247caac410894fb896dfb25a27c3a3213ef7f020
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216429
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9036
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add all the CPUs to the device tree.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Brought up 2nd core on ryu in kernel.
Change-Id: I4cc51f30897e3bd6c1b275a95d5da34ce7ae320e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 485de634a49d606dc6e7168f047eb9365e26415f
Original-Change-Id: I682f23a9b68f49206aa99d55e800540d8d0f8900
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216426
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9034
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Instead of directly using the clk_src_id based on enum for clock source, every
device needs to have its own set of clk source ids defined. This prevents
accidentally selecting a wrong clk source if the ids are different from host1x's.
Also, clk_src_id is separated from clk_src_freq_id. clk_src_id is the clk src id
represented in CLK_SOURCE_<dev> registers, whereas clk_src_freq_id is used for
handling the common clock sources based on id to get the proper frequency in
software.
[pg: integrated a later commit to fix the build]
BUG=chrome-os-partner:31821
BRANCH=None
TEST=Compiles successfully and boots to kernel prompt
Change-Id: I5d40fb49b81e8838b2be071d32c466213215e0d6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 27d5d6a34d1c826c6095c18368efb78c228d4ca8
Original-Change-Id: I5c88bed62841ebd81665cf8ffd82b0d88255f927
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/216761
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Id: 13c30c50a9e8a7f3c48673a2f6c144ba546129b6
Original-Change-Id: I6659858c24e925aec9495bf64344c0000ad19b4c
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/217342
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9033
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Provide access to the MIDR_EL1 register to obtain the
main id for determining CPU implementer and part/revision
information.
BUG=chrome-os-partner:31761
BRANCH=None
TEST=Built and printed the output of this function on ryu.
Change-Id: I42cec75072fc5e8b48f63c1971840fdc415e4326
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ad19ffe629d9f16b8fd07051ce73533e97fb3f5c
Original-Change-Id: I8b8506ebff8e6f9d7c4f96d7ff7e21803972961e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216423
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9032
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This function is breaking display bring up in the kernel. While
this functionality may be needed it's not until there is a
necessity to beep and/or bring up the display in firmware.
BUG=chrome-os-partner:31820
BRANCH=None
TEST=Sean ran with this patch and the display indeed did come up.
Change-Id: I5cf8a6c6e6941ee138991933215f96f5562382be
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 038bc1d53028409d0640c78fb62c7025ba12dcb9
Original-Change-Id: I833d66a0e63e04118b130b6803a7a3b68c802148
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/216421
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9031
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
These are not needed/were never really used. SDRAM init will now
be done in sdram.c, not the BootROM.
BUG=chrome-os-partner:29921
BUG=chrome-os-partner:31031
BRANCH=None
TEST=Built rush_ryu AOK.
Change-Id: Id046592415574badb97026224e1e525c174eece4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: aab1045817125cb022c8e8b89b85ef14e581baa7
Original-Change-Id: I7d25de3e888bb24e4c6e6dea2726510c97fe1730
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/215863
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9030
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Expanded sdram.c to add support for LPDDR3 init. This code can
be used with matching BCT .inc files to have LPDDR3 SDRAM
initialized by coreboot instead of the T132 BootROM.
BUG=chrome-os-partner:29921
BUG=chrome-os-partner:31031
BRANCH=None
TEST=Built for rush and rush_ryu.
Change-Id: I53801d9399dbf67fd86d0a2521174f0668567620
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 60e130c47c1894925a12f251af5b83a1fa144d57
Original-Change-Id: I6bcffcd22d2e4f8da6d729b6757714657f3f6735
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/214753
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9029
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The power button signal is driven from the silego part.
It's active high when the button is pressed.
BUG=None
BRANCH=None
TEST=Booted with power button pressed. vboot saw the press and
requested a shut down.
Change-Id: Ifff1bd8d4340849e0c218812fd401b61c90c5743
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b6bd7c0de38e1078b85f1671493c6d2948d43149
Original-Change-Id: If25ebce28c1ab5a363f3b4b5ab9fc24baebad56a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214847
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9028
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Instead of calling out the gpio index and port numbers use
real names. It's semantically clearer and there's only one
place to adjust the hardware values.
BUG=chrome-os-partner:31106
BRANCH=None
TEST=Built and booted.
Change-Id: I4a0bc034fe4f648b73ebf6389d8669fe15db1d8f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5f2af2e32903b3df64f3f25a42fb42b0b629152c
Original-Change-Id: I68c138b428abbd0c9bc60be0cfc70681528d7728
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/215542
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9027
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The kernel doesn't have the logic for bringing up the plld.
Therefore, configure it in the firmware. The clock used
is an interim value until the display controller sequencing
is fully implemented.
BUG=chrome-os-partner:31640
BRANCH=None
TEST=Noted configured freq is close to requested. Also, no
more plld errors observed from the kernel.
Change-Id: I0788c83843699ec7cef52b3a219ebb9b0db9082f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b44956ec87e9083aebe589349cbe168f7f101d8b
Original-Change-Id: I6f57d5c48630385d1814e7ef61898a2d49c8f747
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214841
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9026
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Depending on the requested frequency the plld cannot
necessarily obtain the exact clock. Therefore provide the
closest configured frequency as a return value. This is
equivalent to the t124 patch.
BUG=chrome-os-partner:31640
BRANCH=None
TEST=Built and noted plld actual value close to requested.
Change-Id: I9aaba81222fb97d9fbbb4156af3a7476ba654c10
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fc928db8197b465220e53b4d0ba5896b3c06a863
Original-Change-Id: I94b94a1bf01087ff0d0e4b1ef3fb59eec2a8ba15
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214843
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: http://review.coreboot.org/9025
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
With the latest changes to include stack storage within ramstage, we no longer
need to define Kconfig options for ramstage/exception stacks in arm64.
BUG=None
BRANCH=None
TEST=Compiles successfully and boots to kernel on ryu
Change-Id: I7361d8f567453e775240151fd1180c49025141b3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9aaa89115a67606fcb66eb354741043f7f2094bf
Original-Change-Id: I93c23ac3fa9adab4eac3c739023cbae3e5135497
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/214607
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9023
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
These symbols should have been removed with the stack
refactoring. I'm not sure how it was missed.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and booted into kernel with both cpus.
Change-Id: Ia6c2103d7b5e2c9d74cdc5d1b5f42f8954812231
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d9432b5cf0cce3bfdbfd5371fb3280e3cc746a42
Original-Change-Id: I17bc9a7aaaf133f427b15f803a6003fa2ca8f8a6
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/215541
Reviewed-on: http://review.coreboot.org/9024
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Instruct the SoC to bring up the 2nd core.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Brought up 2nd core in Linux.
Change-Id: I4b31ea5f1466c43abce273b2bfb6a4d06b7faa63
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 74c62e62a6790de65e303123abee2be1dfffbee3
Original-Change-Id: I5f5febc4719951188106041f73625231eafe1b08
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214778
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9022
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Until PSCI is functional the other core still needs to be
brought up in the kernel. The kernel boots these cpus with
the spin table which is just an address in memory to monitor
a jump location.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and brought up secondary core in linux.
Change-Id: Iaa69110f6a647d8fd4149119d97db4fc45d7da00
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 01ca36685852bc5dd85fd4015c8a1e600e23e7ca
Original-Change-Id: Ieaf19cd70aff3e6c8de932e04b1b5aba71822a97
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214777
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9021
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Optionally bring up secondary cpu according to devicetree.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and enabled bringing up second core on ryu.
Change-Id: I5ede8b2f1b30a6170520cc11c18e263793cea301
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d7da2dcce9be653a3c551c33bbefb3810a6949e9
Original-Change-Id: Ia3f2c10dab2bbfd65ba883451bf4eafc26f2e7cf
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214776
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9020
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Provides a minimal API for coordinating with the SoC for
bringing up the secondary CPUs. There's no eventloop or
dispatcher currently nor does it do anything proper when
one of the secondary CPUs are brought up. Those decisions
are deferred to the SoC.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and brought up 2nd cpu using this API.
Change-Id: I8ac0418282e2e5b4ab3abfd21c88f51d704e10f9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5303ae3d6bfc9f8f908fcb890e184eb9b57f1376
Original-Change-Id: I3b7334b7d2df2df093cdc0cbb997e8230d3b2685
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214775
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9019
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
For the secondary CPUs the set of banked registers needs to be
initialized. In the boot CPU path all both the CPU's banked
registers and the global register set is initialized.
BUG=chrome-os-partner:31545
BRANCH=None
TEST=Built and brought up 2nd cpu in kernel.
Change-Id: I3a7bc708f726c4435afca817a251790f536844d9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 813b0a8b3faacf2342164d385e5837ebede29b18
Original-Change-Id: Ie5db56ca052eebac4ed1a34eaeeb6bbd8a26ca30
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214774
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9018
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Furquan Shaikh